Interrupt Handling

INTERRUPT HANDLING
INTRODUCTION

Very often something happens which necessitates precipitate action from the processor. The vast majority of MCUs have the capability to deal with a range of such events that disrupt their smooth running. Requests for service may come from an internal peripheral device, such as a timer overflowing, or the completion of an analog to digital conversion, or from a source entirely external to the device in the outside world. At the very least, on reset, the MCU must be able to get to the first instruction of the main program. A service request or interrupt when answered must lead to the start of the special subroutine known as an interrupt service routine.

INTERRUPT SERVICE ROUTINE

Essentially signalling an interrupt causes the PIC to drop whatever it is doing, save its position in the interrupted program and go to a special subroutine known as an Interrupt Service Routine (ISR). This program is just a subroutine entered when an interrupt occurred.

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Interrupt Handling

The PIC16F84A will respond to service requests from four sources. 1. An external signal at pin 6 which is labelled INT in this context, but doubles as the Port B bit 0 RB0 pin. The request may be activated optionally by either a rising edge or a falling edge at this input. An input change at any of the top four Port B pins since the last read of this port. By the Timer counter TMR0 overowing FF 00h. When an internal Data EEPROM write-to action has been completed.

2. 3. 4.

The following is the PICs response to such an event. Essentially the sequence is:

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Interrupt Handling

1.

The processor samples the interrupt line once in each instruction cycle. If this line is active a latch is set otherwise it is cleared. This latch is called the interrupt flag. Irrespective of the state of this line, the current instruction is always completed. If the interrupt flag is not active, the PIC simply continues on into the next instruction cycle and the process is repeated. If both the interrupt flag is set and bit 7 of the INTCON special purpose register is clear, the next three instruction cycles are involved in moving execution to the interrupt service routine, although the first of these may be the final cycle of a 2-cycle instruction otherwise a dummy cycle, plus two more cycles to flush the pipeline. This 3 to 4-cycle delay from the instant of the hardware INT signal and beginning the execution of the first instruction of the ISR is known as latency. During this latency period the PIC does three things: a.) Bit 7 of the INTerrupt CONtrol register (INTCON) is zeroed. This bit is labelled as General Interrupt Enable (GIE). Once GIE is cleared all further requests for interrupts from whatever source are locked out, so an interrupt service process cannot be further interrupted.

2.

3.

4.

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Interrupt Handling

b.)

The state of the 13-bit Program Counter is pushed into the hardware stack in exactly the same manner as for a call instruction. The first instruction of the ISR is always in location 004h in the Program store. Thus the final step of the sequence is to overwrite the PC with this instruction address, known as the Interrupt vector.

c.)

5.

Like a subroutine, an ISR must be terminated by a Return instruction. However, in this case not only has the PC to be pulled out of the hardware stack to move execution back to the interrupted program but the GIE bit in the INTCON register must be set to re-enable the interrupt capability. The Return instruction relevant to this situation is retfie (RETurn From Interrupt and Enable).

An ISR differs from a subroutine in more subtle ways than the use of the retfie instruction. Some of these differences relate to the logic of the interrupt system and some are due to the pseudo random nature of the interrupts.

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Interrupt Handling

Each of the four PIC16F84A interrupt sources interact with the processor via two associated control register bits. The flag bit is set when the related source device requests service. If the local mask bit is 1 then the request will go forward to the next layer of interrupt logic. The local mask bit can be written to in the normal way by software. On reset, it is zeroed and thus the interrupt from the affiliated source disabled. The ISR must clear it before return to cancel the request otherwise an endless series of interrupts will occur. This is because on return the interrupt flag will still be set and another interrupt will immediately be set in train. As there are four sources of interrupt, each flag:mask AND gate must be ORed to give a composite request signal, which when active initiates the CPUs interrupt response. This ORing process is further gated with the Global mask bit GIE, which is located in bit 7 of INTCON.

FEU -East Asia College

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Interrupt Handling

FEU -East Asia College

M I P S Y S 2 - CpE Department

Interrupt Handling

As there is only one common interrupt vector, then one of the first tasks the ISR has to do is check which peripheral is calling for help. All interrupt flags can be polled until the one that is set is found. Based on this approach a typical polling sequence could be:
bsf STATUS,RP0 btfsc INTCON,1 goto EXTERNAL btfsc INTCON,2 goto TIMER0 btfsc INTCON,0 goto CHANGE_B btfsc EECON1,4 goto EEPROM_WR IRQ_EXIT bcf STATUS,RP0 retfie ; Return to Bank 0 registers ; and return ; ; ; ; ; ; ; ; ; Change to Bank 1 registers Check for external interrupt IF set THEN go to INT handler Check for Timer0 interrupt IF set, go to TMR0 handler Check for change at PortB int IF set, go to correct handler Check EEPROM write-to inter IF set, go to EEPROM handler

The order of polling gives a priority level if more than one interrupt request should coincide. Thus if both the external hardware and Timer 0 interrupts are active, the former will be processed first. In this case, on return the pending Timer 0 interrupt requests will then be processed. In all instances the appropriate interrupt flag should be cleared, otherwise the interrupt will be generated indefinitely.

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Interrupt Handling

Where masks are set, this same polling technique can be used to check on the status of events without using the PICs interrupt processes. For example, when a byte is written to the Data EEPROM the program typically checks the state of EEIF (bit 4 of EECON1) until it is set, then clears it and continues on.
W_LOOP btfss EECON1,EEIF ; Check state of the EEIF flag goto W_LOOP ; IF still zero THEN try again ; ELSE continue after clearing the write-to EEPROM flag bcf EECON1,EEIF

Interrupts happen randomly as viewed by the software and thus, unless masked out, may happen at any part of the program, including in the middle of a subroutine. An ISR routine uses the internal processor registers in the same way as any other software, so conflict over such resources will exist. All but the most elementary ISR will need to, at the very least, save the STATUS and Working registers. Generally the programmer sets aside two File registers as temporary storage and for no other use. Then just before the execution of the retfie instruction, the STATUS and Working registers should be restored with its original value. This process of saving and restoring the state of internal registers on entry and exit is known as context switching.

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Interrupt Handling

In conclusion, ISRs are similar to subroutines, but keep in mind the following points: The ISR should be terminated by retfie instead of return. Any SPRs that are to be altered should be saved on entry and retrieved on exit. Parameters cannot be passed to and from the ISR via the Working register. Instead, global variables (data in known memory locations) should be used as required. ISRs should be as short as possible, with minimal functionality. This helps in debugging, and helps ensure that other events are not missed.

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Interrupt Handling

Example In a food processing factory, cans of baked beans on a conveyer belt continually pass through a tunnel oven, where the contents are sterilized. Photocell detectors are used to sense cans, both entering and leaving the oven. The output of the sensors are logic 1 when the beam is broken. You are asked to design an interrupt-driven interface for this system, combining the two signals to activate the PICs one INT input. A buzzer connected to Port Bs bit RB0 is to be sounded if the number of tins in the oven exceeds four, indicating that a jam has occurred.

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