Institute of Engineering Studies

Digital Electronics

Problems to be solved
1. Consider the logic circuit shown in the figure below:

The functions f1, f2 and f (in canonical sum of products form in decimal notation) are:

the function A) C)

is B) D) can be either B or C

2. Consider the following circuit with XOR gates and non inverting buffers :

the non inverting buffers have delays d1= 2 ns and d2 = 4 ns as shown in the figure. Both XOR gates and all wires have zero delay. assume that all gate inputs, outputs and wires are stable at logic level 0 at time 0. If the following waveform is applied at input A, how many transitions (change of logic levels) occur at B during the interval from 0 to 10 ns?

A) 1 C) 3

B) 2 D) 4

3. In the SR latch made by cross coupling two NAND gates, if both S and R inputs are set to zero, then it will result in: A) Q=0, Q'=1 C) Q=1, Q'=1 B) Q=1, Q'=0 D) Intermediate/ Unstable states

4. Consider the following circuit:

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Institute of Engineering Studies

Digital Electronics

Which statement of the following is true A) F is independent of X C) F is independent of Z B) F is independent of Y D) None of the X, Y, Z is redundant

5. What will be the binary string generated if output is taken at QB and 6 clock pulses are applied, assuming intial state is 110 (State S6)

A) C)

1001001 1001100

B) D)

1010010 None

6. For a synchronous MOD 16 counter using T flipflops, if the time delay per flip flop tflipflop is 20 ns, and the time delay per AND gate tcombinational is 5 ns, what should be the maximum clock frequency which can be used so that counter operates as expected A) 66.66 MHz C) 28.57 MHz B) 33.33 MHz D) 50 MHz

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Institute of Engineering Studies

7. What is the Modulus of following synchronous sequential circuit (Assume that X = 0):

Digital Electronics

A) MOD 2 C) Either A or B

B) MOD 1 D) None

8. You are given a free running clock of duty cycle of 50% and a digital waveform f which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip flops) woll delay the phase of f by 180
o

9. Consider the following circuit involving a positive edge triggered D flip-flop:

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Institute of Engineering Studies

Digital Electronics

Consider the following timing diagram:

Lets A' represent the complement of A. The correct output sequence on Y over the clock periods 1 through 5 is: A) A0A1A1'A3A4 C) A1A2A2'A3A4 B) A0A1A2'A3A4 D) A1A2'A3A4A5'

10. The Minimized expression for the following K Map is

A) (Y+Z) (Y'+Z') (W'+X) C) (X+Y'+Z') (W'+X+Y') (W'+X'+Y+Z)(W+X+Y+Z)

B) (X+Y'+Z') (W'+X+Y') (Y+Z) D) (Y+Z) (Y'+Z') (W+X')

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