Illinois Scan Architecture

Janak H. Patel Center for Reliable and High-Performance Computing University of Illinois at Urbana-Champaign jhpatel@uiuc.edu

Cost of a Chip
300mm wafer will give 700 ~1cm2 chips Material Costs (wafer, copper etc) ~5% Fab amortization cost ($3B/fab) plus Fab operational cost ~25% Personnel cost ~20% Package Cost ~10%

Testing Cost ~40% !!!

2005 Janak H. Patel

Cost of Testing Semiconductor Chips

Three main variable components Test Application Time
When amortizing the cost of a tester over all chips, higher test time results in to higher actual cost Rule of thumb: 1 second per chip!

Example: An IBM chip

7million gates (logic only, RAM not included) 250k Flip-Flops Full Scan design, all FFs connected as shift register
Scan in
250,000 ffs

Test Data Volume

Low and medium cost testers have limited storage

Scan out

Tester Pins
Cost of a tester is directly proportional to the number of pins it supports

7000 Test Vectors Test Application Time: 7000x250k = 1.75G cycles at 100MHz scan speed it takes 17.5 Seconds! at 500MHz scan speed it takes 3.5 Seconds Tester memory required: 7000x250k = 1.75G bits
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Parallel Scan
1000 Parallel Scan Chains by 250 FFs

Parallel Scan Output Compaction

100 Parallel Scan Chains by 2500 FFs

output compactor

Scan-in

Scan-out
Scan-in

1000 scan-in pins!

1000 scan-out pins!

A Combinational Compactor is a tree of XOR gates

Reduces Test Vector Load time by a factor of 1000!

Scan Channels on a Tester range from 10 to 200

A Sequential Compactor is a Linear Feedback Shift Register with multiple parallel inputs XORed. Also called a Multiple Input Signature Analyzer (MISR) 6

Parallel Scan - Summary

Scan loading time can be reduced by dividing the single scan chain in to parallel scan chains

Test Vector Compaction

For example, all 40 ISCAS 85 and ISCAS89 (full scan) circuits, sizes of the test sets generated by MinTest
(Hamzaoglu and Patel, ICCAD 1998, pp. 283-289) meets

Some Observations Output Compaction is well established Number of scan chains is limited by the availability of pins on a chip and tester scan channels Additional pins on an embedded core require more routing in the SOC Parallel Scan has no impact on test data volume
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Lower bounds for 31 out of 40 ISCAS circuits. This shows that Compaction has already reached theoretical lower bounds in many instances So we must look for other solutions beyond vector compaction

Test Vectors Lower Min Circuit Bound Test C432 27 27 C5315 37 37 C7552 S1196 S1423 S5378 S38714 65 113 20 97 62 73 113 20 97 68

BIST: STUMPS Architecture

P. H. Bardell and W. H. McAnney, Self-Testing of Multichip Logic Modules, Proc. Of Int. Test Conf., pp. 200-204, Nov. 1982. (used by IBM for multi-chip-modules)

Limitations of Logic BIST

BIST is excellent for Data Volume Reduction, But Lower Fault Coverage. Test Point insertion and/or additional logic in test generator is required to cover Random Resistant Faults Design Modification needed to permit any arbitrary test pattern
Tri-State logic must be fully decoded No floating bus is permitted, since unknown values can corrupt the signature Switching activities of various modules, and hence the power, cannot be easily controlled

Scan Chain

LFSR

MISR

Scan Chain Scan Chain Scan Chain

Linear Feedback Phase Shift Shifter Register

Circuit Under Test

Multiple Input Signature Register

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This has the same limitations as any other BIST based scheme

Will almost always increase the tester time! Failure Diagnosis becomes extremely difficult
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Proposed New Method

Illinois Scan Architecture Applicable to full-scan embedded cores and fullscan stand-alone chips Addresses all issues raised earlier Low test application time, low pin overhead, and low test data volume
Scan in

Illinois Scan Architecture

Take a Serial Scan Scan out

1. Divide it up into several chains keeping the same Scan-in pin 2. Add a MISR to compact the outputs Scan in
MISR
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Does not have any of the limitations of the BIST No test point insertions and No design modifications! Undesirable test vectors can be filtered, e.g., Vectors that produce Tri-State Conflicts, Unknown value generation, or High switching activity

Scan out

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Illinois Scan
Internal Scan Chains
scan in

Untestable Faults in Illinois Scan

0 1 0 1 0 1

Scan-in pin

In the figure shown on left, all three scan chains will have identical test vectors Therefore, only applicable test vectors are 000 and 111 for the AND gate Test vectors 100, 010 and 001 cannot be applied due to Broadcast constraint This makes three faults on the AND gate Untestable

Output Compactor

In practice, how serious is this problem? How many faults become untestable?
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Additional Untestable Faults

Illinois Scan puts constraints on inputs Cannot generate tests for some of the faults that are testable under normal scan The number of such Additional Untestable Faults is surprisingly small even for arbitrary partition! Experimental Data for Scan Chain divided into 16 chains (arbitrary partition), with a single scan input
1200 Untestable Faults 1000 800 600 400 200 0 ILS-13207 ILS-15850 ILS-35932 ILS-38417 ILS-38584

Two Test Modes of Illinois Scan

1. Broadcast Test Mode
Scan In Scan Chain 1

2. Serial Test Mode

Scan Chain 1

MISR

Scan Chain 2 Scan In

Scan Chain 2

MISR

Scan Chain n

Scan Out Scan Chain n

Scan Out

1. Reduces Scan Time by a factor of n 2. Reduces Scan Data by a factor of n But may require many more vectors and may reduce fault-coverage!
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Mode 2 Used for covering the loss of fault-coverage in the Broadcast Mode Generates top-off vectors.
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Number of Test Vectors

400 350 300 250 200 150 100 50 0
fs13207 scan vectors broadcast vectors
200,000 175,000 150,000 125,000 100,000 75,000 50,000 25,000
Cy c l s e

Number of Test Cycles

scan cycles broadcast cycles

Vectors

fs15850

fs35932

fs38417

ILS-13207

ILS-15850

ILS-35932

ILS-38417

fs38584

ILS-38584

0 fs13207 fs15850 fs35932 fs38417 ILS-13207 ILS-15850 ILS-35932 ILS-38417 fs38584

Ci ut c i r

Circuit
Circuit Versions: fs = full scan, and ILS = Illinois Scan, DIV16
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Circuit Versions: fs = full scan, and ILS = Illinois Scan, DIV16

ILS-38584
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Illinois Scan Data Volume

450,000 400,000 350,000 300,000

Illinois Scan
internal scan chains

Scan Test Data Broadcast Test Data

Data Bits

250,000 200,000 150,000 100,000 50,000 0

scan-in pin

output compactor
ILS-arb ILS-arb ILS-arb ILS-arb fs13207 fs15850 fs35932 fs38417 fs38584 ILS-arb
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Circuit

Circuit Versions: fs = full scan, and ILS = Illinois Scan, DIV16

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Illinois Scan with multiple pins

internal scan chains

Case Study at Texas Instruments

Original Circuit : 150K logic gates, 9300 scan flip-flops 910 Scan Vectors, 94.25% stuck-at fault coverage
Illinois Scan Version Serial Broadcast Additional Scan Broadcast Fault Untestable Vectors Vectors Coverage Faults needed Data Serial Broadcast Volume Scan Vectors Reduction Fault Factor Coverage needed

external scan-in pins output compactor

DIV16 DIV24 DIV32

15,000 14,000 12,000

94.08% 94.09% 93.87%

733 692 1565

53 38 59

70% 67% 73%

9700 9500 8000

1.4 2 3

Similar reduction was also found in Transition Fault Data

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Frank Hsu, Ken Butler and Janak Patel, A Case Study on the Implementation of the Illinois Scan Architecture, Int. Test Conf. Oct. 2001

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IBM Data using Illinois Scan (OPMISR+)

Gate Count Scan flip-flops Test Time Reduction Test Volume Reduction

Intel Data on Illinois Scan

From a Paper by D. Wu et. al. of Intel, published in 2003 Int. Test Conf. The first test chip has 81 scan-in and 81 scan-out channels, we use Illinois Scan with 4 scan-in and 81 scan-out. The results are quite surprising: both methods got the same test coverage. We have implemented Illinois scan into one of the microprocessors, but the silicon results will not be ready for the timing of this years ITC.

Design

Chip1 Chip2 Chip3* Chip4*

1.7M 2.1M 715k 1.2M

230k 31k 41k 65k

130x 38x 7x 8x

200x 54x 21x 12x

* These chips already had their scan divided by customer

.scan fan-out, which is sometimes informally referred to as Illinois Scan [ix]. In the Cadence ATPG tools we refer to this as OPMISR+.
Data and quote From: Test Compression Methods in Cadence Encounter Test Design Edition, Technology Application Note, December 2003 23 24

More Data on Illinois Scan

7M Gates, 250k flip-flops, 7000 test vectors

Illinois Scan in CAD Tools

Cadence (formerly IBM) Illinois Scan on their patented OPMISR is called OPMISR+ Syntest Illinois Scan is called Virtual Scan Synopsis ATPG Tools understand and support Illinois Scan Mentor Graphics No Illinois Scan! Proprietary tool called TestCompress
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Source: V. Chickermane, B. Fautz and B. Keller, Channel-Masking Synthesis for Efficient On-Chip Test Compression, Int. Test Conf., 2004.

Illinois Scan with multiple pins

Large Industrial Circuits have used Illinois Scan with multiple pins IBM ASIC-4 chip (Design and Test, Sept. 2002, pp. 65-72)
1.14 million gates, 46 pins, 269 internal chains

Optimal Grouping of Chains

scan-in pins scan chains

Intel chips (Int. Test Conf., Sept. 2003, pp. 1229-1238)

ASIC-1, 4 pins, 81 internal chains ASIC-2, 4 pins, 96 internal chains Next generation microprocessor (no data given)

All of the above scan-chain groupings are ad-hoc! Objective: Minimize number of Scan-In Pins without loss in fault coverage.
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Compatibility among Chains

Compatibility between two scan cells Two inputs (scan cells) are compatible if and only if no fault becomes untestable as a result of tying the two cells to a single input (Chen&Gupta, ITC 1995) Compatibility between two scan chains Two chains are compatible if and only if every pair of scan-cells that receive the same broadcast value are compatible (Hamzaoglu&Patel, FTCS 1999)
Determination of all pair wise compatibilities is computationally very expensive Resort to an inexpensive algorithm which gives a subset of all compatible pairs
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Incompatibilities from a Test Set

A Partially Specified Test Vector, 20-bits long folded on to 5 chains
Chain

001x 0xx1 x01x 0011 xx11

No conflicting values found

0 0 x 0 x 0 0 x 0 x

0 x 0 0 x 0 x 1 0 x

1 x 1 1 1 1 x 1 1 1

x 1 x 1 1 x 1 x 1 1

a b c d e a b c d e
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001x 0xx1 x11x 0011 xx11

Chains a and c are incompatible, so are chains c and d

Example of Chain Grouping

Given Incompatible Pairs: AB, AD, AG, BD, BE, BF, CE, CF, EF, EG, EH, FH Construct a Graph with Nodes=Chains and Edges=Incompatibility
A B C
A B C

Dual-mode Illinois Scan

A B C D E F G H A B C D E F G H

D E F

H
Conflict-free Chain Grouping

G H

Single Pin Broadcast Mode

Group Mode

Perform Graph Coloring Algorithm

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Some Results on Pin Reduction

Circuit no. of Chains no. of Pins Reduction Factor

Illinois Scan: Summary

A simple DFT technique, ideal for reducing test costs for large chips Significant reduction in test application time, test data and test pins without loss in fault coverage Even a dumb partition is very effective! For very large chips, 200 fold reduction is likely! Things should be made as simple as possible, but not any simpler Albert Einstein

s13207.1 s15850.1 s38417 s38584.1

64 107 54 89 52 82 90 119

8 9 7 11 5 7 7 8

8.0 11.8 7.7 8.0 10.4 11.7 12.8 14.8

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More information on Illinois Scan

1. I. Hamzaoglu and J.H. Patel, Reducing test application time for full-scan embedded cores, Proc. 29th Int. Symp. On Fault-Tolerant Computing (FTCS-29), pp.260-267, June 1999 2. F. Hsu, K. Butler and J.H. Patel, A case study on the implementation of Illinois Scan Architecture, Proc. Int. Test Conf. pp. 538-547, October 2001 3. A.R. Pandey and J.H. Patel, An incremental algorithm for test generation in Illinois Scan Architecture based designs, Proc. Of Design Automation and Test in Europe (DATE), pp. 368-375, March 2002. 4. A.R. Pandey and J.H. Patel, Reconfiguration techniques for reducing test time and test data volume in Illinois Scan Architecture based designs, IEEE VLSI Test Symp. (VTS), pp. 9-15, April 2002. 5. M.A. Shah and J.H. Patel, Enhancement of the Illinois Scan Architecture for Use with Multiple Scan Inputs, IEEE Computer Society Annual Symposium on VLSI, pp. 167-172, Feb. 2004.

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