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# Assignment

Q:1) Explain the decimal number system with an example. And give the general polynomial representation of a number. A:) The decimal number system is the most commonly used number system because of its ease of use. We can express any decimal number in units, tens, hundreds, thousands and so on. It has radix 10 (i.e. base). In decimal number system, the base or radix is 10 i.e. there are ten digits which we can use. They are: 0,1,2,3,4,5,6,7,8,9. Eg: 59.79 is a decimal number. Its polynomial representation is: 5*10^1+9*10^0+7*10^-1+9*10^-2 In general, polynomial representation of any number in any system is: N = a(n-1)*r^(n-1)+a(n-2)*r^(n-2)++a(1)*r^1+a(0)*r^0+a(-1)*r^-1+ +a(m)*r^(-m) Where N=number in decimal a=digit r=radix or base n=number of digits in integer portion m=number of digits in fraction portion

Q:2) Explain the decimal to binary conversion up to 4 binary places. (47.8125)10. A:) To convert a decimal number whose radix is 10 to binary number of radix 2, we convert the whole number part of the decimal number first to binary by repeated division by 2 in base 10 and keeping track of the remainder. The fractional part of the decimal number is converted to binary by repeated multiplication by 2 in base 10 and keeping track of resulting whole number part of the answer until required number of binary places. To get whole number part, we read binary number upwards. To get fractional part, we read binary number downward.

## Binary of whole no. part is:

2 47 2 23 1 2 11 1 2 5 2 2 2 1 0 1 1 0 1

Thus (47)10 = (101111)2 Fractional part: 0.8125 2*0.8125=1.625=0.625 carry 1 2*0.625=1.25=0.25 carry 1 2*0.25=0.5=0.5 carry 0 2*0.5=1=0 carry 1 Thus (0.8125)10 = (0.1101)2 Therefore (47.8125)10 = (101111.1101)2

Q:3) Convert binary to: a) 110101 to decimal 110101 = 1*2^5+1*2^4+0*2^3+1*2^2+0*2^1+1*2^0 =32+16+0+4+0+1 =53 Thus (110101)2 = (53)10

b) 1110.01101 to octal

## (1110.01101)2 = (001 110 . 011 010)2 = (1 6 . 3 2)8 Thus (1110.01101)2 = (16.32)8

c) 1011101.110111 to hexadecimal (1011101.110111)2 = (0101 1101 . 1101 1100)2 = (5 D . D C)16 Thus (1011101.110111)2 = (5D.DC)16

Q:4) Convert octal to decimal a) 426.73 (426.73)8 = 4*8^2+2*8^1+6*8^0+7*8^(-1)+3*8^(-2) = 256+16+6+0.875+0.046875 = (278.921875)10 b) 124.21 (124.21)8 = 1*8^2+2*8^1+4*8^0+2*8^(-1)+1*8^(-2) = 64+16+4+0.25+0.015625) = (84.265625)10 c) 0.65 (0.65)8 = 0*8^0+6*8^(-1)+5*8^(-2) = 0+0.75+0.078125 =(0.828125)10

## Q:5) Convert decimal: 1) To octal: a) (847.951)10

8 847 8 105 7 8 13 8 1 0 1 (847)10 = (1517)8 And 0.951*8 = 7.608 = 0.608 carry 7 0.608*8 = 4.864 = 0.864 carry 4 0.864*8 = 6.912 = 0.912 carry 6 0.912*8 = 7.296 = 0.296 carry 7 and so on.. Thus (847.951)10 =(1517.7467)8 b) (0.728)10 0.728*8 = 5.824 = 0.824 carry 5 0.824*8 = 6.592 = 0.592 carry 6 0.592*8 = 4.736 = 0.736 carry 4 0.736*8 = 5.888 = 0.888 carry 5 and so on.. Thus (0.728)10 = (0.5645)8 2) To hexadecimal a) 2604.10546875 16 2604 16 162 16 10 0 10 (2604)10 = (A2C)16 And 0.10546875*16 = 1.6875 = 0.6875 carry 1 0.6875*16 = 11.00 = 0 carry 11 12 2 1 5

Thus (2604.10546875)10 = (A2C.1B)16 b) (64026)10 16 64026 16 4012 16 250 16 15 0 15 Thus (64026)10 = (FACE)16 14 12 10

Q:6) Explain the process of binary subtraction: a) Subtract ((100.111)2 from (110.101)2 110.101 - 100.111 0 0 1 . 1 1 0 ans: (1.11)2 (positive)

b) Subtract (1011.11)2 from (101.1)2 1011.11 -0 1 0 1 . 1 0 0010.01 ans: (-10.01)2 (as we have subtracted in reverse order)

Binary subtraction can be done by using the following rules: (It is similar to that of decimal numbers. If the borrow is 0, difference is positive, & if borrow is 1, difference is negative). A 0 0 1 1 B 0 1 0 1 Difference 0 1 1 0 Borrow 0 1 0 0

Q:7) Perform binary subtraction using 1s complement and 2s complement method for: 1) 101.111 from 10.0101 a) Is complement: 1s complement of larger number: (101.111)2 = (010.000)2 010.0101 +0 1 0 . 0 0 0 0 1 0 0 . 0 1 0 1 = (100.0101)2 Answer is in ones complement form: Answer : (-11.1010)2 (1s complement with negative sign)

b) 2s complement: 2s complement of larger number : (101.111)2 = (010.000)2 + 1.000 = (11)2 10.0101 +1 1 . 0 0 0 0 101.0101 Now, answer is in 2s complement form. Answer : (-011.101)2 (2s complement wit negative sign)

2) 1101 from 110 a) 1s complement: 1s complement of larger number: (1101)2 = (0010)2 110

## +10 1000 Answer in 1s complement form. Thus answer = (-111)2

b) 2s complement: 2s complement of larger number: (1101)2 = (10)2 + 1 = (11)2 110 +11 1001 Answer in 2s complement form. Answer = (-111)2

Q:8)What are binary coded decimal numbers? Represent the following decimal numbers in BCD: (a) 821 (b) 35.67 A:) Binary coded decimal number or BCD, is numeric code in which each digit of a decimal number is represented by a separate group of bits. The most common BCD code is 8-4-2-1 BCD code, in which each digit of decimal number is represented by a 4-bit binary number. 8-4-2-1 BCD code is given as follows: BCD Code 8 4 0 0 0 1 0 0 2 0 0 3 0 0 4 0 1 5 0 1 6 0 1 7 0 1 8 1 0 9 1 0 (positional weights bit 3 has weight 8, bit 2 has weight 4, 0 has weight 1) a) 821 = 1000 0010 0001 Decimal Digit 2 0 0 1 1 0 0 1 1 0 0 bit 1 has weight 2 1 0 1 0 1 0 1 0 1 0 1 and bit

## b) 35.67 = 0011 0101 . 0110 0111

Q:9) Explain the logical AND operation and also the construction of an AND gate using diode. A:) Logical AND operation can be performed for two or more inputs to get one output. We will get output as high only when all the inputs are high. Eg: If A & B are inputs and Y is output, then Y is high only when A & B both are high Truth table: A 0 0 1 1 (Symbol in Boolean for AND is .) Symbol used for AND gate is: B 0 1 0 1 (A.B) Y 0 0 0 1

## B Circuit diagram of AND gate using diodes: +V cc

A Y=A+ B

We can construct AND gate using diodes. Number of diodes used is equal to the number of inputs used. For two input AND gate. Circuit diagram is shown below:

## Working of this gate can be explained as follows:

Case 1: A is LOW & B is LOW: Here, both D1 & D2 diodes are forward biased and both cathodes are grounded. Thus, output obtained Y is LOW. Case 2: A is LOW & B is HIGH: Here, D1 is forward biased & D2 is reversed biased and cathode of D1 is grounded. It (D1) pulls the output (Vcc) voltage towards it and hence output Y is low. Case 3: A is HIGH & B is LOW: Here, D1 is reversed biased, and D2 is forward biased and cathode of D2 is grounded. Hence D2 pulls the output (Vcc) voltage towards it and hence output Y is low. Case 4: A is HIGH & B is HIGH: Here both D1 and D2 are reversed biased. Both diodes will not conduct and hence output Y is high.

Q:10) Explain the construction of a transistor based NOT gate. A:) A NOT gate can be constructed using a transistor(n-p-n). The truth table for NOT logic is: Input Output 0 1 1 0 A NOT gate is also called inverter operator. It will reverse the input given to it (as shown in truth table). Circuit diagram:

+Vc c

R Y

Case I: When A is low: Here resistance drop across resistor R will not be full 5V as no collector current will flow. Hence output Y will be HIGH. Case II: When A is high: Here resistance drop across resistor R will be full 5V as collector current flows. Hence, output Y will be LOW. Symbol for NOT:

Q:11) Name the universal gates and why are they called so? A:) There are two logical universal gates. They are: (1) NAND gate(NOT-AND gate)

(2) NOR gate(NOT-OR gate) These two gates are called so because these gates can be used to construct any other logic i.e. AND, OR, NOT or any other combination of the given logics. The truth tables for the two universal gates are: NAND A 0 0 1 1 B 0 1 0 1 Y 1 1 1 0 NOR

A 0 0 1 1

B 0 1 0 1

Y 1 0 0 0

Q:12)Prove the following Boolean identities using Boolean theorems and truth tables. (a) A+BC = (A+B)(A+C) LHS : A+BC =A(1+C)+BC =A+AC+BC =A(1+B)+AC+BC =A+AB+AC+BC =AA+AB+AC+BC =A(A+B)+C(A+B) =(A+C)(A+B) (Distributive property) (As 1+C=1) (Distributive property) (As 1+B=1) (Distributive property) (AA=A)

= RHS

Hence proved

## -Truth table: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 BC 0 0 0 1 0 0 0 1 A+BC 0 0 0 1 1 1 1 1 A+B 0 0 1 1 1 1 1 1 A+C 0 1 0 1 1 1 1 1 (A+B) (A+C) 0 0 0 1 1 1 1 1

(b) ABC+ABC+ABC = AB+AC LHS = ABC+ABC+ABC =AC(B+B)+ABC =AC(1)+ABC =AC+ABC =A(C+BC) =A(C+B) =AB+AC = RHS (Distributive property) (As B+B=1) (As AC.1=AC) (Distributive property) (As C+BC=C+B) (Distributive property) Hence proved

## -Truth table: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 B 1 1 0 0 1 1 0 0 C 1 0 1 0 1 0 1 0 AB C 0 0 0 0 0 0 0 1 AB C 0 0 0 0 0 1 0 0 AB C 0 0 0 0 0 0 1 0 (ABC+ABC+ ABC) 0 0 0 0 0 1 1 1 AB 0 0 0 0 0 0 1 1 AC 0 0 0 0 0 1 0 1 (AB+AC) 0 0 0 0 0 1 1 1

Q:13) Simplify and realize the following Boolean expressions using logic gates: (a) Y= ((BC)+(AD)((AB)+(CD))) =(BC).((AD)((AB)+(CD))) =BC.((AD)+((AB)+(CD))) =BC.(AD+((AB).(CD)) =BC.(AD+(AB.CD)) =ABCD+(ABCD)(BC) =ABCD+ABCD =ABCD (Distributive property) (As ABCD.BC=ABCD) (De Morgans theorem) (De Morgans theorem) (De Morgans theorem)

A B C D

Y=ABC D

A B A

AB

A C Y

C B C

## Using logic gates:

A Y B C

Q:14) Simplify the expression and implement using only NAND gates and only NOR gates: (a) XYZ+YZ+Z =(X+1)YZ+Z =1.YZ+Z =YZ+Z =Y+Z Using NAND gates: Y O Z X (as 1.YZ=YZ) (as YZ+Z=Y+Z) (Distributive property)

## Using NOR gates:

(b) ((A+B+C)(A+B+C)(A+B)) =(((A+B+C)A+(A+B+C)B+(A+B+C)C)(A+B)) property) =((AA+AB+AC+AB+BB+BC+AC+BC+CC)(A+B)) (Distributive property) =((0+AB+AC+AB+0+BC+AC+BC+C)(A+B)) =((AB+AB+C(A+A)+C(B+B)+C)(A+B)) property) =((AB+AB+C)(A+B )) & B+B=1) =((AB+AB+C)A+(AB+AB+C)B) property) =(AB.A+AB.A+AC+AB.B+AB.B+BC) =(0+AB+AC+0+AB+BC) =(AB+BC+AC) =(AB+BC).(AC) =(AB)(BC)(AC) -> For NAND -> For NOR (Distributive (as A+A=1, C.1=C (Distributive (Distributive

A B C

(AC )

## Using NOR gates: A B

A B B C C A

B C

A C

Q:15) Draw the output waveform and truth table of logic circuit for input waveform: A B C

A B C Y

A:) Given logic circuit has equivalent Boolean expression: Y=((AB)+C) =(A+B+C) =(A+B).C =A.B.C Truth table : A 0 1 0 1 0 1 0 B 0 1 1 0 0 1 1 C 0 0 1 1 0 0 1 C 1 1 0 0 1 1 0 Y=A.B.C 0 1 0 0 0 1 0

## Output timing diagram: A B C Y

Q:16) Explain the operation of half adder and full adder. A:) Half Adder:The logic circuit which can perform addition of two (significant) bits is called half adder. It needs two inputs and it can give two outputs i.e. sum and carry. Truth table for the relation of the input and output can be given below:

Inputs A 0 0 1 1 B 0 1 0 1 Carry 0 0 0 1

Outputs Sum 0 1 1 0

A\B 0
0 1 0 0

1
0 1

A\B 0
0 1 0 1

1
1 0

## Hence its logic and bloc diagram are as follows:

A B

Su m Carr y

A B

Su m Carr y

Half adder has limited use as it can add only two bits and for addition of three bits becomes more difficult. Full adder:It is a combinational circuit that forms the arithmetic sum of three input bits. It consists of 3 inputs and two outputs. Inputs are denoted by A, B and Cin. Truth table is as follows: A 0 0 Inputs B 0 0 Outputs Cin 0 1 Carry 0 0 Sum 0 1

0 0 1 1 1 1

1 1 0 0 1 1

0 1 0 1 0 1

0 1 0 1 1 1

1 0 1 0 0 1

A\BCi n
0 1

00
0 0

01
0 1

11
1 1

10
0 1

## Cout=AB+ACin+BCin For Sum-

A\BCi n
0 1

00
0 1

01
1 0

11
0 1

10
1 0

Sum=ABCin+ABCin+ABCin+ABCin

=ABCin

A B Cin

Su m

Cout

Cin

A B

Sum Cout