Test and Verification Solutions

Experiences in Developing and Using OVM and UVM VIP

Mike Bartley, TVS Andy Bond Icera Bond,

Test and Verification Solutions 5th May 2011 1

Agenda

Advantages (and issues) of using VIP Example VIP usage models VIP packaging Metric driven verification UVM is for software engineers too! Example VIP test bench and package Maximising VIP reuse

Test and Verification Solutions

05 5th May 2011 May 2011

Advantages and issues in VIP

Advantages in using VIP

The ability to rapidly develop complex test benches
Standards help with compatibility and markets

Independent interpretation (of protocols) Leverage knowledge and experience from others Huge p g potential ROI ( (return on investment) )

Two main issues in using VIP

Visibility for debug y g Licenses in constrained random environments

Test and Verification Solutions

05 5th May 2011 May 2011

Example use models for VIP SDCard

Verify the design IP y g Verify integration of the design IP Develop the lower levels of a SDC driver

USB 3.0
Verify corner cases of the protocol Suspend in normal operation, host initiates device reset. Unplug from a HS host port, re-plug into a SS host port

AXI/AHB
Verify corner cases of the protocol Generate heavy traffic on the bus for stress testing

Serial protocol interfaces

Verify corner cases of the protocol Build complex multiple master and slave environments

Test and Verification Solutions

05 5th May 2011 May 2011

VIP packaging

Distinguish test bench and example code

User may only want to copy test bench code Ensure all typedefs, constant declarations and defines are in VIP code that gets included in the user test bench

Some simulators distinguish SV & Verilog code

by file extensions

Distinguish code for compile vs. include Identify files that contain package declarations which must be compiled before code that uses that package p g
Test and Verification Solutions 05 5th May 2011 May 2011 5

VIP packaging

Remember the user owns the compilation!

Avoid VIP relying on switches that may conflict with user switches

Avoid assumptions regarding messaging & objections

Users also often also have their own mechanisms for such things The supplier cannot assume that the UVM mechanisms (uvm_report, uvm_objection, etc) are ubiquitous. For example, users with lots of C, C++, Specman, etc. p , , , p , components in their test bench. A simple solution to this is to use macros for each message / objection, defined in a separate file. j , p This allows the customer the ability to easily override these macro definitions for simpler integration.

Test and Verification Solutions

05 5th May 2011 May 2011

Write once, run everywhere? Interoperability

User issues
Using multiple OVM/UVM components
Need to ensure they all work with a common release

Using the simulator vendor OVM/UVM g

Vendors deliver their own OVM with some additional features (e.g. for debug)

Supplier questions have they they

tested their component with multiple simulators tested their component with multiple releases of each simulator tested their component with multiple releases of OVM
including the vendor-specific releases vendor specific releases.
Test and Verification Solutions 05 5th May 2011 May 2011 7

Mapping to the specification Enabling metric driven verification Map coverage and checkers to the spec
USB 3.0 PKT Type: Section 8.3.1.2, Protocol Layer (Packet Type Field) Link Management Packets, Transaction Packets, Data Packet Header, Isochronous Ti I h Time St Stamp Packets P k t tvs_usb3_pkt_type_c : coverpoint usb3_pkt_hp_dw[4:0] { bins lmp = { h00}; {h00}; bins trp = {h04}; bins dph = {h08}; bins itp = {h0C}; { h0C}; }

Cadence Compliance Management System

Executable verification plan mapped to the specification Library of constrained random tests for corner cases Coverage model to grade verification completeness Checks and metrics to identify DUT verification gaps y g p See http://www.cadence.com/products/fv/verification_ip/pages/cms.aspx
05 5th May 2011 May 2011 8

Test and Verification Solutions

UVM is for software engineers too! Making test configuration easy SDCard verification of basic software routines:
Device driver identifies SD cards & establishing their capabilities

Verification responsibility
Build the VIP into the SoC test bench Constructs test programs that are agnostic to the SD card it detects Test bench constructed to instance specific variants of SD cards similar to inserting different cards on an evaluation board

Software responsibility
Instances were configured using uvm_test extensions with individual t f factory overrides d fi i th VIP capability i di id l set of f t id defining the VIPs bilit All other card characteristics, such as response times, error responses etc. are left to be randomized Each simulation alters the execution flow through the SW & HW
Test and Verification Solutions 05 5th May 2011 May 2011 9

UVM is for software engineers too! Making test configuration easy

For example
By default the card sends the response R1 for CMD11. However, the protocol allows for card to not respond

The software engineer is thus able to configure the t t b th test bench for various scenarios hf i i
set_config_int("sve.tvs_sdc0.slaves[0].slave_engine", "hold_cmd11_resp", user_val); p, ); where user_val is either 0 (response enabled), or 1(response disabled)

VIP delivered with synthesisable BFM The software was running within a day of putting silicon and a real SDCard on the board
Test and Verification Solutions 05 5th May 2011 May 2011 10

Example USB3.0 VIP test bench structure

Test and Verification Solutions

05 5th May 2011 May 2011

11

VIP Delivery

VIP is delivered with the following

Top Level Configuration Virtual Sequencer Generic Scoreboard VIP (Driver, Monitor, Bus Monitor) User Interface VIP using on chip protocol
Typically AHB, APB, AXI, PLB, OPB ...

Proven DUT or VIP (No Backend User Interface VIP) T t Sequences Test S Testbench Top

Test and Verification Solutions

05 5th May 2011 May 2011

12

USB 3.0 VIP delivery structure

TVS_USB3_VIP_TEMPLATE

SIM

DUV

BIN

RUNDIR

TVS_USB3_TOP

TVS_USB3_GENERIC

TVS_USB3_HOST

COMPILE

AXI

EXAMPLES TB_TOP TB TOP EXAMPLES

EXAMPLES EXAMPLES RTL-TB RTL TB TEST_LIB SV RTL-TB

UVM_SRC RTL-TB

TEST_LIB RTL-TB SV SV

SV

Test and Verification Solutions

05 5th May 2011 May 2011

13

Maximising reuse of the VIP components Generic Scoreboard

Users connect their User Interface VIP via "TLM Analysis Ports"

Sequences (Virtual Sequencer)

Need to port DUT/VIP Configuration and Data Transfer Sequences

Tests
Can be reused completely once the sequences are ported

Testbench Top
R l Replace sample DUT/VIP with U l ith User DUT

VIP Configurations
Multiple configurations of the VIP are delivered can be reused for particular USER Configurations of the DUT. User can create various environments (e.g. multi master/slave) Can disable ach component of the VIP using has_checker, has_monitor, has_driver.
Test and Verification Solutions 05 5th May 2011 May 2011 14

Summary

VIP offers huge potential advantages Consider ease of use issues

Debug P k i Packaging Interoperability

Usage model
Metric driven verification against the specification Ease of use for software engineers?

Maximise re-use of the delivered components Questions (mike@tandvsolns.co.uk) (mike@tandvsolns co uk)

Test and Verification Solutions 05 5th May 2011 May 2011 15