State of the Art in the Analog CMOS Circuit Design

~~~ ~~ ~~~ ~~ ~ ~ ~ ~~~ ~ ~~ ~~~ ~ ~~ ~~ ~~

ERNST HABEKOITE, MEMBER, IEEE, BERND HOEFFLINGER, HANS-WALTER KLEIN, MEMBER, IEEE, AND MICHIEL A. BEUNDER
Invited Paper

This paper isnot intended to cover CMOS analog circuit design exhaustively. Yet, it describes how much CMOS technology has been involved in analog circuit design despite the general opinion that CMOS is only suited for digital design. After some developments in the CMOS technology have been discussed, the analog building block scene is covered. The analog building blocks can roughly be divided into two subgroups: the switched-capacitorand the non-switched-capacitor building blocks. Following this subdivision different approaches are briefly looked at. Several tables conclude this review and indicate that new analog developments in CMOS circuit design are still to be expected. Next, the C A D tool development for analogCMOS is discussed, showing that there is still a lot to done in the field of automated be analog design. In conclusion, some ideas concerning analog CAD or, concerning CAD in a more generalsense are described.
INTRODUCTION

highnoiseimmunity, ease of design, relative ease of scaling. Theseadvantageswill gain importanceas the minimum feature sizes of CMOS devices are still being shrunk allowing complex electronic systems to be integrated on one chip. Therefore, during the last years a lot of effort has been invested in digital CMOS and the necessary design tools (CAD) in order to be able cope with these complex digital to designs. Further, today the difference between analog and digital is diminishing, because it is recognized that many analog functions can be realized with digital circuitry and sometimes even better than with an analog solution. It is, however, due to the increase of system complexity that integrating analog and digital functions on oneischip becoming necessary. The emphasis lies in thiscase on the monolithical combination of digital and analog. This means that in many cases very high performance analog functions are not that much required and greater number of moda erate performance analog functions are preferred. Thus today combined analog and digitalCMOS is in the center of interest. This involves three developments: First, there is the development of very well controlled CMOS technologies; second, there is the development of an analog CMOS cell library, and finally, there the development of is analog CMOS design tools (CAD). These three developments can be summarized as follows. The integration of analog building blocks in a CMOS technology demands very good control of the many different process steps in this CMOS technology. Very good process control is necessary in order to achieve analog process requirements such as minimum pn-junction leakage, good matching properties for active and passive components, precise resistor and capacitor ratioswith minimal voltage and temperature dependancy, reproducible and well-described(ac, dc, temperature dependant) behavior of the different active and passive components,

Activities inanalog CMOShave been rather limited in as many cases analog bipolar solutions were preferred, because bipolar devices provide several specific advantages for analog circuit design, such as: an inherent low input referred noise, low input offset voltage, high voltage gain, highoutputdrive, high frequency capability. Analog CMOS has also been hampered bythegeneral opinion that only bipolar devices are well-suited for analog circuits and that CMOS devices are only tobe used for digital circuits. Yet, the CMOS technology todayis becoming one of the most important technologies especially in the domain of digital circuits. This is due to the following main advantages: lowpowerconsumption, highpacking density,
Manuscript received October 1 , 1986; revised November 15, 0
1986.

The authors are with lnstitut f u r Mikroelektronik Stuttgart,

D-7000Stuttgart 8 0 , Federal Republic of Germany.

IEEE Log Number 8714502.

00189219/87/060(M816$01.00 1987 IEEE 0

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PROCEEDINGS OF THE IEEE, VOL. 75, NO. 6, JUNE 1987

reproducible and well-described bipolar devices.

lateralandvertical

This describes i n a nutshell which special requirements are demanded from an analog CMOS process. I n reference to analog CMOSbuilding blocks and analog CMOS CAD, the state of the art can be summarized as follows. Until recently, almost every analog CMOSfunction had to be designed completely by hand for its specific application. However, due to

with an accent on the analog requirements. Hereafter, a shortdescriptionofthestateoftheartinanaloaMOSbuilding blocks, fixed and parameterized, will beiiven in the following section (Section II) based on a subdivision into two types of analog MOS building blocks: switched-capacitor building blocks (Section Il-A) and non-switched-capacitor building blocks (Section 11-B).

This division into two different groups of building blocks is, however, not very strictsince, for example, amplifiers as non-switched-capacitor buildingblockswill beused in switched-capacitor filter modules. The third section will man-power limitations, review the existing CAD tools for analog CMOSdesign. In morestringentspecifications, the fourth section, some new proposals for analog CMOS the high risk that the first design will not function corCAD will be discussed. rectly, increasing complexity, I . STATE OF THE ART IN CMOS TECHNOLOGY it is necessary to automate the design process. The first step Today, all major semiconductor producers introducare ing 2-p-17technologies into production orhave done so in the previous year. A technology with such a feature size may handle circuits with a complexity of 256-kbit dynamic a RAM (DRAM). However, the learning curve for high yield and high reliability is still to be evaluated as so far there is not enough statistical information available. The following generation in CMOS technologies with the smallest feature size somewhere between 1.5 and 1.25 p n is currently beingevaluated in several process lines. Here, it should bepossible t o produce circuits with complexity a of a I-Mbit DRAM. Tomorrows generation of circuitswill need I n - feature p sizes or even less. The herefore needed technologies are under development at different manufacturing sites throughout the world as described in [2], [3]. JapaneseIC producers seem to be in the front in this lines racetowards small featuresizes since they havealready presented different prototypes of I-Mbit dynamic RAMS the at ISSCC in 1985. Apart from a few American activities there is a gap between Japanese and theAmerican andthe European IC producers. Recent efforts of European manufacturers aimto make this gap smaller or even to eliminate it. Different laboratories are developing submicrometer technologies, which will permit to realize circuits with 4 M b i t DRAM complexity or even higher. These technologies will be available for production lines the endof thisdecade. at Due to the developments described aboveis important it to use dimensionless design rules in terms of the length unit lambda.The minimum feature size is usually2 lambda. In this way, the design rules need not to be altered when the minimum physical feature size in the technology has advanced. The digital designs realized with the lambda design rules should scale automatically withthe new lambda, though the implementation less straightfonvard is due to not-scalable spacings,for exampleconcerning latchup. Special new technological solutions such as epitaxial materials, trench isolation, and indirectly, retrograde tubs will help to reduce latch-up sensitivity. Further, these solutions allowdenser circuits.These and other different alternatives of CMOSsuch as the choice between and n-well por twin-tub and the different types of isolation between the activecomponents are discussedin detail in Chens reviewing article [4]. This article gives a good presentation of the state of the art and the future trends.

inthisdirectionisananalogCMOScelllibrarywhichmakes the design more reliable and allows shorter designtimes. The second step is the development of analog design tools (CAD) allowing to exploit an analog cell library to its full potential. One step further is the introduction of parameterized cells. The parameters permit the design of analog functions which specific for an application, although are these functions are still based on a cell library. In this development, the time-discrete circuits such as switched-capacitor filters and converters played imporan tantrole.Duetothegainedexperienceinthefieldofanalog CMOS so far, there is now also a general interest for continuous-time analog CMOS such continuous-time RCfilas ters. Hence, there has been andstill is a lot of activityin the field of analog building blocks and parameterized blocks. Parallel to the development towards analog CMOS functions, there is adevelopment of mixed bipolar and ((3)MOS (BIMOS) technologies. The development of BIMOS technologies opens the way to new circuitdesigns combining MOS and bipolaron the same chip allowing optimal of use the differentanalog features of both active devices. There are many advantages to beexpected with BIMOS processes. Several companies around the world are making major investments in mixed-processing technology, as described by Cole a special report in Electronics [I]. Also, in several universities aredeveloping BIMOS processes, such as the University of Waterloo, Ont., Canada. It is interesting to note that the first mixed-technology activities date back to 1973 when RCA developed BIMOS techniques. RCA presented MOSlbipoIar operational amplifiers as early as in 1976. It will beevidentthatthisdevelopmentbydifferent research groups involves different variants of mixed-processing technologies, such as a combination of a buried twin-well CMOS structure with bipolar transistors on-chip, a bipolar-enhanced CMOS, or a combination of CMOS with epitaxial bipolar proan cess.

Although we should not underestimate the impact BIMOS will have on circuit designespecially if analog and digital analog are involved, wewill limit ourselves in this report to CMOS. Therefore, Section I will only cover CMOS technology in relation to combined analog and digital design

H A B E K O ~ Eet a/.: ANALOG CMOS CIRCUIT DESIGN

817

Table 1 Example of AnalogScalmg 1 7 81

-_ V
I W

. -

~ _ _ _ _ .

Standard Analog
voltage current K-'
K - l

/(

- 112

width thickness capacitance unit

length L
t". Cox oxide CL
AT

A,
gm

channel channel oxide thm total (thin) oxide capacitor translstor area capacitor area weak inversion transconductance inversion strong swltchlng time
weak inversion strong inversion

K T
K-'
(

- l/tox

- WL)/to, - l/CO& - (WL) -//(KT/@ - JiiZTJ

- VCJ/

to,

K -I K-' K" K K -Z K -l K -I
1

K ' K -I Kt'
K - l

-'

K-l

K-' 1 K *lil
i i l

K-I

voltage gain

energy disslpation power power disblpationlarea equivalent thermal V i inversion strong voltage noise v:,( equivalent low-frequency noise voltage
IP Plarea

weak inversion

The influence of the technology the on design of analog 'vDo MOS circuits has been discussed in detail by Allstot and Black in a tutorial paper in the PROCEEDINGS THE IEEE [5]. OF They describe the components which be realizedin an can NMOSor a CMOS process. Further,they discuss the achievable matching properties these of components. Noise, maximumvoltage gain, offset voltage, commonmode range, power dissipation, power-supply noise rejection, and moreare discussed as well. Thus the technology INPUT influences thedesign of analog MOS circuits. One important conclusionis that for high and lownoise the changain nel lengths ofthe MOS load transistors should be long. Further, the matching betweentransistors with similar layout geometry but in different locations is better with larger geometries. Apparently, analog CMOS does not fit very well in the F . 1. High-frequency amplifier [8]. i g emerging VLSl technology. It is less suited forscaling than digital CMOS,since it suffers more from shortthannel Analog CMOS design will become more sophisticated effects than digital CMOS. Table1gives anexample of scaland more competitive with analog bipolar design, as new ing. In order to cope with these problemsit is necessary to possibilities for better process control are offered by the have ananalytical model allowing quantitative scaling into advanced I-pm and submicrometer CMOS technologies. the submicrometer regime, for example the one described by Hoefflinger [6].Apart from good analytical models for 11. MOS ANALOG BUILDING BLOCKS short-channel MOS transistors in analog designs it i s necessary to have a guaranteed stable process. Some of the Two important remarks have be madeconcerning to most most important requirements relation tothis havealready in analog MOS building blocks described in the literature: been mentioned in the Introduction. Several authors, for 1) The building blocks are fixed on one technology and example, Demler, Milkovic, Ribner, and Matsui,report anahave to be redesigned(full custom and handcrafted) if the log MOS designs compatible with a short-channel VLSl technology changes;therefore, they are not technology technology (1 to 1.5 pm) in spite of the above mentioned independent. problems [;7-[IO]. These analog designs, a 10-bit N D con2) Most building blocks representa fixed design which verter, a high-frequency amplifier with 1WMHz unity gain is not adaptable to specific demands. This is, however, necbandwidth, high-frequency switched capacitor filters, and essary for correct analog design; therefore, they are not video filters,show the high performanceavailablewith anaoptimal in the implementation. log VLSI. The high-frequency amplifier proposed by Milkovic is depicted in Fig. l. Moreover, it is important to notice A. Switched-Capacitor AnalogBuilding Blocks that the ditference in performance of PMOS and NMOS MOS technology provides, especially the field samin of devices smaller gets as the transistor dimensions are pled analog design, unique properties for the charge storreduced. Thissuggests thepossibility ofwell-balanced age and transfer: active devices in submicrometer CMOS.

m -

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the possibility of compensating offset and low-frequency noise by double-correlated sampling. The low-frequency noise introduced by the MOS signal-processing circuit can also be shifted towards higher frequencies by frequency It is due to these unique properties that in the switchedmultiplication so that it can be avoided in the baseband. capacitor field many analog building blocks have already These compensation techniques are discussed by Gregobeen proposed. rian et a/. [I51 and show the importance of the switchedMOS amplifiers are surely one of the first analog MOS capacitor design approach as they relax the limitations of building blocks,which will beclearfrom thetutorial papers MOS for analog circuits toa certain extent. Abe et/ . give a on MOS amplifier designsuch as those written by Tsividis another good example of using chopper compensation [ I l l a n d Gray and Meyer [12]. More recently, Degrauwe, Miltechniques in their paperon ultra-low driftamplifierwith an kovic, and Ribner show their in papers [13], [8],[9] that there a MOSFET chopper [28]. Another author, Klein, reported are still new developments in this field. These MOS amplinoise reduction for CMOS amplifiers with chopper techfierstogether with MOS transmission gates as analog niquesin hispresentationattheESSClRC1984inEdinburgh switches and combinations of unitcapacitorsarrays form in [29]. At theESSCIRC 1986in Delft, chopper amplifier with a the basic elements for switchedtapacitor filters. For the a second-order low-pass selective amplifier was presented design of switched-capacitor filters the conventional filter by Enz [30]. In order to limit the contribution of the spikes design methods with reference filters can bedirectly due to charge injection, the spectrum thesespikes atthe of exploited. The switchedcapacitor filter design approach odd harmonics of the chopper frequencyeffectively lowis has been described by many authors, for example by Brodpass filtered by the selective amplifier. This chopper ampliersen eta/. and Gregorian eta/. tutorialpapers in the in PROfier is shown in Fig. 2. CEEDINGSOF THE IEEE [14], [15]. Also in NMOS technology, analog building blocks for a PCM Codec Filter chip have been developedas described bySenderowicz eta/. in[16]. This development of switched-capacitor filters has led to switched-capacitor filter blocks whichcan be exploited in larger filter systems, such as a programmable switchedcapacitor bandpass filter, described by Hosticka eta/. I q . [ Some general-purpose first- and second-order switchedcapacitor filter blocks have been proposed by Hoekenek and Moschytz [18]. Other switched-capacitor, non-filter-building blocks ranging from square-wave oscillators, AID and DIA converters, to balanced modulators,etc., have been described in the above mentioned tutorial paper by Gregorian et a/. [15]. McCreary, Suarez, McCharles, Demler, and Habekotte Fig. 2. CMOS chopper amplifier [30]. describe different approaches for AID or DIA conversion with switched-capacitor techniques [q, [19]-[22]. A recent Proposals for switchedcapacitor solutions have also been paper describing a low-voltage high-resolution CMOS AID made in the field of nonlinear circuit design. For example, converter shows that currentlystill new converter designs a German research group developed several nonlinear anaor improvements of older designs under development are log switched-capacitor buildingblocksfor aswitched[23]. Goodenough reports in Electronic Design new archicapacitor FSK modulator and demodulator [31], [32]. tectures and processes for advanced monolithic AID conS far, standard analog cell approach been described. o has verters [24]. Especially the autocalibration techniques There are, however, gate or more appropriatelytransistor referred to in this report allow theMOS-based converters array approaches for analog switched-capacitor circuits. to reach veryhigh resolution of to 16 bits with short con14 One very interesting transistor array was described by Kash version times of about 20 to 60 ps. in a presentation at the Conference on Custom and SemiGregorian et a/. also present in their tutorial paper [I51 Custom ICs [33].It allows digital circuits and analog circuits many examples of switchedcapacitor filter and non-filter to be realized o n one and the same prefabricated chip. switched-capacitor building blocks, implemented inlarger These analog building block% realizable with one metal systems such as a coder-decoder, a dial-signal receiver, a mask on thetransistor array include amplifiers, a bandgap speech synthesis system, or a tracking filter. Two other reference, comparators, and switchedtapacitor filters. recent papers, onebyOswald [25] on adual-toneand Another array presented by Caillon the ESSCIRC [34] perat modem frequency generator and one by White [26] on a mits only switched-capacitor filters with a universal dual-tone frequency receiver, show again the possibilities switchedcapacitor structure using foldedcascode ampliof analog switched-capacitor building blocks. This holds in fiers as basic building blocks for sampled data filter design particular for the switched-capacitor voltage referenceciras mentioned before. Although it does not really belong in cuit which is described by Oswald eta/. Another nice and it a review IC-design building blocks isworth mentioning of recent example of cell-based semicustom analog design that several universal programmable switched-capacitor filtechnique for switchedcapacitorfilters, AID and DIA conter chips in a dual-in-line package are available today, for version systems, and interfacecircuitry has been presented example, the one described by Lacanette recently in an issue by Pletersek et a/. [27. of Electronic Design News [35]. This suggests the possibility A very important aspect of switched-capacitor design is of programmable building blocks.
*

MOS amplifier with negligible input current, MOS bidirectional (analog)switch, (MOS)capacitor.

HABEKOlTE et a/.: ANALOG CMOS CIRCUITDESIGN

819

In conclusion to the discussion on switchedcapacitor building blocks, Figs. 3 and 4 give two other examples of switched capacitor solutions for particular applications, referred to in the next section on non-switchedcapacitor building blocks. Fig. 3 concerns a switchedeapacitor current source and Fig. 4 shows the principle of a switchedcapacitor temperature measurement.

vB2 0

VBI0

i' I

Fig. 5. Highly linear CMOS buffer amplifier [43].

Fig. 3. Current reference [59].

(451. Bandgap voltage referencesin CMOS exploit theexistence ofparasitic verticalor lateral bipolar transistorswith the well as base. A good example of such a bandgap reference is described by Degrauwe et a/. in a recent paper [46]. The principle of this reference is shown in Fig. 6. Other

"REF

Fg 4. i.

CMOS SC temperature measurement [52].

Fig. 6. Voltage reference [ a ] .

references use the difference between the threshold voltages of differenttypes of MOS transistors, as described in Although the exploitation of switchedcapacitor circuits (471. Vittoz and Fellrath proposespecial voltage references as building blocks has spread out widely, one should not based on theweak-inversion mode of MOS transistors in forget the efforts directed towards non-switchedcapacitor, their paper (481. The channel current of MOS transistor an analog building blockssuch as the I b i t building block for in theweak-inversion modedepends logarithmicallyon the 20-MHz AID convertersor the pulsedensity modulator for input voltage in a similar way as with bipolar transistors. high-resolution AID convertersboth developed byFiedler Voltage and current references are important for an opti[36], [371 and the designs for operational amplifiers (espemum setting of transistor bias points, which is critically cially those for resistive loads) [MI-[42]. A recent presenimportant for high-performance CMOS analog circuits. A tation at the ESSCIRC 1986 Fischer describes a by highly lincentral bias generator circuit producing referencevoltage a ear CMOS buffer amplifier for resistive loads down to100 and adistribution of this reference across the chip through slave bias cells is therefore important in n (431, which is depicted in Fig. 5. every analog stanOne important difference between amplifier for conan dard CMOS cell library as discussed at the ClCC Confertinuous-timeanddiscretetimeapplications is the conence in 1986 (491. For voltage referencesthere are intrinsic straint on the linearity and the offset. In discrete-time appliphysical values, which can be extracted by adequate circations, for example, it i s unimportant how the output of cuits as described above. However, semiconductorphysics do not provide any "built in" current. Therefore, current the amplifier slews and settles to its final output level. It is references have t o be derived from voltage references by onlyimportantthattheamplifiersettleswithinacertaintime converting the reference voltageinto a current with resisa slot given an allowed error. tor. This results in an inaccurate current reference due to Other examples of continuous-time building blocks are theerrors introduced bythe resistor. Klein presented agood programmablevoltage sources, comparators, and bandgap switched-capacitor solution for an accurate current refervoltage references as described by Stone et a/. in (441 and ence at the ESSCIRC 1983 in Lausanne [50] (Fig. 3). Vittoz in his presentation the ESSCIRC 1984 Edinburgh at in B. Non-Switched-Capacitor Building Blocks

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The possibility to create a reference voltage n an MOS o whole gate array whether they are switched-capacitor or chip implies that is possible to measure the temperature. it not [57l. This is in many cases necessary for correct on-chip temSeveral silicon foundries do offer cell libraries with anaperature compensation such as described by Shenton in log buildingblocks. They allow to use comparators, ampli[51] for temperature compensation ofn c h i p Hall sensors. o fiers, and voltage references in their standard cell design, Habekotte discusses different approaches for temperature as explained in publications such as [58]. Not many vendors measurement in CMOS [52]. allow the use of weak inversion for very low power consumption and offer special cells for this purpose. And only Theweak-inversion mode as described above is only practical at low current levels (<I-5 PA), so that it does not in some cases also switched-capacitor building blocksand allowhigh-frequencyperformance.However,high-gain A/D and DIA converters are being offered in the standard amplifiers with very low current consumption can be realcell documentation besides cell libraries with theclassical analog functions such as comparators, amplifiers, and refized using the input transistor(s) in weak inversion. This is especially of interest for battery-powered electronics. Tee1 erences. and Waynedescribeastandardcellapproachutilizing C. Summary subthreshold building blocks for implantable medical elecAlthough the subject of building blocks have not been tronic devices [53]. Other time-continuous building blocks getting attentiondiscussed exhaustively, it will be summarized in the following six tables: nowadays arethe fully integrated active RCfilters.They do Table 2 givesseveral specifications of afew MOS notsufferfromnoisealiasedfromthefrequencybandabove amplifier building blocks found in the literature. the sampling frequency because they are continuous-time. Table 3 shows the most important characteristics of a Thus anti-aliasing filters and on-chip clock generators can few MOS amplifiers for resistive loads. beavoided. Yet, atotallydifferentialfilterstructure is Table 4 gives an overview of existing switched-capacneeded in order to minimize second- (even-) order distoritor building blocks. tion components with balancing techniques. In these filTable 5 presentsexamples of integrated systems using ters, MOS transistors in the linear partof their output charswitched-capacitor building blocks. acteristics are exploited as resistors. In order to guarantee Table 6 presents examples of analog integrated cira correct time constant, an on-chip tuning circuit adjusts cuits, which do not exploit switched-capacitor techniques. the channelresistance by changing the gate voltage of the Table 7presents several advanced monolithicND conused transistors. Fine tuning is realized by adjusting the verters [24]. gate voltage so that an on-chip oscillator realizedwith the Thesetables indicate how much building blocks are being same continuous-time filter structures tuned to exteris an nal clock. Banu andTsividis[54] introduced such afullyinte- used for integrated circuit design. Further,they suggest how effective a library of building blockscan be. grated activeRCfilter in1983. Pennock eta/. demonstrated is set selfHowever, another very interesting trend by the in their presentation [55] at the ClCC Conference some adjusting or self-calibrating circuit technique. Compared advantages of integrated continuous-time filters over to earliertechniques, where laser trimming andbetter switched-capacitor filters. matching of bipolardevices were used to realize high-perIn thenon-switched-capacitor area there are gate arrays formance analog circuits, self-adjusting techniques open a which permit to realize analog functions as well. Watson, new area of high-precision ICs. One representative examfor example, proposes several analog building blocks his in ple is the clock-controlled continuous-time RCactive filter paper [56] a CMOS for gate arraywhere it is possible to real[54].Anotherimpressiveexampleisaone-chipfullyselfcalize analog functions,such as comparators or amplifiers, in the periphery. Another transistor array described by Pickibrating 12-bitADC [24].These techniquesallowhigherell allowsto implement analog functions throughout the precision analog ICs,even in a VLSl environment. And
9

Table 2 Several Characteristics of Some MOS Amplifiers Found in the Literature Bias Reference MilkovicM StoneM [8] Configuration one-stage with stacked current mirrors69 two-stage strong and weak inversion adaptive biasing cascode output strong and weak inversion foldedcascode 80, two-stage in weak inversion input pchannel input nchannel Slew Rate (V/PS) 200 1.8 0.039 91 107 Gain (dB) Current BW, (PA) 50 5 0.2 0.5 Unity-Gain C load (MHz) (pF)

70,
1.0, 0.058,

1.0 1.2

[MI

DegrauweM [13]

1.o 3.3 250

60
60
68.5

0.74 0.22 10.0

0.1, 0.05,

10.0 1.o

Ribner85 Tee185 1531

[9]

0.038 0.022

101 107

0.01 0.01

0.11, 0.11,

5.0 5.0

HABEKOTE et a/.: ANALOG CMOS CIRCUIT DESIGN

821

Table 3 Several Specifications of Some MOS Amplifiers for Resistive Loads Found in the Literature
Output power in resist.) 160 in 100 Q 30 in600Q 36 in 300 Q 24 in 200Q 12.7 100 in 100 Q DC Power Gain (dB) 78
84

Quiescent Unity-Gain

Reference Maeding83 [MI [39] Saari83 Brehmer83 Fixher85 Fischer86 [42]

Configuration (mW class B three stage

(mW)
7
8

BW, (kHz) 260,

80%

C load
(pD
?

160 loo0 lo00

?

[a]
[41]

class AB class AB mixed PMOS and n-MOS foldedcasc. inputstage output buffer

83 93 82

420, 1200,

19

3500,

Table 4 List of Several Switched-Capacitor Building Blocks Found in the Literature

Table 5 Examples of Integrated or Discrete Systems Using Switched-Capacitor Building Blocks

Reference White79 [261 Function dual-tone multifrequency receiver PCM codec filter (NMOS) spectral line enhancer dual-tone and modem frequency generator FSK modulator FSK demodulator analog front-end for high-speed modems abit 2EMHzflash N D converter MOS AID converterand filter four-channel call progres detector video filters &MHz subranging &bit N D converter

Reference Martin81 [59]

Block

Building

phase-lock loop tracking filter programmable equalizer synchronous demodulator adaptive channel equalizer Schmitt trigger phase comparator interpolative N D converter phase reverser biquad and ladder filter blocks digital-to-analog converter analog-to-digital converter voltagecontrolled oscillator continuous-time peak detector balanced modulator full-wave rectifier first- and second-order filter blocks voltage reference current reference temperature measurement

(mm3
3. 00
24.0 discrete 9.1 1.3 6.6 31.5 21.6 4.5

Area

Senderowicz82 [16] Martin83 Oswald84 HostickaM Fotouhi84 Tsu kada85 Hauser85 Levy85 Matsui85 Dingwall85

Hosticka82

[32]

Gregorian83 [15]

Hoekenek83 (18) Oswald84 Klein83 Habekotte

[X]

32.4 7.0

[MI
[52]

moreover, the overhead due to integrated controllers or similar building blocks further reduced duet o this techis Table 6 Examples of Non-Switched-Capacitor Analog nological advance. Local intelligence has brought the important breakthrough in the digital areawhen manyyears Integrated Circuit Designs ago the integrated microcontroller or microprocessor was Function Reference introduced. Today, the implementation of self-adjusting or selfcontrolling analog circuits may be the breakthrough Soo85 1661 750 megasamples/s latched for analog high functional density circuit techniques.
comparator

Area

(mm2)

Ill. CAD

FOR

ANALOGMOS DESIGN

Sau185 Band85

[67l 1681

&bit video DAC

elliptic continuous-time filter fourquadrant analog multiplier

1.0 (active) 4.0 (active)

Before discussing CAD for analog MOS design an overview of CAD for digital MOS design will be given t o demonstrate its current state of the art. A. State-of-theArt Digital MOS Design i n the current digital CAD market a large number of vendors is active, offering products ranging from simple layout editors to completed integrated design systems. Current CAD packages can be divided into two separate groups: design tools, covering onlya specific part the design of path,

Babnezhad85

[69]

design systems, covering the complete design path from schematic entry down to CIF tape.
A n intermediate between thesetwo groups is the toolbox

concept:

PROCEEDINGS OF THE IEEE, VOL. 75, NO. 6, JUNE 1987

Table 7 Some Features ot Advanced Monolithic

~ 4 1

A/DConverters with Autocalibration

Resolution (bits)
16 14 12
12

Conversion Time (25 C)

(1s) 20
20 20 no

Sampling Capability no Yes Yes Yes no Ye5

Clock no no no no Yes
Yes

On-Board Reference

Principle succ. approx. succ. approx. succ. approx. two-step

Process CMOS CMOS CMOS CMOS BlMOS BIMO5

1 25 15

no

12 12

Yes Yes Yes

Ye5

succ. approx. succ. approx.

a number of separate design tools packed together. are Suitable interfacesare added to enable the transfer of data between the differenttools. For design tools, well-defined interfaces to an existing design environment are of extreme importance.For design systems, this is a less severe constraint, or sometimes it is even undesired. The only interface important for an integrated design system is its interface to the foundry. Almost all current state-of-the-art CAD packages support a hierarchical design approach whichusually carriedout is insuchawaythatthedesignisspecifiedinatop-downfashion. Depending on the implementation chosen, the data can either be transferred to the foundry in the form of a netlist (gate-array implementation), or the designer use can the topdownspecified circuit data in a bottom-up fashion to design and/or assemble the layout of the circuit. In this case, atape containing geometrical datawill be handed over to the foundry. Currently, no design systems are available which allow adesigner work a strict top-down fashion. to in Des@ systems leaning towardssuch anapproach are sold under the name of silicon compilers. The first step in the design of a circuit is usually the schematic entry of the circuit. it has alreadybeen stated preAs viously, the specification will be done in top-down fasha ion. If available, a high-level functional simulator will be used to verify the correctness of the circuit specification. During this phase the designer is confronted with several choices concerning the implementation of the different functions: Using megacells for implementing complex functions. CurrentIy,anumberofsiliconvendorsofferawiderange of megacells, ranging from simple peripheral circuits UP to complete microprocessor cores. Using standardcelllibraries. Usingparameterized cells, t o compile different functions (e.g., ROM, shift registers, PIAS, etc.). Usingfullcustomfunctions,constructedwith a geometrical layout editor ora stick editor. Using a gate-array implementation. The application of the different concepts either mixed or constrained to one concept only, will depend on factors such as: the design system or tools used, the foundry which will manufacture the circuit, the circuit applicationdemands, how fast it should be implemented, etc. The designer will evaluate the applicability of the different concepts o n a per-function and per-levelbase accord-

ing to his system partitioning results. This will start at the system level,where he encounters functions as memsuch ory, ALUs, etc., [70]. One can state that currently no tools or design systems are available which support the designer in this decision process. Usually, the designer will make thesedecisions basedon"back-of-the-enve1ope"sketches. Some work is under way to fill this gap [71]. The designer will ideally.choose on a per-function base which implementation concepts he wants to use. After the designerhas chosen how to implement a function (or decompose it again in a number of subfunctions), he can use different tools to realize these implementations,such as: a layout editor, either symbolic or geometrical; acell compiler, acceptingaparameterized description as input, resulting a layout description (with or within out a simulation model); a standard cell placement and routing tool; a full custom placement and routing tool, placingand routing ordinary sized blocks. Using a layout editor to realize a certain function will usually only happenat the lowestlevels of thehierarchy: constructing leaf cells. At these levels, the designer can also compare the performance of the different functions with their predicted behavior using an extractor and a timing simulator (e.g., SPICE). At subsequent levels (as stated before we are following a bottom-up construction in the layout of the circuit), place androute tools will used. the be Analysis of realized functions with the help atiming simof ulator will become too tedious. Along this process of bottom-up construction, the designer will also use tools such as design rule checkers, netlist compare, and electrical rule checkers. If possible, a critical path extraction and analysis will be done. More advanced design tools orsystems also support the designer in the preparation test vectors. Support for of scan test maybeavailable, with or without automatic pattern test generation. Concluding,onecould state thatthe state-of-the-art design tools and systems show the following deviations from what would currently seen as the ideal design envibe ronment: support onthe system design level, advising the designer during system partitioning on items such as test strategy, floorplanning, and design tradeoffs;
a higher degree of technology independence, especially in thearea of cell libraries, parameterized cells, and simulation models;

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paper [27]. These special approaches allow interesting layout solutions for the capacitor arrays, where capacitors are grown from a "capacitor seed." enabling the designerto change from one foundry to Before concluding this section on analog two other CAD another without significant problems. analog silicon assemblers should mentioned. be One descrip In spite of the enormous development of computerized assembler [78] permits the generation of a layout tion of an AID or a D/A converter from resolution and lindigital design tools andthe state of the artas described in the previous paragraph, analog CAD not evolved in the earity specifications.The assembler exploits charge redishas tribution techniques as described by McCreary et a/. [I91 same way. Thisis due to the fact that in analog circuits the signals havea continuum of values for amplitudeand time and Suarez et a/. [20]. Thus the assembler is restricted to 'converterswith a successiveapproximation using a resistor and, hence, the components also havea continuum of Values. This makes the modeling of analog circuitsfar more string to decode the more significant bits and a binary complex than the modeling of digital circuits, where the weighted capacitorarray to decode theless significant bits signal is at least limited to a finite number of (usually or the other around. The assemblerwill determine the way values best configuration, if at all possible, depending on the two: 0 and 1) with a discrete elapse of time. achievable matching within the string and the array and Today, some developments towards analog CAD be can given a certain resolution and linearity for the converter. recognized apart from thealready existing simulation programs such as SPICE with all its different versions [72] at The layout is realized with thesame program whichis used component level, or SWITCAP[73], which is specifically for switched-capacitor filter design [81]. meant for discrete-time circuits, and DIANA [74], which Especially the description of a program presented by Degrauwe at the ISSCC 1984is of interestin the discussion allows simulations at component level but also at system level due to its so-called mixed mode. on analog MOS building blocks [82]. It permits to dimension an MOS amplifier selected from a limited number of Computer-aided design of analog integrated circuits was possible amplifiers according to what is actually needed. reviewed by Allen in a tutorial paper at the ClCC Conferencein1986[75].ThispaperdiscussesfirstthedifferentanaIn everynewdesign theenvironmentof an amplifier log design methodologies which can be divided into five changes, which means that the amplifier block has to be different categories: redesigned in order to be optimal in the given application. By taking different amplifier configurations and recalcusingle-component arrays, is it lating the dimensions of the MOS transistors possible circuit arrays, larger system. The layout for the to have adaptable cells in a * standardblocks (megacells), amplifier is generated with the new dimensions of the tranparameterized blocks, is sistors using a symbolic layout, whichin thiscase a stick programmablechips. diagram. This stick diagram fixes only the relative position In many cases, the CAD is limited to placing and routing of the different transistors t o each other and guarantees standard fixed cells using the metal interconnection mask. similar layouts for one and the amplifier for different same Schematic entry of the design is usually possible and the applications. This is, however, only possible within a limdesign can be simulatedwith one of the above mentioned ited range of(WIL) ratios of the MOS transistors due to othsimulation programs. Only the parameterized blocks allow erwise too inefficient use of silicon real estate. some adaptation of the blocks to the specific application. It is, in fact, necessary t o every analog building block to The programmable chips provide only a very narrow rangebeadapted to itsenvironment, but sofar specifications new of applications,an inefficient use of area, and a limited perstill mean to redesign a new full custom analog cell or t o formance. They do not really fit in this discussion. accept the limitationsof afixed analog building block. Even Analog CAD has mainly developed in field the of the switchedcapacitor parameterized cells are not really switched-capacitorbuilding blocks, because in the disadaptable since a change ofthe feedback capacitor should crete-time domain the design is relatively straightforward be followed by adaptation of the amplifier design to this andisinmostcaseslimitedtothecorrectchoiceofbuilding new load. blocks and the calculation of the capacitor ratios (values). B. Future CAD for Analog M O S Design Severalauthorsclaim in theirpaperstodescribeaswitchedcapacitor filter compiler, and show proven designs [76]-[79], If we draw a parallel the current developments in the to but it would probably be more appropriate to call these proarea of digital CAD and compare them with the results in grams assemblers. the literature study of state-of-the-art analog MOS CAD, the Kimble et a/. proposed additionally a strategy for autofuture analog/digital MOS design tools should develop the routed analog VLSl in a presentation at the ClCC Conferfollowing capabilities: ence in 1985[80]. This analog router keeps sensitive tersystem level support for the designer, including highminals, which have to be interconnected with other blocks, level functional simulation; within special analog routingchannelssothat parasiticcouextended use of parameterized cells; pling can be minimized. Othersensitive terminals are kept place and routing tools which willtake analog design inside analog the building blocks in order to avoid constraints into account; unwantedparasiticcoupling. The authorsprovidefour suitable test strategies; examples of chip designs realizedwith this assembler. a higher degree of technology independence; The calculation of the capacitor ratios introduces parathe possibility to introduce autocalibration techmeterized blocksinto the design methodology. Some speniques. cial approaches are described by Pletersek et a/. in their significantly more support on the implementation of different types of test strategies;

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Tf::l An essential part of mixed analogldigital design will be CONCEPT the floorplanning. Because of the far-ranging implications of analog cells on the floorplanning operation, it will no DATA BASE describing longer be feasible for a designer perform manualplace to of BUILDING BLOCKS and route operations. This will lead towards a strict topBUILDING BLOCKS down approach, where circuit partitioning and floorplanningare parallel operations. When thedesignerreached has of BUILDING BLOCKS wilh PARAMETRICAL ADJUSTMENT the lowest level of specification, bottom-up construction POSSIBRITIES of the circuit will consist only of filling up the empty floori t plan modules. Such atrue hierarchical approach towards circuit design would also support the implementation of a BUILDINGS BLOCKS STICKDIAGRAMS BLOCK LAYOUT straightforward test strategy. Currently, the only feasible test strategy consists of isolating the analog from the digital functions, enabling separate testing of both worlds. The usage of parameterizedcells has several advantages I over the usage of full custom cells: TECHNOLOGY DESCRIPTION It provides an implementation concept, which enables a more technology-independent approach. Fig. 7. Hierarchical conJguration of a CAD tool. It will ease the test problem slightly because of the usage of test libraries. ELECTRICAL
Only in thisway it is possible to adapt the building block to the actual implementation and to give a certain guarantee that the first silicon will correct. Future be CAD tools, however, should also permit a topdown design of mixing analog and digital systems. In order to realize top-down design, a hierarchical approach has to be implemented in the CAD tool. One very important part of such a tool will be the high-level verifier (simulator) which allows get a to feeling of the performance of the total system without directly going into details. If the design corresponds with the specifications at this high level, one can fill in details of the different blocks in the design. This will be done by going down in the hierarchy and by simulating, for example, a switchedtapacitor filter with SWITCAP or an amplifier with SPICE as local simulators. Certaindetails, such as noise or limited gain-bandwidth, found with the local simulator can be reintroduced in the high-level simulator in order to verify the validity of the total system. Further, it should be possible to adapt the analogldigital building blocks t o the actual technology in which they have to be realized.Thiswouldallowadevelopmentinthetechno1ogy without a redesign of the cells whenever the technology advances. As the blocks have to be adapted to the actual implementation through its parameters, synthesizers are needed. Fig. 7 gives an impression of the hierarchical configuration of the CAD tool as described above. Fig.8 shows the basic concept of the database with the cells the synand thesizers. The different types of cells may need different simulators, but the whole system should be simulated with an overall verifier (simulator). The parameterized cells may include amplifiers, comparators, oscillators, or larger building blocks as filters such and converters. Their implies, however, a limited numuse ber of fixed configurations, since they have to stay adaptable. Although it .is not optimal to design with a limited number of fixed configurations, a library of such cells allows fast turn-around times. The performance of this CAD tool can be summarized as a topdown design of integrated circuits implementing a libraryofanalogldigital building blockswhich can be adapted to thetechnology in whichthese have to be realized. This involves the following:
(REALISATION) MSCRIPTION (FUNCTION)

\r

1
I

h
D A T A BASE rhh EUILOING BLOCKS

I
I

SILICON SYNTHESIZER OVERALL SIMULATOR BUILDIUG BLOCKS

ITYPElI

i
SVNTHESIZER I SYNTHESIZER II LOCAL SIMULATORS

I il

4
[A O T L Y U]
i

Fig. 8. Basic concept of analogldigital silicon synthesizer.

High-level functional simulation allowingthedesigner to estimate the validityof a design concept anearly stage at of the design. The use of different local simulators (such SPICE as or SWITCAP). This permits to extract details of the electrical performance of the implemented building blocks and their influence on the design concept. details can be reinThese troduced in the functional simulator in order to verify their influence on the total system behavior; an example is the frequency behavior ofan amplifier calculated by SPICE as local simulator. The introduction of synthesizers makes it possible to adapt the building block to electrical and its physical environment, permitting a technologically independent CAD system (restricted, however, to CMOS technologies). For a realistic and fast CAD system, a limited number of building blocks with general electrical, general performance, and general physical (stick-diagram) descriptions have been defined in thedatabase. The system has modular structureso that at any time, a when a new type of building block i s found necessary, it can be added to the database with the necessary descriptions. The synthesizer for this new building block to be has introduced as well. For proper choice and correct definition (standards)

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of the building blocks and database, at first study is neca essary in o r d e r to model and correctly characterize the CMOS technology. Hereafter, the necessary parameters to characterize the building blocks can be chosen; this is meant to be routinely used (standard CMOS analog/digital

building blocks).
Realization and evaluation building b l o c k s a n d t h e i r of implementation in an evaluation circuit of greater comp l e x i t y t h a n only o n e building block allows to v e r i f y t h e results both of C A D tools and database as w e l l as its management. D u e to t h e l i m i t e d p e r f o r m a n cof these cellswith fixed e configuration, it cannotbeexpectedthathigh-performance analog or digital circuits in front-end designs can be realized with them. Especially, high-performance analog f r o n t e n d d e s i g n s a r e h a n d i c a p p e d . T h e r e f o r e , t h e tool CAD has to p e r m i t a design with analog primitives such tranas sistors biased as common source or common drain, etc. Nordholt describes a straightforward synthesis approach using bipolar primitives[83].This synthesis has proven itself with many high-performance analog bipolar designs[84][861. ACKNOWLEDGMENT Theauthorsare indebted toEurosil (Germany)and Sagantec (The Netherlands) for discussions concerning analog C M O S C A D . T h e y a l s o w i sto t h a n k S. Kruger for typing h the manuscript, Weisskopf for making thedrawings, and C. H. Schmidbauer for taking the photographs of the authors.

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Information Sciences Center at the Universityof Minnesota, Minneapolis, MN. He became Head of the School of Electrical Engineering at Purdue University,West Lafayette, IN, in 1984. In the fall of 1985, he was appointed Director of the Institute for Microelectronics, a public research foundation, i n Stuttgart, West Germany. He has authored or coauthored over 100 publications and has edited and co-authored two books on microelectronics. Dr. Hoefflinger received the 1968 Award of the German Nachrichtentechnisihe Gesellschaft and the 1969 IEEE ISSCC Outstand1980 Darlington Prize ing Paper Award. He is theco-recipient of the 1982 Electronics of theIEEE Circuits andSystems Society and of the Letters Premium of the British IEE. He became a member of the Dusseldorf Academy, one of the five German Academies of Science, in 1981. From 1973 to 1977, he was an Associate Editor ofthe IEEE TRANSACTIONSELECTRON DEVICES. ON

was born in 1939 in Bucharest, Romania. He studied physics in Goettingen and Munich, West Germany, and received the diploma degree from the University of Munich 1964, and the Docin tor rer.nat. degree from theTechnical University of Munich in1967. From 1964to 1967, he was associated with the Siemens Research Laboratory in Munich.From1%7to1970,hewasAssistantProfessor in the School of Electrical Engineering, Cornell University, Ithaca, NY. From 1970 to 1972, he was Manager of the MOS Integrated Circuits Department, Semiconductor Division Siemens AG, Munich. In1972, he became Professor of Electrical Engineering and the founder and first dean of the Electrical Engineering Departmentat the University of Dortmund, West Germany. There hewas also director of the Electron Devices Laboratory. During 1979-1980, he spent a half-year sabbatical with the Electronics Research Laboratory at the University of California, Berkeley. From 1981 t o 1983, he was head of the Department of Electrical Engineering andcodirector of the Microelectronics and
Bernd Hoefflinger

Michiel A. Beunder was born in Merauke, Dutch New Guinea, on October 31,1959. He received the masters degree in electrical engineeringand i n computer science in June 1985. He had his first VLSl experience during the VLSl Program of Dr. Craig Mudge i n Adelaide, Australia. From1984 till July 1985 he worked at Philips Telecommunications Industry, Hilversum, The Netherlands, on VLSl design strategies based on the usage of quality factors. He joined the Institute for Microelectronics Stuttgart, West Germany, i n September 1985. He currently holds the position of group leader Design and ComputerServices. VLSl HisinterestsareVLSl system design, siliconcompilation,operating systems, and computer architecture.

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PROCEEDINGS OF THE IEEE, VOL. 75, NO. 6 , JUNE 1987