W.

Daniel Leon-Salas
University of Missouri-Kansas City
ECE 401AN and ECE5590N - Analog Integrated Circuit Design
Course Syllabus

Instructor
Dr. Daniel Leon-Salas
Office: 560E Flarsheim Hall
Office Hours: To be arranged
Email: leonsalasw@umkc.edu

Class Location and Time
Royal Hall room 111, Wednesday from 5:30 pm to 8:15 pm

Course Website
http://blackboard.umkc.edu
Means of Communication
Your UMKC-assigned email will be the primary and official means of communication for this course.

Text
Required:
Design of Analog CMOS Integrated Circuits, by B. Razavi, McGraw-Hill, 2001. ISBN: 978-0-07-238032-3
Reference Texts:
CMOS Circuit Design, Layout, and Simulation, 2
nd
edition , by R. Jacob Baker, Wiley-Intescience, 2008. ISBN:
978-0-470-22941-5
Prerequisites
A good background in electronic circuits is highly desirable. Must have taken ECE 276 -Circuit Theory. Intermediate
knowledge of calculus and probability is also desirable.

Homework

Homework will usually be assigned every week. You will be credited for turning in a complete homework. You are
encouraged to see me for any questions that you might have regarding the assignments and to check your answers
against the posted solutions. If you work on your homework you will be able to do a good job on your exams.

PLEASE NOTE: Partial credit will be given for late homework. You are allowed to discuss homework problems with
your classmates but the final solution MUST be completed individually. You are required to STAPLE your
assignments. In the case of electronic submission, you will be asked to upload your work by the exact deadline on
Blackboard. Please direct all your Blackboard questions or technical problems to UMKC Blackboard support at
callcenter@umkc.edu.

Exams
There will be two midterm exams. No makeup exams will be offered. Exams will be close book and close notes.
There wont be a final exam. Instead a final project will have to be completed. Final projects might be completed in
groups of up to three students depending on the complexity of the project. Project topics might be suggested by the
student or assigned by the instructor. Projects will have to be presented in class.

Grading
Homework 30%
Exam 1 20%
Exam 2 20%
Final Project 30%

Letter-grade equivalency:
94-100 A
90-93 A-
87-89 B+
83-86 B
80-82 B-
77-79 C+
73-76 C
70-72 C-
67-69 D+
63-66 D
60-62 D-
0-59 F

Course Outline (tentative)

Review of IC active device models
MOS and Bipolar IC fabrication technology and layout
Current mirrors and single-stage amplifiers
Noise in ICs: analysis and modeling
Basic Opamp design
Advanced current mirrors and advanced Opamps
Voltage references
Micropower circuits
Operational transconductance amplifiers (OTA)
DC-DC converters
PLL, oscillators

Academic Rules of Conduct
According to UMKCs regulations academic dishonesty, including cheating, plagiarism or sabotage, is adjudicated through the
University of Missouri Student Conduct Code and Rules of Procedures in Student Conduct Matters. By attending this class,
you implying that you have read, understood, and are fully committed to the required codes of conduct and are aware of
consequences of breaching them. For more information on the student code of conduct please visit:
http://www.umkc.edu/helpline/code_conduct.asp



Academic Calendar
Thanksgiving Holiday
Last week of classes
(Projects due and presentations)
First midterm
Second midterm
Introduction to Analog Design
Why should we bother to study analog design?
Natural signals are analog
Wireless communications rely heavily on analog
circuits
Sensor interfaces need to be analog
Even microprocessor and memory design need analog
expertise (sense amplifiers, clock generation and
distribution)
Power management (battery chargers, voltage
regulators)
Analog Designers are in Good
Demand
Analog Design Hexagon
Noise
Power
Frequency
Gain
Supply
Voltage
Linearity
What Things Would an Analog
Engineer Design?
Synthesis and Analysis
Schematic Entry & Simulation
Layout Design
Evaluation and Testing
Analysis vs Synthesis
Circuit
Analysis
Properties
Analysis vs Synthesis
Properties
Synthesis
Circuit 1
Circuit 2
Circuit 3
Design
Process for
Analog
Integrated
Circuits
CMOS IC Technologies
Semiconductors
Conducting materials: atoms can easily share
orbiting electrons
Insulating materials: atoms have valence electrons
tightly coupled to the nucleus
Semiconductor materials: something in between.
Elements with valence of 4: Si, Ge, Sn.
Energy Bands: when atoms are brought together to
form a crystal they create regions (bands) of
allowable energy for the electrons: valence and
conduction bands.
Energy Bands
At T= 0 K: All electrons are in the valence band.
As T increases, electrons gain energy and move to conduction
band.
Electrons leave a hole behind as they move to the conduction
band.
Holes can move too but not as easy as the electrons
Eg
(1.12 eV)
No allowable
states here
Ev
Ec
generation recombination
free to move (not tightly
coupled to the nucleus)
Intrinsic (Pure) Silicon

B = 7.3x10
15
cm
-3
K
-3/2

(materials constant)
k = 8.62x10
-5
eV/K
(Boltzman constant)
As comparison, N
Si
= 50 x 10
21
atoms/cm
3
one electron is excited for every trillion
(10
12
) atoms
Doping
Process of adding other materials (dopands or impurities) to
intrinsic silicon increases concentration of electrons or
holes
Donor: material with 5 valence electrons such as
Phosphorous (P)
donor density or
concentration (atoms/cm3)
materials with donor atoms is
called n-type
Doping
Acceptor: material with atoms with valence 3 such as Boron
(B).
acceptor density or
concentration (atoms/cm3)
materials with acceptor atoms
is called p-type
Mass-Action Law
For doped silicon:
For n-type silicon:
For n-type silicon:
Conduction in Semiconductors
Drift Current: Due to an electric field E.


Diffusion Current: Due to a gradient (non-uniform)
concentration of charges

()

()

diffusion constants

mobilities

E
The PN Junction
I
D
= current due to diffusion
I
S
= current due to drift
The PN Junction
If the contacts are left
unconnected, no
current flows and I
D
=I
S
The width of the depletion region is given by:
=

=
2

+
1

0

built-in potential
permittivity of silicon =
1.04x10
-12
F/cm
Also

+
=

The PN Junction
When a reverse bias voltage V is applied, the width of the depletion region increases
according to:
=

=
2

+
1

(
0
+)
The built-in potential is given by:

0
=

ln(

Solving for x
n
and x
p
we have:

k = 8.62x10
-5
eV/K
(Boltzman constant)
temperature in K
electron charge = 1.6x10
-19
C
The PN Junction

We now can calculate the small-signal capacitance of the PN junction:
Replacing back into the equation for |Q
+
| to find an expression for the charge in the junction:

+
=

= 2

0
+
Taking the derivative:

=

0
1 +

0
=

0

The MOSFET
Bulk or Body
Polysilicon = amorphous (non-crystal) silicon
Silicon dioxide (SiO
2
)
Heavily doped n regions
Width (W)
Side diffusion
The MOSFET
The MOSFET transistor is a FOUR terminal device
In an NMOS transistor the substrate must be always
connected to the most negative supply in the system
The MOSFET
NMOS and PMOS transistors are fabricated on the same substrate
Where should we connect the n-well to?
MOS Symbols
Threshold Voltage
What would happen if we start increasing V
G
?
Depletion region
Threshold Voltage
As V
G
increases, electrons flow from the source to the
region underneath the gate a channel is formed
The gate voltage at which inversion occurs is called
the threshold voltage. As V
G
continues to increase, the
channel charge density increases
Onset of Inversion
After inversion occurs, the transistor resembles two capacitors
in series: the gate oxide capacitor (C
ox
) and the depletion
region capacitor (C
dep
)
Threshold Voltage
The turn-on phenomenon is a gradual function of the
gate voltage.
The threshold (V
TH
) is defined as the gate voltage for
which the interface is as much n-type as the substrate
is p-type.
ox
dep
F MS TH
C
Q
V + u + u = 2
Charge in depletion region
Gate oxide capacitance
per unit area (fF/m
2
)
Difference between work
functions between the polysilicon
and the substrate
Fermi level
Threshold Voltage
The threshold voltage is typically adjusted to a
sufficiently high value to avoid leakage currents.
Threshold adjustment is achieved by implanting
dopants into the channel area.
Inversion Layer for a PFET
Derivation of I-V Curve
v =
d
Q I
Charge density
(coulombs/meter)
Charge velocity
(meter/sec)
Current
(amps)
Derivation of I-V Curve
The inversion charge density must be proportional to V
GS
V
TH
(V
GS
= V
TH
onset of inversion)
For a uniform channel:
Q
d
= W C
ox
(V
GS
V
TH
)
Capacitance
per unit length
Effective
channel voltage
Derivation of I-V Curve
Lets increase the drain voltage V
D
Q
d
= W C
ox
(V
GS
V(x) V
TH
)
Channel
potential at x
V(0)=0 V(L)=V
D
Derivation of the I-V Curve
Recall that Q
d
= I v
Thus,
I
D
= - W C
ox
(V
GS
V(x) V
TH
) v
For solid-state semiconductos:
v = E
But,
E(x) = - dV/dx
Replacing we have
I
D
= W C
ox
( V
GS
V(x) V
TH
)
n
dV(x)/dx
Derivation of the I-V Curve
I
D
= W C
ox
( V
GS
V(x) V
TH
)
n
dV(x)/dx
Multiplying both sides by dx and integrating:



Thus,

( ) dV V x V V WC dx I
DS
V
V
TH GS n ox
L
x
D
=
} }
= = 0 0
) (
( )
|
.
|

\
|
=
2
2
1
DS DS TH GS ox n D
V V V V
L
W
C I
effective channel
length
Derivation of the I-V Curve
( )
|
.
|

\
|
=
2
2
1
DS DS TH GS ox n D
V V V V
L
W
C I
quadratic
function
overdrive
voltage
TH GS DS
V V V <<
Triode Region
( )
TH GS ox n
D
DS
on
V V
L
W
C
I
V
R

= =

1
Saturation Region
Saturation Region
Recall that

What happens if V(x)=V
GS
-V
TH
?
Channel is pinched off inversion layer stops
before x=L

Q
d
= W C
ox
(V
GS
V(x) V
TH
)
Saturation Region
Lets revisit the I
D
equation derivation:


( ) dV V x V V WC dx I
TH GS
V V
V
TH GS n ox
L
x
D
=
} }

= = 0 0
) (
'

( )
2
2
1
TH GS ox n D
V V
L
W
C I =
I
D
is independent
of V
DS
In Summary
Triode Region (V
DS
<= V
GS
- V
THN
):



Saturation Region (V
DS
> V
GS
- V
THN
):


( )
|
.
|

\
|
=
2
2
1
DS DS THN GS ox n D
V V V V
L
W
C I
( )
2
2
1
THN GS ox p D
V V
L
W
C I =
For a PMOS Transistor
Triode Region (V
SD
<= V
SG
- |V
THP
|):



Saturation Region (V
SD
> V
SG
- |V
THP
|):


( )
|
.
|

\
|
=
2
2
1
SD SD THP SG ox n D
V V V V
L
W
C I
( )
2
2
1
THP SG ox p D
V V
L
W
C I =
Graphically
MOSFETs as Current Sources
Transconductance
In saturation, the I
D
is a function of V
GS
Changes in V
GS
result in changes in I
D
The transconductance (g
m
) is defined as





Think of g
m
as the sensitivity of the device
const V
GS
D
m
DS
V
I
g
=
c
c
=
( )
TH GS ox n m
V V
L
W
C g =
Transconductance


Combining this equation with :





The transconductance is a small signal parameter
( )
TH GS ox n m
V V
L
W
C g =
( )
2
2
1
THN GS ox p D
V V
L
W
C I =
D ox n m
I
L
W
C g 2 =
TH GS
D
m
V V
I
g

=
2
Transconductance
How would g
m
behave as W/L is increased (for a constant V
GS
-V
TH
)?
Second Order Effects
The Body Effect
So far we have assumed that the source and the bulk
were both tied to ground.
What happens if V
B
< V
S
?





Are the Source and Drain junction reverse biased?

The Body Effect
Lets assume that V
D
=V
S
=0
and no inversion layer has
formed yet.
As V
B
< 0, holes are attracted
to the bulk depletion
region becomes wider.
Recall that
Thus, as V
B
V
TH
It can be shown that:
ox
dep
F MS TH
C
Q
V + u + u = 2
0
( )
F SB F TH TH
V V V u + u + = 2 2
0

ox
sub Si
C
N qc

2
=
Channel Length Modulation
Recall that after pinch off, the channel length decreases as V
D

increases.



We can write L = L-L or by equivalently


Assuming a linear relationship between L/L and V
DS
, i.e.
L/L=V
DS
and replacing in
L L
L L
L L L L L A +
A +

A
=
A
=
1 1
'
1
( ) ( )
L
L L
L L L
L L
L L
L L
L
/ 1
/
/ 1
'
1
2 2 2
A +
~
A
A +
=
A
A +
=
( )
2
2
1
THN GS ox p D
V V
L
W
C I =
Channel Length Modulation
We get:


Note that I
D
is not independent of V
DS
as assumed before.



( ) ( )
DS THN GS ox p D
V V V
L
W
C I + = 1
2
1
2
Subthreshold Conduction
We have assumed that the transistor turns off when V
GS
<V
TH
In reality this process is gradual and a weak inversion layer
exists for V
GS
V
TH


For V
GS
<V
TH
the transistor does not turn off immediately.
In subthreshold I
D
decreases by 10 for each 80 mV decrease
in V
GS
.
T
GS
V
V
D
e I I

=
,
0
Subthreshold Conduction
What can we say about the transconductance in the
subthreshold regime?



Due to exponential behavior higher gains can be achieved in
this regime but at the cost of speed (I
D
is small in
subthreshold)
GS
D
m
V
I
g
c
c
=
T
D
m
V
I
g

=
,
MOS Device Layout
A layout is a collection of rectangles that define the
geometry of the layers that constitute a device.
The definition of these layers is determined by the
desired electrical properties and the design rules
imposed by the fabrication technology.
MOS Device Layout
MOS Device Capacitances
To predict the AC behavior of a transistor we need to
take into account the parasitic capacitances.
ox
WLC C =
1
Oxide capacitance between
gate and channel
F
sub Si
N q
WL C
u
=
4
2
c
Depletion capacitance
between channel and
substrate
ov
WC C C = =
4 3
Overlap
capacitance
jsw j
C C C C + = =
6 5
Junction
capacitance
between
Source / Drain
and substrate
MOS Device Capacitances
Oxide capacitance between gate and channel:

Depletion capacitance between channel and substrate:


Overlap capacitance:

Junction capacitance between Source / Drain and
substrate:
ox
WLC C =
1
F
sub Si
N q
WL C
u
=
4
2
c
CGDO W CGSO W C LD W C L W WC C C
ox ox ov ov
= = = = = =
4 3
jsw j
C C C C + = =
6 5
m
DB
D j
j
V
A C
C
|
|
.
|

\
|
u
+

=
0
0
1
sw m
DB
D sw j
jsw
V
P C
C

|
|
.
|

\
|
u
+

=
0
0
1
MOS Device Capacitances
Junction capacitance between Source / Drain and
substrate:
jsw j
C C C C + = =
6 5
m
DB
D j
j
V
A C
C
|
|
.
|

\
|
u
+

=
0
0
1
sw m
DB
D sw j
jsw
V
P C
C

|
|
.
|

\
|
u
+

=
0
0
1
CJ
CJSW
MJSW
MJ
MOS Device Capacitances
Junction capacitance between
Source / Drain and substrate:
sw m
DB
D sw j
m
DB
D j
DB
V
P C
V
A C
C

|
|
.
|

\
|
u
+

+
|
|
.
|

\
|
u
+

=
0
0
0
0
1 1
sw m
SB
S sw j
m
SB
S j
SB
V
P C
V
A C
C

|
|
.
|

\
|
u
+

+
|
|
.
|

\
|
u
+

=
0
0
0
0
1 1
MOS Device Capacitances
When the transistor is OFF:



When the transistor is in the triode region:
2
C WLC C
ox GB
=
CGSO W WC C C
ov GS
= = =
3
CGDO W WC C C
ov GD
= = =
4
eff GB
L CGBO C =
ox ox eff ox ov ox eff GS
C LD W C WL C WL C WL C C C + = + = + =
2
1
2
1
2
1
3 1
ox ox eff ox ov ox eff GD
C LD W C WL C WL C WL C C C + = + = + =
2
1
2
1
2
1
4 1
CGSO
CGDO
(CGBO = Overlap capacitance between gate and bulk)
MOS Device Capacitances
When the transistor is in the saturation region:
eff GB
L CGBO C =
ox ox eff ox ov ox eff GS
C LD W C WL C WL C WL C C C + = + = + =
3
2
3
2
3
2
3 1
ox ox ov GD
C LD W C WL C C = = =
4
CGSO
CGDO
MOS Device Capacitances
MOS Small Signal Model
If the perturbation in bias conditions is small, an
approximation of the large signal model can be used.
This approximation is called the small signal model
and it is a linear model.
The model is derived by introducing a small increment
in a bias point and observing the resulting increment
in other bias parameters
MOS Small Signal Model
( )
2
2
1
TH GS ox n D
V V
L
W
C I =
const V
GS
D
m
DS
V
I
g
=
c
c
=
MOS Small Signal Model
( ) ( )
DS TH GS ox n D
V V V
L
W
C I + = 1
2
1
2
0
1
r V
I
DS
D
=
c
c
( )
D
TH GS ox n
D
DS
I
V V
L
W
C
I
V
r

1
2
1
1
2
0
~

=
c
c
=
MOS Small Signal Model
( ) ( )
DS TH GS ox n D
V V V
L
W
C I + = 1
2
1
2
( )
|
|
.
|

\
|
c
c
=
c
c
=
BS
TH
TH GS ox n
BS
D
mb
V
V
V V
L
W
C
V
I
g
( )
F SB F TH TH
V V V u + u + = 2 2
0

SB F SB F SB
TH
BS
TH
V V V
V
V
V
+ u
=
+ u
=
c
c
=
c
c
2 2 2
1
2

( )
|
|
.
|

\
|
+ u
=
c
c
=
SB F
TH GS ox n
BS
D
mb
V
V V
L
W
C
V
I
g
2 2

m
g
q
MOS Small Signal Model
High-Frequency Small Signal Model
SPICE Models Level 1
SPICE Models Level 49
.MODEL CMOSN NMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 1.42E-8 +XJ = 1.5E-7 NCH = 1.7E17 VTH0 = 0.6016005
+K1 = 0.9443225 K2 = -0.1133787 K3 = 25.4656036
+K3B = -8.511885 W0 = 1.067822E-8 NLX = 1E-9
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 0.7840513 DVT1 = 0.3287764 DVT2 = -0.5
+U0 = 453.6276921 UA = 1.03161E-13 UB = 1.447392E-18
+UC = -7.50981E-14 VSAT = 2E5 A0 = 0.6164252 +AGS = 0.1245654 B0 = 2.369807E-6 B1 = 5E-6
+KETA = -6.89452E-3 A1 = 0 A2 = 0.3
+RDSW = 916.2918326 PRWG = 0.1544315 PRWB = 0.0516706
+WR = 1 WINT = 2.136244E-7 LINT = 7.925173E-8
+XL = 1E-7 XW = 0 DWG = -1.047546E-8
+DWB = 4.065077E-8 VOFF = -9.263199E-5 NFACTOR = 0.9941433
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 1.557647E-3 ETAB = 0.1498729
+DSUB = 0.1613682 PCLM = 0.7387149 PDIBLC1 = 0.0163083
+PDIBLC2 = 1.535502E-3 PDIBLCB = 0.1864788 DROUT = 0.05
+PSCBE1 = 5.576893E8 PSCBE2 = 3.78474E-4 PVAG = 6.797846E-3
+DELTA = 0.01 RSH = 85.2 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 1.84E-10 CGSO = 1.84E-10 CGBO = 1E-9
+CJ = 4.159658E-4 PB = 0.8447831 MJ = 0.4331676
+CJSW = 3.570064E-10 PBSW = 0.8 MJSW = 0.1935282
+CJSWG = 1.64E-10 PBSWG = 0.8 MJSWG = 0.1935282
+CF = 0 PVTH0 = -0.0200699 PRDSW = 500
+PK2 = -0.0738424 WKETA = 1.467419E-3 LKETA = 0.0352545 )