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DEL620S Notes
1. Further characteristics of flip-flops
1.1Asynchronous Preset and Clear Inputs
Most integrated circuit flip-flops have asynchronous inputs. These are inputs that
affect the state of the flip-flop independent of the clock. These are normally called
Preset(PRE) and clear(CLR), or direct set (S
D
) and direct reset (R
D
)
.
An active level on the preset input will set the flip -flop and an active level on the
clear input will reset it.
A JK flip-flop with preset and clear inputs is shown in fig 1.0.
Fig 1.0 JK flip-flop with PRESET and CLEAR inputs
These inputs are active-LOW, as indicator by the bubbles. That means for them to be
active, the input must be logic 0. For synchronous operation (ie When we want the
flip-flop to be respond to triggering clock), both preset and clear inputs must be kept
HIGH.
1.2 Flip-flops operating characteristics
1.2.1 Propagation delay times
A propagation delay time is the interval of time required after an input signal has
been applied for the resulting output change to occur. These are four categories of
propagation delay;
1. Propagation delay t
PLH
as measured from the triggering edge of the clock pulse to
the LOW to HIGH transition of output Fig 1.1
Fig 1.1 LOW-to-HIGH transition delay time
2
2. Propagation delay t
PHL
as measured from the triggering edge of the clock pulse to
the HIGH-to-LOW transition of the output (Fig 1.2).
Fig 1.2 Propagation delay time for HIGH-to-LOW transition
3. Propagation delay t
PLH
as measured from the leading edge of the preset input to
the LOW-to-HIGH transition of output(Fig 1.3).
Fig 1.3 Propagation delay time for Preset input to LOW-to-HIGH transition
4. Propagation delay t
PHL
as measured from the leading edge of the clear input to
the HIGH-to-LOW transition of the output(Fig 1.4).
Fig 1.4 Propagation delay time of the clear input to the HIGH-to-LOW transition of
output.
1.2.2 Set-up Time
Set-up time (t
S
) is minimum interval required for the logic levels to be maintained
constantly on the inputs (of J and K, or S and R or D flip -flops) prior to the triggering
edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop.
(Fig 1.5)
Fig 1.5 Set-up-time
3
1.2.3 Hold time (t
h
)
It is the minimum interval required for the logic levels to remain on the inputs after
the triggering edge of the clock pulse in order for the levels to be reliably clocked
into the flip-flop (Fig 1.6).
Fig 1.6 Hold time
1.2.4 Maximum clock frequency
Maximum clock frequency (f
max
) is the highest rate at which the flip-flop can be
reliably triggered. At clock frequencies above the minimum, the flip-flop would be
unable to respond quickly enough, and its operation would be impaired.
1.2.5 Power dissipation
Power dissipation of any digital circuit is the total power consumption of the device.
If the flip-flop operates on a +5V dc source and draws 5 mA of current, power
dissipation is P v
mW
If there are ten flip-flops then
P
mW W
If the flip-flops operate on a 5V dc, then the amount of current that the supply must
provide is I
ohm
Common-anode displays are active-LOW (Low-enable) devices become it takes a
LOW to turn on a segment.
The decoder IC used to drive a common-anode LED display must have
active-LOW outputs.
Common-Cathode LEDs and decoders are also available but are not popular.
3.3 BCD-to-seven-segment Decoder or Driver ICs
The 7447 is the most popular common-anode decoder/LED driver (Fig 3.2).
11
Fig Logic Symbol for 7447 decoder
Basically the 7447 has 4-bit BCD input and seven individual active-LOW outputs
(one for each LED system). It also has a lamp test (LT) input for testing all
segments, and it also has a ripple blanking input and output (BCI and BCO) are
used to suppress zeros (ie display 1.4 or 01.4 or 0046.0910 or 46.091).
To complete the connection between the 7447 and seven-segment LED, sevem
330 ohm resistors (or eight if decimal point is included) for curren t limiting are
needed. There resistors are usually Dual-in-line package resistor (DIP)
Fig 3.3 Logic Circuit connection for seven segment display
Fig 3.3 shows the logic circuit connection. For example if a mod-10 counters
outputs are connected to the BCD input, and the count is at 6 (0110
BCD
), the
decoder will determine that a 0110
BCD
must send the c, d, e, f, g; outputs
LOW (a, b will be HIGH) for a .
The counter will always count from 0 to 9 when dp is 0V.
3.4 Synchronous up/down-counter ICs
Four-bit synchronous binary counters are available in single ICs. Two popular
synchronous ICs, are 74192 and 74193
74192 and 74193 ICs
These ICs can count up or down that is desired. The 74192 is a BCD diode counter
which counts up or down. The 74193 is a 4-bit binary up/down counter. The
logic symbol of the device is drawn in Fig 3.4.
12
Fig 3.4 Logic Symbol of 74192 and 74193 ICs
There are two separate clock inputs namely
Cpu for counting up
Cpd for counting down
One clock must be held HIGH while counting with the other.
Q
0
to Q
3
give binary output count (these are outputs of 4 J -K flip-flops)The
Master Reset for resetting Q outputs to zero. The counter can be preset by
placing any binary value on the parallel data inputs D
0
to D
3
and then driving the
parallel load (PL) line LOW. The parallel load operation will change the counter
outputs regardless of the condition of the clock inputs.
The Terminal Count up TCu and terminal Countdown TCd are normally HIGH.
TCu us used to indicate that maximum count is reached and the count is about
to recycle to zero. The TCu line goes LOW for the 74193 when the count reaches
15 and input clock (Cpu) goes HIGH to LOW. TCu remains LOW until CPu returns
HIGH. The TCu output for 74192goes LOW at 9 and when Cpu goes LOW. The
Terminal Count Down TCD is used to indicate that the minimum count is
reached and is about to recycle to the maximum (15 or 9) count. In this case
TCD goes LOW when the down count reaches zero and the input cloc k CPD goes
LOW.
4.Shift Register
4.1 Introduction
Register are required in digital systems for temporary storage of data bits.
Data bits traveling through a digital system may have to be temporarily stopped,
copied, moved or even shifted to the right or left side.
A shift register facilities this movement and storage of data bits. Shift register can
also be used to convert parallel data bits to serial or vice versa.
Computers operate on data internally on parallel format, but to communicate over a
serial cable like the one on RS232 standard or telephone line data has to be
converted to serial format.
4.2 Parallel-to-Serial Conversion
13
The data storage elements can be D, S-R or J-K flip-flops. Let us look at the operation
of J-K flip-flops Registers.
Recall the truth table of JK flip-flops:
J K Q
n+1+
0 0 Q
n
1 0 1
0 1 0
1 1 Q
n
Toggle
4-bit Parallel in-Serial out register
Fig 4.0 4-bit Parallel-to-serial register
Fig 4.0 shows a 4-bit parallel-to-serial register that is first Reset and then parallel
braded with an active-LOW 7(1000) and then shifted right four positions. Note: 7 in
binary 0111.
Because every J-K input is connected to the preceding stage output, then at each
negative edge of clock, each flip-flop will change to the state of the flip-flop to the
left. In other words all data bits will be shifted one position to the right. Initially R
D
goes LOW, resetting Q
3
to Q
0
to zero. Next, the parallel data are input via D
0
to D
3
input lines. Because the S
D
inputs are active LOW, the complement of the number to
be braded must be used. The S
D
must be returned HIGH before shifting can be
initiated. The complement of 7 is 1000.
The serial output data comes out of the right -end flip-flop (Q
0
).