Lab Mano Final

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET
CIRCUIT DIAGRAM
TRUTH TABLE:
Input x 0 0 1 1 y 0 1 0 1
Output Carry Sum 0 0 0 1 0 1 1 0
K MAP SIMPLIFICATION
0 0 1 0 1
1 1 0 0 1
0 0 0
1 0 1
Sum= xy+xy
Carry= xy
Ex. No 1a
DESIGN AND IMPLEMENTATION OF HALF ADDER USING LOGIC GATES
AIM
To Design and implementation the Half Adder using logic gates.
APPARATUS REQUIRED S. No Apparatus Range Qty
1. 2. 3. 4. 5.
IC 7408, IC 7486, Resister LED Bread Board Connecting wires
330 -
Each 1 1 1 1 As required
THEORY :
A Combinational circuit which performs addition of two bits is called a half adder. It consists of two bit inputs (x and y) and two outputs (Sum and Carry). Sum is LSB Bit and Carry is MSB bit. The truth table gives the relation between input and output variable for half adder operation.
PROCEDURE
1. Check all the given components working properly. 2. Connect the circuit as per the circuit diagram. 3. Give all possible logical inputs as per the truth table. 4. Observe the logical output and verify with your truth table.
RESULT:
Thus the Half adder was designed and implemented using logic gates.
2

CIRCUIT DIAGRAM
TRUTH TABLE:
Input x 0 0 1 1 y 0 1 0 1
Output barrow 0 0 1 0
diff 0 1 1 0
0 0 1 0 1
1 1 0 0 1
0 0 1
1 0 0
diff= xy+xy
barow= xy

DESIGN AND IMPLEMENTATION OF HALF SUBTRACTOR USING LOGIC GATES
Ex. No 1b
AIM
To Design and implement Half Subractor using logic gates.
1. 2. 3. 4. 5.
IC 7408, IC 7404, IC 7486 Resister LED Bread Board Connecting wires
330 -
THEORY :
A Half Subtractor is a Combinational circuit that subtracts two bits and produces their difference. It also has an output to specify if a 1 has been borrowed. Let us designate minuned bit as A and the subtrahend bit as B. The result of operation A-B for all possible values of A and B is given in the truth table.
PROCEDURE
RESULT:
Thus the Half Subractor was designed and implemented using logic gates.
4

CIRCUIT DIAGRAM
TRUTH TABLE:
x 0 0 0 0 1 1 1 1
K MAP SIMPLIFICATION 00 0 1 0 1 01 1 0 11 0 1
Inputs y 0 0 1 1 0 0 1 1
z 0 1 0 1 0 1 0 1
Outputs Carry Sum 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1
10 1 0 0 1
00 0 0
01 0 1
11 1 1
10 0 1
Sum= x xor y xor z
Carry= xy+xz+yz =((x xor y )and z )or(x and y)
Ex. No 1c
DESIGN AND IMPLEMENTATION OF FULL ADDER USING LOGIC GATES
AIM
To Design and implementation the Full Adder using logic gates.
1. 2. 3. 4. 5.
IC 7408, IC 7486, IC7432 Resister LED Bread Board Connecting wires
330 -
FULL ADDER :
A Full Adder is a combinational logic circuit that performs the arithmetic sum of three binary input bits. It consists of three inputs (x, y & z) Two of the input variable denoted by x & y represent the two significant bits to be added. The third input z represents the carry from the previous lower significant position. It consists of two outputs they are Sum and Carry. Sum is LSB Bit and Carry is MSB bit. The truth table gives the relation between inputs and output var iables for full adder operation
PROCEDURE
RESULT:
Thus the Full adder was designed and implemented using logic gates.
6

CIRCUIT DIAGRAM
TRUTH TABLE:
A 0 0 0 0 1 1 1 1 Input B 0 0 1 1 0 0 1 1 Bin 0 1 0 1 0 1 0 1 Output Borrow Difference 0 0 1 1 1 1 1 0 0 1 0 0 0 0 1 1
K MAP SIMPLIFICATION 00 0 1 0 1 01 1 0 11 0 1 10 1 0 0 1 00 0 0 01 1 0 11 1 1 10 1 0
Sum= x xor y xor z
Carry= xy+xz+yz =((x xor y ) and z )or(x and y)
Ex. No 1d
DESIGN AND IMPLEMENTATION OF FULL SUBRACTOR USING LOGIC GATES
AIM
To Design and implementation the Full subractor using logic gates.
1. 2. 3. 4. 5.
IC 7408, IC 7486, IC 7404, IC7432 Resister LED Bread Board Connecting wires
330 -
FULL SUBTRACTOR :
A full subtractoris a combinational circuit that performs a subtraction between two bits, taking into account borrow of the lower significant stage. This circuit has three input and two outputs. The three input are A,B, c in denote the minuend,subtrahend and previous borrow repectively .The two outputs D and Bout represent the difference and output borrow respectively
PROCEDURE
RESULT:
Thus the Full Subractor was designed and implemented using logic gates.

CIRCUIT DIAGRAM
TRUTH TABLE:
BCD CODE B3 B2 B1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0
B0 0 1 0 1 0 1 0 1 0 1
EXCESS 3 CODE E3 E2 E1 E0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0
Ex. No 2 a
DESIGN AND IMPLEMENTATION OF BCD TO EXCESS 3 USING LOGIC GATES
AIM
To Design and implement BCD to Excess 3 code converter using logic gates.
1. 2. 3. 4. 5.
IC 7408, IC 7404, IC7432 Resister LED Bread Board Connecting wires
330 -
THEORY
The availability of a large variety of codes for the same discrete elements of information results in the use of different codes by different digital systems. It is sometimes necessary to use the output of one system as the input to another. A conversion circuit must be inserted between the two systems compatible even though each uses a different binary code. Digital systems can be designed to process data in discrete form only Excess 3 Code is a modified form of a BCD number. The Excess 3 code can be derived from the natural BCD code by adding 3 to each coded number. For example Decimal 12 can be represented in BCD as 0001 0010 . Now adding 3 to each digit we get excess 3 Code 01000101. With this information truth table for BCD to Excess 3 code converter can be determined.
10
00 00 01 11 10 1 1 X 1
01
11
10 1 1 00 01 11 10
00 1 1 X 1
01
11 1 1
10
X X
X X
X X
X X
E0=B0
E1=B0B1+ B0B1
00 00 01 11 10 1 X
01 1
11 1
10 1 00 01
00
01
11
10
1 X 1 X 1
1 X X
1 X X
X 1
X X
X X
11 10
E2=B2B1+B2B0+B2B1B0
E3=B3+B2B1+B2B0
11
PROCEDURE
RESULT:
Thus the BCD to Excess 3 was designed and implemented using logic gates.
12

CIRCUIT DIAGRAM
13
Ex. No 2 b
DESIGN AND IMPLEMENTATION OF EXCESS 3TO BCD USING LOGIC GATES
AIM
To Design and implement Excess 3 to BCD code converter using logic gates.
1. 2. 3. 4. 5. 6. 7. 8.
IC 7408 IC 7404 IC7432 IC7486 Resister LED Bread Board Connecting wires
3 1 1 1
330 -
5 5 1 As required
THEORY
The availability of a large variety of codes for the same discrete elements of information results in the use of different codes by different digital systems. It is sometimes necessary to use the output of one system as the input to another. A conversion circuit must be inserted between the two systems compatible even though each uses a different binary code. Digital systems can be designed to process data in discrete form only. It is sometimes convenient to use Gray codes.
14

TRUTH TABLE:
EXCESS 3 CODE E3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 E2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 E1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 E0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 B4 X X X 0 0 0 0 0 0 0 0 0 0 1 1 1
BCD CODE B3 X X X 0 0 0 0 0 0 0 0 1 1 0 0 0 B2 X X X 0 0 0 0 1 1 1 1 0 0 0 0 0 B1 X X X 0 0 1 1 0 0 1 1 0 0 0 0 1 B0 X X X 0 1 0 1 0 1 0 1 0 1 0 1 0
15
DIGITAL ELECTRONICS LAB MANUAL ECE / CIET Excess 3 Code is a modified form of a BCD number. The Excess 3 code can be derived from the natural BCD code by adding 3 to each coded number. For example Decimal 12 can be represented in BCD as 0001 0010 . Now adding 3 to each digit we get excess 3 Code 01000101. With this information truth table for BCD to Excess 3 code converter can be determined.
16

00 00 01 11 10 X
01 X
11
10 X 00 01
00 X
01 X
11
10 X
11 10
1 1
B4=E3E2(E1+E0)
B3=E3(E2E1E0+E2E1E0)
00 00 01 11 10 1 X
01 X
11
10 X 00 01 11
00 X
01 X 1
11
10 X 1
1 1 1
10
B2=E3E2E1+E3E2E0
B1=(E3+E2) (E1 XOR E0)
00 00 01 11 10 X 1 1 1
01 X
11
10 X 1 1 1
B0=EO
17

PROCEDURE
RESULT:
Thus the Excess 3 to BCD was designed and implemented using logic gates.
18

CIRCUIT DIAGRAM
TRUTH TABLE:
BINARY GODE GRAY CODE B3 B2 B1 B0 G3 G2 G1 G0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

19
0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 1 1 1 1 1 1 1 1 0 0 0 0
1 1 1 1 0 0 0 0 1 1 1 1 0 0
1 0 0 1 1 0 0 1 1 0 0 1 1 0
Ex. No 2 c
DESIGN AND IMPLEMENTATION OF BINARY TO GRAY CODE CONVERTER USING LOGIC GATES
AIM
To Design and implement the binary to gray code converter using logic gates.
1. 2. 3. 4. 5.
IC 7486, Resister LED Bread Board Connecting wires
330 -
1 4 4 1 As required
THEORY
The availability of a large variety of codes for the same discrete elements of information results in the use of different codes by different digital systems. It is sometimes necessary to use the output of one system as the input to another. A conversion circuit must be inserted between the two systems compatible even though each uses a different binary code. Digital systems can be designed to process data in discrete form only. It is sometimes convenient to use Gray codes. The advantage of Gray codes over Binary codes is that only one bit in the code group changes when going from one number to the next. Gray codes are used in application where the normal sequen ce of the binary number may produce an error or ambiguity during the transition from one number to the next. If binary numbers are used a change from 0111 to 1000 may produce an intermediate erroneous number 1001 if the right most bit takes more time to ch ange the other three bits. Gray code eliminates this problem since only one bit changes in value during any transition between any two numbers.
20

00 00 01 11 10 0 0 0 0
01 1 1 1 1
11 0 0 0 0
10 1 1 1 1 00 01 11 10
00 0 1 1 0
01 0 1 1 0
11 1 0 0 1
10 1 0 0 1
G0=B1 XOR B0
G1=B2 XOR B1
00 00 01 11 10 0 1 0 1
01 0 1 0 1
11 0 1 0 1
10 0 1 0 1 00 01 11 10
00 0 0 1 1
01 0 0 1 1
11 0 0 1 1
10 0 0 1 1
G2=B3 XOR B2
G3=B3
21
1. The MSB of the gray numbers is the same as the MSB of the Binary number so write as such. 2. To obtain the next gray digit, perform an exclusive OR operation between the first two binary bits. 3. Similarly, third digit is obtained by XORing 2 nd & 3rd binary digit and so on.
PROCEDURE
RESULT:
Thus the binary to gray code converter was designed and implemented using logic gates.
22

CIRCUIT DIAGRAM
TRUTH TABLE:
G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
GRAY GODE BINARY CODE G2 G1 G0 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0
23
Ex. No 2 d
DESIGN AND IMPLEMENTATION OF GRAY TO BINARY USING LOGIC GATES
AIM
To Design and implement Gray to Binary code converter using logic gates.
1. 2. 3. 4. 5.
IC 7486, Resister LED Bread Board Connecting wires
330 -
1 4 4 1 As required
THEORY
The availability of a large variety of codes for the same discrete elements of information results in the use of different codes by different digital systems. It is sometimes necessary to use the output of one system as the input to another. A conversion circuit must be inserted between the two systems compatible even though each uses a different binary code. Digital systems can be designed to process data in discrete form only. It is sometimes convenient to use Gray codes. The advantage of Gray codes over Binary codes is that only one bit in the code group changes when going from one number to the next. Gray codes are used in application where the normal sequence of the binary number may produce an error or ambiguity during the transition from one number to the next. If binary numbers are used a change from 0111 to 1000 may produce an intermediate erroneous number 1001 if the right most bit takes more time to change the other three bits. Gray code eliminates this problem since only one bit changes in value during any transition between any two numbers.
24

00 00 01 11 10 0 1 0 1
01 1 0 1 0
11 0 1 0 1
10 1 0 1 0 00 01 11 10
00 0 1 0 1
01 0 1 0 1
11 1 0 1 0
10 1 0 1 0
B0= G3 XOR G2 XOR G1 XOR GO
B1=G3 XOR G2 XOR G1
00 00 01 11 10 0 1 0 1
01 0 1 0 1
11 0 1 0 1
10 0 1 0 1 00 01 11 10
00 0 0 1 1
01 0 0 1 1
11 0 0 1 1
10 0 0 1 1
B2=G3 XOR G2
B3=G3
25

PROCEDURE
RESULT:
Thus the Gray to Binary code was designed and implemented using logic gates.
26
DIGITAL ELECTRONICS LAB MANUAL ECE / CIET . CIRCUIT DIAGRAM
TRUTH TABLE:
SUB 0 0 1 1 0 1 0 1
NIBBLE A
NIBBLE B
SUM/DIFFERENCE S3 1 0 0 0 S2 1 0 0 0 S1 0 0 0 1 S0 1 0 1 0
CARRY/ BORROW C4 0 1 0 1
A3 A2 A1 A0 B3 B2 B1 B0 0 0 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1
27
Ex. No 3 a
DESIGN AND IMPLEMENTATION OF FOUR BIT BINARY ADDER/ SUBRACTOR
AIM
To Design and implement the four bit Binary Adder/ Subractor using IC7483.
APPARATUS REQUIRED
S. No
Apparatus
Range
Qty
1. 2. 3. 4. 5.
IC 7486 , IC 7483 Resister LED Bread Board Connecting wires
330 -
THEORY
The addition and subtraction operations can be combined into one circuit with the help of control input (SUB). To add the nibbles, SUB is to be made 0.To subtract B4 B3 B2 B1 from A4 A3 A2 A1 , SUB is to be made 1. EXOR gates function as controlled inverters. When SUB =1, B 4B3 B2 B1 is complemented. Now A4 A3 A2 A1,, complemented version of B4B3 B2 B1 and 1 at Ciin pin are added together. Thus 2s complement of subtrahend, is added with th e minuend. If minuend is less than subtrahend , the obtained output will be the 2s
complement of difference.
28
29

PROCEDURE
1. Check all the given components working properly. 2. Connect the circuit as per the circuit diagram. 3. Make SUB=0 and verify whether it works as a nibble adder. 4. Make SUB=1and verify whether it works as a nibble Subractor 5. Repeat steps 3 and 4 for other nibbles 6. Give all possible logical inputs as per the truth table. 7. Observe the logical output and verify with your truth table.
RESULT:
Thus the four bit Binary Adder/ Subractor was designed and implemented using IC7483.
30

CIRCUIT DIAGRAM
TRUTH TABLE:
NIBBLE A
NIBBLE B
BCD SUM
CARRY C4 0 1 1 0
A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 1 1 1 0 0 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0 1 0 1 1 0 0 0 0 1 0 0 0
31
Ex. No 3 b
DESIGN AND IMPLEMENTATION OF BCD ADDER
AIM
To Design and implement the BCD Adder using IC7483.
1. 2. 3. 4. 5. 6.
IC 7483 IC 7408 Resister LED Bread Board Connecting wires
330 -
2 1 5 5 1 As required
THEORY
A BCD adder adds two BCD digits and produces a sum digit in BCD. The two decimal digits, together with the input carry, are first added in the top 4 bit adder to produce the binary sum. When the output carry is equal to one , binary 0110 is added to the binary sum through the bottom 4 bit adder. The output carry generated from the bottom adder can be ignored , since it supplies information already available at the output carry terminal.
32
33
PROCEDURE
1. Check all the given components working properly. 2. Connect the circuit as per the circuit diagram. 3. Make SUB=0 and verify whether it works as a nibble adder. 4. Make SUB=1and verify whether it works as a nibble Subractor 5. Repeat steps 3 and 4 for other nibbles 6. Give all possible logical inputs as per the truth table. 7. Observe the logical output and verify with your truth table.
RESULT:
Thus the BCD Adder was designed and implemented using IC7483.
34
DIGITAL ELECTRONICS LAB MANUAL ECE / CIET .CIRCUIT DIAGRAM
TRUTH TABLE:
BINARY WORDS A&B A1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 35 A>B 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 OUTPUTS A=B 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 A<B 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0
Ex. No 4 a
DESIGN AND IMPLEMENTATION OF TWO BIT MAGNITUDE COMPARATOR
AIM
To Design and implement the two bit magnitude comparator
1. 2. 3. 4. 5. 6. 7.
IC 7408 IC 7404 IC 7432 Resister LED Bread Board Connecting wires
330 -
2 1 1 3 3 1 As required
THEORY
Magnitude comparator is a logic circuit, which compares two binary numbers and gives the result. It compares two input binary numbers (binary word A&B) and gives three Outputs (A>B, A=, A<B)
If A is greater than B, a logic HIGH appears in A>B output. If A is less than B, a logic HIGH appears in A<B output. If A is equal to B, a logic HIGH appears in A=B output.
36

00 00 01 11 10
1 1 1
01
11
10 00 01
00
1
01
11
10
1 1 1
1 1
11 10
A>B = A 0B1B0+A1B 1+A 1A0B0
A=B = (A 0B0) (A 1B1)
00 00
01
1
11
1 1
10
1 1
01 11 10
A>B = A 1A0B 0+A0B 1 B0+A 1B 1
37
PROCEDURE
RESULT:
Thus the two bit magnitude comparator was designed and implemented using logic gates.
38

CIRCUIT DIAGRAM
TRUTH TABLE:
Comparing input AB A>B
Cascading Input I(A>B) X 1 X 0 0 1 X I(A=B) X 0 1 0 0 0 X I(A<B) X 0 X 1 0 1 X (A>B) 1 1 0 0 1 0 0
Output (A=B) 0 0 1 0 0 0 0 (A<B) 0 0 0 1 1 0 1
A=B A<B
39
Ex. No 4 b
DESIGN AND IMPLEMENTATION OF 8 BIT MAGNITUDE COMPARATOR
AIM
To Design and implement the eight bit magnitude comparator
1. 2. 3. 4. 5.
IC 7485 Resister LED Bread Board Connecting wires
330 -
2 3 3 1 As required
THEORY
Magnitude comparator is a logic circuit, which compares two binary numbers and gives the result. It compares two input binary numbers (binary word A&B) and gives three Outputs (A>B, A=, A<B)
If A is greater than B, a logic HIGH appears in A>B output. If A is less than B, a logic HIGH appears in A<B output. If A is equal to B, a logic HIGH appears in A=B output. In the case of 8 bit comparator using IC74682, If A>B a logic low appears at pin no.1 (A>B, output) If A=B a logic low appears at pin no.19 (A=B, output) If A<B a logic high appears at both pin nos.19&1 (A=B, output) 8 bit comparison is obtained by cascading two 7485 ICs as shown in the logic diagram.The outputs of 1 st IC 7485 i.e [ A>B,A=B,A<B ] are given to the respective I(A>B), I(A=B),I(A<B) of 2 nd IC7485. Depending upon the input condition the corresponding output of the 2 nd IC 7485 goes high. A 8-bit comparator is obtained by cascading 2 IC 7465 in series as shown. The o/p of first comparator is given as cascade input to the second comparator .The 8 -bit comparator Output is available at the output of the second comparator.
40

PIN DIAGRAM
16 VCC 15 A3 14 B2 13 A2 12 A1 11 B1 10 A0 9 B0
IC 7485
B3 1
1(A<B) 2
1(A=B) 3
1(A>B) 4
A>B 5
A=B 6
A<B 7
GND 8
41

PROCEDURE
RESULT:
Thus the 8 bit magnitude comparator was designed and implemented using IC 7485.
42

CIRCUIT DIAGRAM
TRUTH TABLE:
Input No of High data PE i/p (I 0 I7) Even Odd Even Odd X X 1 1 0 0 1 0 0 0 1 1 1 0 PO
Output
7E 7O
1 0 0 1 0 1
0 1 1 0 0 1
43
Ex. No 5
DESIGN AND IMPLEMENTATION OF 16 BIT ODD/ EVEN PARITY CHECKER AND GENERATOR
AIM
To Design and implement the 16 bit odd/ even parity checker and generator
1. 2. 3. 4. 5.
330 -
1 2 2 1 As required
THEORY
The 74180 is a 9- bit Parity generator or checker commonly used to detect errors in high speed transmission or data retrieval systems. Both even and odd parity enable inputs and parity outputs are available for generating or checking parity on 8- bits. In the function table , true active High or true active low parity can be generated at both the Even or Odd outputs . Active High Parity: True active- High parity is established with Even parity enable input (PE) set high and Odd parity enable input (P O) set Low. Active Low Parity: True active low parity is established when P E is low and PO is High .When both the enable inputs are at same logic level , both outputs will be force d to the opposite logic level.
44

PIN DIAGRAM
VCC 14
13 I5
12 I4
11 I3
10 I2
9 I1
8 I0
IC 74180
I6 1
I7 2
PE 3
P0 4
Ee 5
E0 6 7 GND
45
DIGITAL ELECTRONICS LAB MANUAL ECE / CIET Parity Checking : Parity Checking of a 9 bit word ( 8 - bit plus parity ) is possible by using the two enable input plus an inverter as the ninth data Checking Active High Parity :
y y
Ninth data input is tied to the P O input. Inverter is connected between P O and PE
Checking Active Low Parity :

y y
Ninth data input is tied to the P E input. Inverter is connected between P O and PE
Expansion to larger word size is accomplished by serially cascading the 74180 in 8- bit increments. The Even and odd parity outputs of the first stages are connected to the corresponding P O and PE inputs , respectively of the succeeding stage.
PROCEDURE
RESULT:
Thus the 8 bit magnitude comparator was designed and implemented using IC 74180.
46

CIRCUIT DIAGRAM
TRUTH TABLE:
S1 0 0 1 1
S0 0 1 0 1
Y I0 I1 I2 I3
47
Ex. No 6 a
DESIGN AND IMPLEMENTATION OF 4x1 MULTIPLEXER USING LOGIC GATES
AIM
To Design and implement the 4X1 Multiplexer using logic gates.
1. 2. 3. 4. 5. 6.
330 -
THEORY
Multiplexer is a combinational circuit which can select any one of the inputs and route it to the output . A multiplexer has data input lines, data select lines and output. The logic symbol of a 4 line to 1 line MUX is shown. According to the two bit binary code on the data select inputs, corresponding data input line will be selected and routed to output. For example if s1s0 i s 00, D0 will be selected , if s1s0 is 01, D1 will be selected and so on. From the truth table it can be seen that output. Y= D0 S1S0 + D1S1S0 + D2S1S0 +D3S1S0 This Boolean expression can be realised using gates.
PROCEDURE
RESULT:
Thus the 4X1 Multiplexer was designed and implemented using logic gates.
48

CIRCUIT DIAGRAM
TRUTH TABLE:
S3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
S2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
49
S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Y I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15
Ex. No 6 b
DESIGN AND IMPLEMENTATION OF 16x1 MULTIPLEXER USING IC 74150
AIM
To Design and implement the 16X1 Multiplexer using IC 74150.
1. 2. 3. 4. 5.
330 -
1 1 1 1 As required
THEORY
IC74150 is a 16 line to 1 MUX. It has 16 data inputs D 0 through D15 and 4 data select inputs. The output is the complement of the input data. Strobe input active low. For example if ABCD is 0001 , the output will be D 1
PROCEDURE
1. Check all the given components working properly. 2. Connect the circuit as per the circuit diagram. 3. Give all possible logical inputs as per the truth table. 4. Observe the logical output and verify w ith your truth table.
RESULT:
Thus the 4X1 Multiplexer was designed and implemented using IC74150.
50

CIRCUIT DIAGRAM
TRUTH TABLE:
S1 0 0 1 1
S0 0 1 0 1
o/p D0 D1 D2 D3
51
Ex. No 6 c
DESIGN AND IMPLEMENTATION OF 1X4 DEMULTIPLEXER USING LOGIC GATES
AIM
To Design and implement the 1X4 Demultiplexer using logic gates.
1. 2. 3. 4. 5. 6.
330 -
THEORY
Demultiplexer does the reverse operation of the Multiplexer. The data on a line is distributed on any one of the output line according to the binary code on data select lines. The logic symbol of a 1 to 4 line demultiplexer is shown. When the input on data select inputs S1S0 is 00 , data on the data line will be available on D0 output , so on.
PROCEDURE
RESULT:
Thus the 1X4 Demultiplexer was designed and implemented using logic gates.
52

CIRCUIT DIAGRAM
TRUTH TABLE:
S3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
S2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
53
S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
O/P D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
Ex. No 6 d
DESIGN AND IMPLEMENTATION OF 1X16 DEMULTIPLEXER USING IC 74150
AIM
To Design and implement the 16X1 Multiplexer using IC 7415 4.
1. 2. 3. 4. 5.
330 -
1 16 16 1 As required
THEORY
IC74154 is a 1 to 16 demultiplexer. It has a data input D and 16 output Y 0 through Y15 and an active low strobe input. The data select inputs ABCD decides the output pin at which the data should be available. For example if ABCD is 0001,data input will be available at Y 1.
PROCEDURE
RESULT:
Thus the 1X16 Demultiplexer was designed and implemented using IC74154.
54

CIRCUIT DIAGRAM
TRUTH TABLE:
D3 1 0 0 0
D2 0 1 0 0
D1 0 0 1 0
DO 0 0 0 1
X 0 0 1 1
Y 0 1 0 1
55
Ex. No 7 a
DESIGN AND IMPLEMENTATION OF 4X2 ENCODER USING LOGIC GATES
AIM
To Design and implement the 4X2 encoder using logic gates.
1. 2. 3. 4. 5.
330 -
1 2 2 1 As required
THEORY
Encoder is an combinational circuit that performs inversion operation of decoder. An encoder has 2 n input lines and n output lines. The output lines generate the binary code corresponding to the input value. The encoder is implemented using OR gate .
PROCEDURE
RESULT:
Thus the 4x2 Encoder was designed and implemented using logic gates.
56

CIRCUIT DIAGRAM
TRUTH TABLE:
D0 0 1 1 1 1 1 1 1 1 1
D1 1 0 1 1 1 1 1 1 1 1
D2 1 1 0 1 1 1 1 1 1 1
D3 1 1 1 0 1 1 1 1 1 1
D4 1 1 1 1 0 1 1 1 1 1
D5 1 1 1 1 1 0 1 1 1 1
D6 1 1 1 1 1 1 0 1 1 1
D7 1 1 1 1 1 1 1 1 0 1
D8 1 1 1 1 1 1 1 1 1 0
Q0 1 1 1 1 1 1 1 0 0 0
Q1 1 1 1 0 0 0 0 1 1 1
Q2 1 0 0 1 1 0 0 1 1 0
Q3 0 1 0 1 0 1 0 1 0 1
57
Ex. No 7 b
DESIGN AND IMPLEMENTATION OF ENCODER USING IC 74147
AIM
To Design and implement the encoder using IC 74147.
1. 2. 3. 4. 5.
330 -
1 4 4 1 As required
THEORY
Encoder is an combinational circuit that performs inversion operation of decoder. An encoder has 2 n input lines and n output lines. The output lines generate the binary code corresponding to the input value. The encoder is implemented using OR gate.
PROCEDURE
1. Check all the given components working properly. 2. Connect the circuit as per the circuit diagr am. 3. Give all possible logical inputs as per the truth table. 4. Observe the logical output and verify with your truth table.
RESULT:
Thus the encoder was designed and implemented using IC74147.
58

CIRCUIT DIAGRAM
59
Ex. No 7 C
DESIGN AND IMPLEMENTATION OF 2X4 DECODER USING LOGIC GATES
AIM
To Design and implement the 2X4 decoder using logic gates.
1. 2. 3. 4. 5.
330 -
1 2 2 1 As required
THEORY
A Decoder, which has an n-bit binary input code and a one activated o/p out of 2 n Output code is called biary Decoder. A binary decoder is used when it is necessary to activate exactly one of 2 n o/ps based on n-bit value. In the truth table of 2 to 4 decoder, if enable input is 1 (EN =1) One and only one of the o/ps. y0 to y3 is active for a given input .the o/p y 0 is active ,when output A=B=0, the o/p y1 is active ,when i/p A=o and B=1 .If ena ble input is 0 , (i.e.) EN =0 ,then all the o/ps are 0.Decoder Circuits are commonly used for binary to decimal conversion. BCD to decimal Decoder is also referred as 1 of 10 decoder, as only one of the ten outputs lines is high or low at a time.
60
TRUTH TABLE:
S1 0 0 1 1
S0 0 1 0 1
D3 1 0 0 0
D2 0 1 0 0
D1 0 0 1 0
DO 0 0 0 1
61
PROCEDURE
RESULT:
Thus the 2X4 Decoder was designed and implemented using logic gates.
62
CIRCUIT DIAGRAM
TRUTH TABLE:
A 0 0 0 0 0 0 0 0 1 1
B 0 0 0 0 1 1 1 1 0 0
C 0 0 1 1 0 0 1 1 0 0
D 0 1 0 1 0 1 0 1 0 1
D0 0 1 1 1 1 1 1 1 1 1
D1 1 0 1 1 1 1 1 1 1 1
D2 1 1 0 1 1 1 1 1 1 1
D3 1 1 1 0 1 1 1 1 1 1
D4 1 1 1 1 0 1 1 1 1 1
D5 1 1 1 1 1 0 1 1 1 1
D6 1 1 1 1 1 1 0 1 1 1
D7 1 1 1 1 1 1 1 1 0 1
D8 1 1 1 1 1 1 1 1 1 0
63
Ex. No 7 d
DESIGN AND IMPLEMENTATION OF DECODER USING IC 7445
AIM
To Design and implement the decoder using IC 7445.

1. 2. 3. 4. 5.
330 -
1 4 4 1 As required
THEORY
A Decoder, which has an n-bit binary input code and a one activated o/p out of 2 n Output code is called biary Decoder. A binary decoder is used when it is necessary to activate exactly one of 2 n o/ps based on n-bit value. In the truth table of 2 to 4 decoder, if enable input is 1 (EN =1) One and only one of the o/ps. y0 to y3 is active for a given input .the o/p y 0 is active ,when output A=B=0, the o/p y1 is active ,when i/p A=o and B=1 .If ena ble input is 0 , (i.e.) EN =0 ,then all the o/ps are 0.Decoder Circuits are commonly used for binary to decimal conversion. BCD to decimal Decoder is also referred as 1 of 10 decoder, as only one of the ten outputs lines is high or low at a time.
PROCEDURE
RESULT:
Thus the decoder was designed and implemented using IC7445.
64

CIRCUIT DIAGRAM
65
Ex. No 8 a
DESIGN AND IMPLEMENTATION OF 4 BIT RIPPLE COUNTER
AIM
To Design and implement the 4 bit ripple counter.
1. 2. 3. 4. 5.
330 -
2 4 4 1 As required
THEORY
Asynchronous counter consists of series connections of flipflops JK type, With each flipflop connected to clock pulse of the next higher order flipflop. The Flipflop holding the least significant bit receives the incoming count pulse. It is obvious that the lower order bit Q 0 is complemented with each count pulse. When Q0 goes from 1 to 0, it complements Q1. When Q1 goes from 1 to 0 it complements Q2 and so on. The output transitio n of Q3 if connected to next stage will not trigger the next flipflop since it goes from 0 to 1. The flipflop changes one at a time in rapid succession and the signal propagates through the counter in ripple fashion and some times called as ripple counte r. In the circuit satup all flipflopa are clocked by the Q output of the preceeding flipflop. JK inputs of all the F/F are connected to a high state.A Ripple counter comprising of n F/F can be used to Count upto 2 n pulses. The counter gives a natural binary count from 0 to 15 and resets to initial condition on the 16 th input pulse.
66

TRUTH TABLE:
OUTPUTS CLOCK Q3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 Q2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 Q1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Q0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
67

PROCEDURE
1. Check all the given components working properly. 2. Connect the circuit as per the circuit diagram. 3. Apply Count Pulse to the circuit. 4. Observe the output and verify with your truth table.
RESULT:
Thus the 4 bit ripple counter was designed and implemented using JK flip flop.
68

CIRCUIT DIAGRAM
69
Ex. No 8 b
DESIGN AND IMPLEMENTATION OF MOD 10 COUNTER
AIM
To Design and implement the MOD 10 counter.
1. 2. 3. 4. 5. 6.
330 -
THEORY
Asynchronous counter consists of series connections of flipflops JK type, With each flipflop connected to clock pulse of the next higher order flipflop. The Flipflop holding the least significant bit receives the incoming count pulse. It is obvious that the lower order bit Q 0 is complemented with each count pulse. When Q0 goes from 1 to 0, it complements Q1. When Q1 goes from 1 to 0 it complements Q2 and so on. The output transition of Q 3 if connected to next stage will not trigger the next flipflop since it goes from 0 to 1. The flipflop changes one at a time in rapid succession and the s ignal propagates through the counter in ripple fashion and some times called as ripple counter. The Circuit of the decade counter is similar to 4 bit ripple counter but with the aid of the logic circuit, the count is limited to 9 . As soon as the count 1010 takes place , a NAND gate clears the F/F and Counting restarts from 0 .
70

TRUTH TABLE:
OUTPUTS CLOCK Q3 0 1 2 3 4 5 6 7 8 9 10 0 0 0 0 0 0 0 0 1 1 0 Q2 0 0 0 0 1 1 1 1 0 0 0 Q1 0 0 1 1 0 0 1 1 0 0 0 Q0 0 1 0 1 0 1 0 1 0 1 0
71

PROCEDURE
RESULT:
Thus the MOD 10 counter was designed and implemented using JK flip flop.
72

CIRCUIT DIAGRAM
73
Ex. No 8 c
DESIGN AND IMPLEMENTATION OF MOD 12 COUNTER
AIM
To Design and implement the MOD 12 counter.
1. 2. 3. 4. 5. 6.
330 -
THEORY
Asynchronous counter consists of series connections of flipflops JK type, With each flipflop connected to clock pulse of the next higher order flipflop. The Flipflop holding the least significant bit receives the incoming count pulse. It is obvious that the lower order bit Q 0 is complemented with each count pulse. When Q0 goes from 1 to 0, it complements Q1. When Q1 goes from 1 to 0 it complements Q2 and so on. The output transition of Q 3 if connected to next stage will not trigger the next flipflop since it goes from 0 to 1. The flipflop changes one at a time in rapid succession and the signal propagates through the counter in ripple fashion and some times called as ripple counter. MOD 12 counter requires 4 stages of F/F. Here , the count is limited to 11. As soon as the count 1100 takes place, a NAND gate clears the F/F and the Counting restarts from 0.
74

TRUTH TABLE:
OUTPUTS CLOCK Q3 0 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 0 0 0 0 0 1 1 1 1 0 Q2 0 0 0 0 1 1 1 1 0 0 0 0 0 Q1 0 0 1 1 0 0 1 1 0 0 1 1 0 Q0 0 1 0 1 0 1 0 1 0 1 0 1 0
75

PROCEDURE
RESULT:
Thus the MOD 12 counter was designed and implemented using JK flip flop.
76

CIRCUIT DIAGRAM
U4A
C R
M
U6A 1 2
IG
1 2 13
12 1
U5A 3 2
7411
U4B U1A U3A 14 1 3 J CLK K Q 13 CL 2 Q 12 1 3 2 5 7 J CLK K Q 8 CL Q 9 14 1 3 U1B 3 4 5 6
7432
U2A 12
J CLK K
7473
7473
Q 13 CL
7486
10
7404
77
Ex. No 9
DESIGN AND IMPLEMENTATION OF SYNCHRONOUS UP DOWN COUNTER
AIM
To Design and implement the Synchronous up down counter.
1. 2. 3. 4. 5. 6. 7. 8.
IC 7476 IC 7411 IC 7432 IC 7404 Resister LED Bread Board Connecting wires
2 1 1 1
330 -
3 3 1 As required
THEORY
A circuit of a 3-bit synchronous up-down counter and a table of its sequence are shown below. Similar to an asynchronous up -down counter, a synchronous up-down counter also has an up-down control input. It is used to control the direction of the counter through a certain sequence
y y
for both the UP and DOWN sequences, Q0 toggles on each clock pulse. for the UP sequence, Q1 changes state on the next clock pulse when Q0=1.
for the DOWN sequence, Q1 changes state on the next clock pulse when Q0=0.
for the UP sequence, Q2 changes state on the next clock pulse when Q0=Q1=1.
for the DOWN sequence, Q2 changes state on the next clock pulse when Q0=Q1=0.
78

TRUTH TABLE:
Present state Mode 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Q2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 Q1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 Q0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 Q2 0 0 0 1 1 1 1 0 1 1 1 0 0 0 0 1 Next State Q1 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1 Q0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 JK F/F Inputs
J0
1 X 1 X 1 X 1 X X 1 X 1 X 1 X 1
K0 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X
J1 0 1 X X 0 1 X X X X 0 1 X X 0 1
K1 X X 0 1 X X 0 1 0 1 X X 0 1 X X
J2 0 0 0 1 X X X X X X X X 0 0 0 1
K2 X X X X 0 0 0 1 0 0 0 1 X X X X
79

PROCEDURE
1. Check all the given components working properly. 2. Connect the circuit as per the circuit diagram. 3. Apply Up=1 and clock pulse. 4. Apply Up=0, Down=1 and clock pulse 5. Observe the output and verify with your truth table.
80

00 00 01 11 10 0 0 1 1
01 1 1 0 0
11 X X X X
10 X X X X 00 01 11 10
00 X X X X
01 X X X X
11 1 1 0 0
10 0 0 1 1
J1 = M Q0 + M Q0
K1 = MQ0 + MQ0
00 00 01 X 11 X 10 1 0
01 0 X X 0
11 1 X X 0
10 0 X X 0 00
00 X 01 0 11 1 10 X
01 X 0 0 X
11 X 1 0 X
10 X 0 0 X
J2 = MQ1Q0 + MQ1Q0
K2 = MQ1Q0 + MQ1Q0
81
RESULT:
Thus the Synchronous counter was designed and implemented using JK flip flop.
82

CIRCUIT DIAGRAM
TRUTH TABLE:
CLK 1 2 3 4 5 6 7
SI 1 0 1 1 0 0 1
S0 x x x 1 0 1 1
83
Ex. No 10 a
DESIGN AND IMPLEMENTATION OF SISO
AIM
To Design and implement the SISO using D flip flop.
1. 2. 3. 4. 5.
330 -
2 1 1 1 As required
THEORY
A register is simply a group of flip flops that can be used to store a binary number. A shift register is nothing but a register which accepts a binary number and shifts it. The data can be entered to the shift register either in serial or parallel. Similarly, the output can be taken from it either in parallel. Since there are two ways to shift data into a shift register and similarly two ways to shift data out of register, four basic register types can be constructed viz, serial in serial out(SISO), parallel in serial out(PISO), serial in parallel out(SIPO) and parallel in parallel out (PIPO)shift register. It allows the data to enter serially. The outp ut data can be available in parallel or serial
PROCEDURE
1. Check all the given components working properly. 2. Connect the circuit as per the circuit diagram. 3. Give serial inputs SI and clock to the circuit. 4. Observe the logical output S0 and verify with your truth table.
RESULT:
Thus the SISO was designed and implemented using D flip flop.
84

CIRCUIT DIAGRAM
TRUTH TABLE:
CLK 1 2 3 4 5 6 7
SI 1 0 1 1 0 0 1
P0 1 0 1 1 0 0 1
P1 X 1 0 1 1 0 0
P2 X X 1 0 1 1 0
P3 X X X 1 0 1 1
85
Ex. No 10 b
DESIGN AND IMPLEMENTATION OF SIPO
AIM
To Design and implement the SIPO using D flip flop.
6. 7. 8. 9. 10.
330 -
2 4 4 1 As required
THEORY
A register is simply a group of flip flops that can be used to store a binary number. A shift register is nothing but a register which accepts a binary number and shifts it. The data can be entered to the shift register either in serial or parallel. Similarly, the output can be taken from it either in parallel. Since there are two ways to shift data into a shift register and similarly two ways to shift data out of register, four basic register types can be constructed viz, serial in serial out(SISO), parallel in serial out(PISO), serial in parallel out(SIPO) and parallel in parallel out (PIPO)shift register. It allows the data to enter serially. The output data can be available in parallel or serial In this type of shift register data can be fed in serial or parallel using the mode control pin. Output can be taken serial or in parallel. Serial input is fed through A input and parallel input is fed through ABCD. Serial output is taken from Q D and parallel output from Q A QB QC QD.
86
87
PROCEDURE
1. Check all the given components working properly. 2. Connect the circuit as per the circuit diagram. 3. Give serial inputs SI and clock to the circuit. 4. Observe the logical output S0 and verify with your truth table.
RESULT:
Thus the SIPO was designed and implemented using D flip flop.
88

CIRCUIT DIAGRAM
89
Ex. No 10 c
DESIGN AND IMPLEMENTATION OF PISO
AIM
To Design and implement the PISO using D flip flop.
11. 12. 13. 14. 15.
330 -
2 1 1 1 As required
THEORY
A register is simply a group of flip flops that can be used to store a binary number. A shift register is nothing but a register which accepts a binary number and shifts it. The data can be entered to the shift register either in serial or parallel. Similarly, the output can be taken from it either in parallel. Since there are two ways to shift data into a shift register and similarly two ways to shift data out of register, four basic register types can be constructed viz, serial in serial out(SISO), parallel in serial out(PISO), serial in parallel out(SIPO) and parallel in parallel out (PIPO)shift register. It allows the data to enter serially. The output data can be available in parallel or serial
PROCEDURE
1. Check all the given components working properly. 2. Connect the circuit as per the circuit diagram. 3. Give serial inputs and clock to the circuit. 4. Observe the logical output and verify with your truth table.
RESULT:
Thus the PISO was designed and implemented using D flip flop.
90

CIRCUIT DIAGRAM
91
Ex. No 10 d
DESIGN AND IMPLEMENTATION OF PIPO
AIM
To Design and implement the PIPO using D flip flop.
16. 17. 18. 19. 20.
330 -
2 4 4 1 As required
THEORY
A register is simply a group of flip flops that can be used to store a binary number. A shift register is nothing but a register which accepts a binary number and shifts it. The data can be entered to the shift register either in serial or parallel. Similarly, the output can be taken from it either in parallel. Since there are two ways to shift data into a shift register and similarly two ways to shift data out of register, four basic register types can be constructed viz, serial in serial out(SISO), parallel in serial out(PISO), serial in parallel out(SIPO) and parallel in parallel out (PIPO)shift register. It allows the data to enter serially. The output data can be available in parallel or serial
PROCEDURE
1. Check all the given components working properly. 2. Connect the circuit as per the circuit diagram. 3. Give serial inputs and clock to the circuit. 4. Observe the logical output and verify with your truth table.
RESULT:
Thus the PIPO was designed and implemented using D flip flop.
92

Lab Mano Final

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DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

Output Carry Sum 0 0 0 1 0 1 1 0

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

DESIGN AND IMPLEMENTATION OF HALF ADDER USING LOGIC GATES

To Design and implementation the Half Adder using logic gates.

APPARATUS REQUIRED S. No Apparatus Range Qty

IC 7408, IC 7486, Resister LED Bread Board Connecting wires

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

To Design and implement Half Subractor using logic gates.

APPARATUS REQUIRED S. No Apparatus Range Qty

IC 7408, IC 7404, IC 7486 Resister LED Bread Board Connecting wires

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

Outputs Carry Sum 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1

Sum= x xor y xor z

Carry= xy+xz+yz =((x xor y )and z )or(x and y)

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

DESIGN AND IMPLEMENTATION OF FULL ADDER USING LOGIC GATES

To Design and implementation the Full Adder using logic gates.

APPARATUS REQUIRED S. No Apparatus Range Qty

IC 7408, IC 7486, IC7432 Resister LED Bread Board Connecting wires

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

Sum= x xor y xor z

Carry= xy+xz+yz =((x xor y ) and z )or(x and y)

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

DESIGN AND IMPLEMENTATION OF FULL SUBRACTOR USING LOGIC GATES

To Design and implementation the Full subractor using logic gates.

APPARATUS REQUIRED S. No Apparatus Range Qty

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

DESIGN AND IMPLEMENTATION OF BCD TO EXCESS 3 USING LOGIC GATES

APPARATUS REQUIRED S. No Apparatus Range Qty

IC 7408, IC 7404, IC7432 Resister LED Bread Board Connecting wires

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

DESIGN AND IMPLEMENTATION OF EXCESS 3TO BCD USING LOGIC GATES

APPARATUS REQUIRED S. No Apparatus Range Qty

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

B1=(E3+E2) (E1 XOR E0)

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

BINARY GODE GRAY CODE B3 B2 B1 B0 G3 G2 G1 G0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

APPARATUS REQUIRED S. No Apparatus Range Qty

IC 7486, Resister LED Bread Board Connecting wires

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

GRAY GODE BINARY CODE G2 G1 G0 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

DESIGN AND IMPLEMENTATION OF GRAY TO BINARY USING LOGIC GATES

APPARATUS REQUIRED S. No Apparatus Range Qty

IC 7486, Resister LED Bread Board Connecting wires

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

B0= G3 XOR G2 XOR G1 XOR GO

B1=G3 XOR G2 XOR G1

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET . CIRCUIT DIAGRAM

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

DESIGN AND IMPLEMENTATION OF FOUR BIT BINARY ADDER/ SUBRACTOR