2009 IEEE Symposium on Industrial Electronics and Applications (ISIEA 2009), October 4-6, 2009, Kuala Lumpur, Malaysia

A Comparative Study of 6T, 8T and 9T Decanano SRAM cell

Paridhi Athe Electronics and Computer Engineering Dept. IIT Roorkee Roorkee, India athe.paridhi@gmail.com S. Dasgupta Electronics and Computer Engineering Dept. IIT Roorkee Roorkee, India sudebdg@gmail.com

Abstract Data retention and leakage current reduction are among the major area of concern in todays CMOS technology. In this paper 6T, 8T and 9T SRAM cell have been compared on the basis of read noise margin (RNM), write noise margin (WNM), read delay, write delay, data retention voltage (DRV), layout and parasitic capacitance. Corner and statistical simulation of the noise margin has been carried out to analyze the effect of intrinsic parameter fluctuations. Both 8T SRAM cell and 9T SRAM cell provides higher read noise margin (around 4 times increase in RNM) as compared to 6T SRAM cell. Although the size of 9T SRAM cell is around 1.35 times higher than that of the 8T SRAM cell but it provides higher write stability. Due to single ended bit line sensing the write stability of 8T SRAM cell is greatly affected. The 8T SRAM cell provides a write 1 noise margin which is approximately 3 times smaller than that of the 9T SRAM cell. The data retention voltage for 8T SRAM cell was found to be 93.64mV while for 9T SRAM cell it was 84.5mV and for 6T SRAM cell it was 252.3mV. Read delay for 9T SRAM cell is 98.85ps while for 6T SRAM cell it is 72.82ps and for 8T SRAM cell it is 77.72ps. The higher read delay for 9T SRAM cell is attributed to the fact that dual threshold voltage technology has been in it in order to reduce the leakage current. Write delay for 9T SRAM cell was found to be 10ps, 45.47ps for 8T SRAM cell and 8.97ps for 6T SRAM cell. The simulation has been carried out on 90nm CMOS technology. . Keywords6T SRAM cell; 8T SRAM cell; Data retention voltage; Read noise margin; Write noise margin; Intrinsic parameter fluctuation.

better performance new SRAM cells [5] [6] [7] [8] have been introduced. In most of these cell read and write operation are isolated to obtain higher noise margin. In this paper a comparative analysis of 6T, 8T [5] and 9T [6] SRAM cell has been carried out. The major difference between the 8T and 9T SRAM cell is that in case of 8T SRAM cell single bit line has been used while in case of 9T SRAM double bit line as in conventional 6T SRAM cell has been used. All the simulation has been carried on 90 nm CMOS technology. Tools used for the simulation are CADENCE, MATLAB and ORIGIN. II. SRAM CELLS A SRAM cell must be designed in such a way, so that it provides a non destructive read operation and a reliable write operation. In the conventional 6T SRAM cell this condition is fulfilled by appropriately sizing all the transistors in the SRAM cell. Sizing is done according to the cell ratio (CR) [9] and pull up ratio (PR) [9] of the

I. INTRODUCTION For nearly 40 years CMOS devices have been scaled down in order to achieve higher speed, performance and lower power consumption. Due to their higher speed SRAM based Cache memories and System-on-chips are commonly used. Due to device scaling there are several design challenges for nanometer SRAM design. Now we are working with very low threshold voltage and ultra thin gate oxide due to which leakage energy consumption is getting increased. Besides this data stability during read and write operation is also getting affected. Intrinsic parameter fluctuation [1] like random dopant fluctuation [2], line edge roughness [3] and oxide thickness fluctuation [4] further degrades the stability of SRAM cell. In order to obtain higher noise margin along with

Figure 1. 8T SRAM cell

978-1-4244-4683-4/09/$25.00 2009 IEEE

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2009 IEEE Symposium on Industrial Electronics and Applications (ISIEA 2009), October 4-6, 2009, Kuala Lumpur, Malaysia

TABLE I WIDTH OF TRANSISTOR USED FOR SIMULATING 8T SRAM CELL Transistor Width (nm) M1, M2, M3, M4 120 M5 600 M7,M8 480 M6 240

III. SIMULATION RESULTS In this section comparison between conventional 6T, 8T and 9T SRAM cell has been carried out on the basis of read delay, write delay, DRV, RNM, WNM, leakage current, layout and average write power. A. Delay and data retention voltage Simulation results for data retention read delay and write delay is shown in Table IV. Read delay is highest for 9T SRAM cell because high-Vt transistors are used in it, due to which the driving capability of the transistor reduces. Due to the single bit line in 8T SRAM cell its write delay is higher as compared to other SRAM cell. B. Read noise margin Due to intrinsic parameter fluctuation [1] like random dopant fluctuation, line edge roughness and oxide thickness fluctuation the performance and yield of device is greatly affected. To simulate these effects statistical and corner analysis of the SRAM cell has been carried out. The simulation result for corner analysis of read noise margin is shown in Table V. Corner simulation of RNM of SRAM cell with worst case read noise margin is shown in Figure 4, 5 and 6. To perform the statistical analysis of the SRAM cells Monte Carlo simulation of 200 samples has been carried out with 16% deviation in the threshold voltage. Monte Carlo simulation of RNM of 6T, 8T and 9T SRAM cell is shown in Figure 7, 8 and 9 respectively. The result of statistical analysis is tabulated in Table VI.
TABLE II WIDTH OF TRANSISTOR USED FOR SIMULATING 9T SRAM CELL Transistor Width (nm) M1, M2, M3, M4 120 M5, M6 600 M7, M8 240 M9 480 TABLE III THRESHOLD VOLTAGE FOR NOMINAL NMOS/PMOS AND HIGH-Vt NMOS. Nominal-Vt High-Vt PMOS -0.139 V N/A NMOS 0.169 V 0.448 V TABLE IV SIMULATION RESULT FOR DRV, READ AND WRITE DELAY SRAM Cell DRV (mV) Read delay Write delay (ps) (ps) 6T 8T 9T 252.2 93.64 84.5 72.82 77.72 98.85 8.976 45.47 10

transistor. In this paper for the simulation CR=3 and PR=0.2 has been used on 90nm CMOS technology. In 8T and 9T SRAM cell read noise margin of the SRAM cell has been enhanced by isolating the read and write operation. The 8T SRAM cell is shown in Figure 1. The width of transistor used in 8T SRAM cell is shown in Table I In Ref. [6] during read operation gate of M7 was connected to node Qn and gate of M8 to node Q. In that case if Q=1 then BL was discharged and if Q=0 BLB was discharged. Because of this when the cell was storing logic 1; we were getting logic 0 at the output. To eliminate this problem in this paper the node Q is connected to M7 and node Qn to M8 as shown in Figure 3. The width of various transistor used in 9T SRAM cell is shown in Table II Due to the higher number of transistor used in 9T SRAM cell its leakage energy consumption increases. To reduce the leakage current in 9T SRAM dual threshold voltage technology [10] has been used. High threshold voltage transistors are not used for the access transistor as it increases the write delay. The threshold voltage for high-Vt and nominal-Vt NMOS is shown in TableIII

Figure 2. Symbols for nominal-Vt and high Vt transistor

Figure 3. 9T SRAM cell

TABLE V SIMULATION RESULT FOR CORNER ANALYSIS OF READ NOISE MARGIN Process 6T SRAM 8T SRAM 9T SRAM corner (V) (V) (V) FS 0.073 0.285 0.274 FF 0.084 0.314 0.299 TT 0.077 0.320 0.308 SS 0.087 0.325 0.314 SF 0.116 0.342 0.325

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2009 IEEE Symposium on Industrial Electronics and Applications (ISIEA 2009), October 4-6, 2009, Kuala Lumpur, Malaysia

1.2

1.0

FS SF SS TT FF

0.8

0.037

VQn (V)

0.6

0.4

0.2

0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2

VQ (V)

Figure 4. Corner simulation of RNM of 6TSRAM cell

Figure 7. Monte Carlo simulation of RNM of 6T SRAM cell

1.2

1.0

0.228
0.8

SS SF FS FF TT

VQn (V)

0.6

0.4

0.2

0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2

VQ (V)

Figure 8. Monte Carlo simulation of RNM of 8T SRAM cell

Figure 5. Corner simulation of RNM of 8T SRAM cell

1.2

1.0

0.217
0.8

FS SF SS TT FF

VQn(V)

0.6

0.4

0.2

Figure 9. Monte Carlo simulation of RNM of 9T SRAM cell

0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2

VQ(V)

Figure 6. Corner simulation of RNM of 9T SRAM cell

TABLE VI SIMULATION RESULT FOR STATISTICAL ANALYSIS OF SRAM CELLS SRAM cells 6T 8T 9T

RNM
(V) 0.065 V 0.305 V 0.301 V

RNM (mV)
18.85 18.82 20.92

( RNM 6 RNM )
(mV) Negative 192.1 175.48

C. Write noise margin The write noise margin for the SRAM cells have been simulated for write 1 and write 0 operation under process variation. Due to single bit line in 8T SRAM cell it possesses different write margin during write 1 and write 0. During write 1 operation in 8T SRAM cell the node Qn does not discharges fast due to the absence of bit bar line (BLB), this makes the 8T SRAM cell more prone to noise. Due to this the 8T SRAM cell possesses less noise margin during write 1 operation. The simulation of WNM under corner simulation is shown in Table VII. The simulation result for write noise margin with worst case WNM is shown in Figure 10, 11,12 and 13.

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2009 IEEE Symposium on Industrial Electronics and Applications (ISIEA 2009), October 4-6, 2009, Kuala Lumpur, Malaysia

Process corner FS FF TT SS SF

TABLE VII CORNER SIMULATION RESULT FOR WNM 6T SRAM cell 8T SRAM cell 9T SRAM cell Write Write Write Write Write Write 0 1 0 1 0 1 (V) (V) (V) (V) (V) (V) 0.505 0.456 0.399 0.334 0.779 0.774 0.479 0.442 0.445 0.268 0.757 0.762 0.494 0.445 0.454 0.248 0.745 0.739 0.497 0.448 0.465 0.226 0.728 0.725 0.454 0.422 0.506 0.165 0.708 0.711

Where m ox (= 0.32M 0 ) , is the effective electron mass in the oxide and

Tox is the gate oxide thickness.

D. Lekage energy The subthreshold leakage current is modeled as [11]:

The leakage energy of different SRAM cell is compared in Figure 14 and 15. Due to the asymmetric structure of the 8T SRAM cell the leakage energy is different when it is storing logic 1(Q=1) and when it is storing logic 0(Q=0). As the gate oxide thickness for high-Vt transistor was found to be 5.6nm in the technology file, therefore gate tunneling leakage need not to be considered for them because gate tunneling current is significant only for oxide thickness less than 3-4nm[13] E. Layout Layout for different SRAM cell is shown in Figure 16, 17 and 18. Due to larger width of pull down transistors in 6T SRAM cell, finger type layout has been used for it. The area and parasitic capacitance for different SRAM cell is tabulated in Table VIII Average write power The simulation results for power consumed during read and write operation is shown in Table IX. The power is higher for 8T and 9T SRAM cell due to higher parasitic capacitance.
TABLE VIII AREA AND PARASITIC CAPACITANCE FOR DIFFERENT SRAM CELL Parasitic SRAM cell Area capacitance ( mm 2 ) (pF) 6T 12.35 2.71 8T 11.40 2.73 9T 15.46 3.50 TABLE IX AVERAGE WRITE POWER IN DIFFERENT SRAM CELL SRAM cell Average write power ( W) 6T 8T 9T 0.32 1.88 2.02

I sub = Asub

q exp V GS Vt 0 'V SB + V DS n ' kT

(1)

q V DS 1 exp kT

F.

Where Asub = 0 C ox

W (kT / q )2 e1.8 Leff

(2)

C ox is the gate oxide capacitance per unit area, W and Leff denotes the width and effective length of the transistor, k is the Boltzmann constant, T is the absolute temperature, and q is the electron charge. Vto is the zero biased threshold voltage, ' is the linearized body-effect coefficient, is ' the drain-induced barrier lowering coefficient and n is
is zero bias mobility ,

the subthreshold swing coefficient. The gate tunneling leakage current has been modeled as [12]:

4m * q (kT )2 1 + kT 3 2 E h B q S q F EG / 2 exp exp E B kT J Tunnel =

)
(3)
VQn (V)

1.2

1.0

0.8

Where

m (= 0.19 M 0 ) is electron transfer mass,

M 0 is the electron rest mass, h is the Plancks constant, E B is the height of the barrier, S is the surface potential, E G is the silicon band gap energy. The parameter q F is the Fermi energy level either in Si
substrate for the gate tunneling current through the channel or in the source/drain region for gate tunneling current through the source/drain overlap and is defined as,

0.6

0.4

0.351
0.2

FF SS TT FF SF
0.4 0.6 0.8 1.0 1.2

0.0 0.0 0.2

VQ (V)

Figure 10. Corner simulation of WNM of 8T SRAM cell for write0

4Tox 2 m ox h

(4)

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2009 IEEE Symposium on Industrial Electronics and Applications (ISIEA 2009), October 4-6, 2009, Kuala Lumpur, Malaysia

1.2

1
Normalized Subthreshold leakage

1.0

0.8

SF FF FS SS TT
0.160

0.8 0.6 0.4 0.2 0

VQn(V)

0.6

0.4

0.2

0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2

VQ (V)

1. 6T SRAM 2. 9T SRAM 3. 8T SRAM (Q="1") 4. 8T SRAM (Q="0")

Figure 11. Corner simulation of WNM of 8T SRAM cell for write1

1.2

Figure 14. Subthreshold leakage in different SRAM cell

1 0.8 0.6 0.4 0.2 0 1 2 3 4

1.0

0.8

0.6

0.705
0.4

0.2

SF FS TT SS FF
0.0 0.2 0.4 0.6 0.8 1.0 1.2

0.0

VQ (V)

Noramalized gate tunneling leakage

VQn (V)

1. 6T SRAM 2. 9T SRAM 3. 8T SRAM (Q="1") 4. 8T SRAM (Q="0")

Figure 12. Corner simulation of WNM of 9T SRAM cell for write1

Figure 15. Tunneling gate leakage in different SRAM cell

Figure 13. Corner simulation result for 6T SRAM cell for write 0

Figure 16. Layout of 6T SRAM cell

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2009 IEEE Symposium on Industrial Electronics and Applications (ISIEA 2009), October 4-6, 2009, Kuala Lumpur, Malaysia

the cell is not symmetric and its write time is also higher. On the other hand 9T SRAM cell has higher RNM as well as WNM and its write time is also small. The leakage current of 9T SRAM cell is reduced by using dual threshold voltage technology. REFERENCES
[1] A. Asenov, A. R. Brown, J. H. Davies, S. Kaya, and Gabriela Slavcheva, Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs, IEEE Trans. Electronic devices, vol. 50, no. 9, September 2003, pp. 1837-1852. T. Mizuno, J. Okamura, and A. Toriumi, Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFETs, IEEE Trans. Electron Devices, vol. 41, Nov. 1994, pp. 22162221. G. F. Cardinale, C. C. Henderson, J. E. M. Goldsmith, P. J. S. Mangat, J. Cobb, and S. D. Hector, Demonstration of pattern transfer into sub-10 nm polysilicon line/space features patterned with extreme ultraviolet lithography, J. Vac. Sci. Technol., vol. B 17, 1999, pp. 29702974. H. S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S. Nakamura, M. Sato, and H. Ivai, 1.5 nm direct-tunnelling gate oxide Si MOSFETs, IEEE Trans. Electron Devices, vol. 43, Aug 1996, pp. 12331241. A. Sil, S. Ghosh and M. Bayoumi, A novel 8T SRAM cell with improved read-SNM, IEEE Northeast workshop on circuit and system, 2007, pp.1289-1292. Z. Liu and V. Kursun, Characterization of a novel nine-transistor SRAM cell, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 4, April 2008, pp. 488-492. T.-H. Kim, J. Liu, J. Keane and C. H. Kim, A 0.2 V, 480 kb subthreshold SRAM with 1 k cells per bitline for ultra-low-voltage computing, IEEE J. Solid State Circuits, vol. 43, no.2, February 2008, pp. 518-529. B. Calhoun and A. Chandrakasan, A 256-kb 65-nm subthreshold SRAM design for ultra-low-voltage operation, IEEE J. Solid State Circuits, vol. 42, no.3, March 2007, pp. 518-529. A. Pavlov and M. Sachdev, CMOS SRAM circuit design and parametric test in Nano scaled technologies, Springer Netherlands, 2008. J. T. Kao and A. Chandrakasan, Dual-Threshold Voltage Techniques for Low-Power Digital Circuits, IEEE J. Solid State Circuits, Vol . 35, no. 7, July 2000, pp.1009-1018 V. De, A.Keshavarzi, S. Narendra, and J. Kao, Techniques for leakage power reduction, in Design of High-Performance Microprocessor Circuits,A. Chrakasan, W. J. Bowhill, and F. Fox, Eds. Piscataway, NJ:IEEE, 2001. K. A. Bowman, L. Wang, X. Tang, and J. D. Meindl, A circuitlevel perspective of the optimum gate oxide thickness, IEEE Transaction on Electronic Devices, vol. 48, no.8, Aug. 2001, pp. 1800-1810 K. Roy, S.Mukhopadhyay and H. M-Meimand, Leakage current mechanisms and leakage reduction techniques in deep-sub micrometer CMOS circuits, IEEE Transaction on VLSI Systems, vol. 91, no. 2, Feb. 2003, pp.305-327

[2]

[3]

Figure 17. Layout of 8T SRAM cell [4]

[5]

[6]

[7]

[8]

[9]

[10]

Figure 18. Layout of 9T SRAM cell

[11]

IV.

CONCLUSION [12]

Different configurations of SRAM transistor have been compared. The 6T SRAM provide very less RNM which is further degraded due to process variation. To obtain higher RNM in 6T SRAM cell width of the pull down transistor has to be increased but this increases area of the SRAM which in turn increases the leakage currents. The 8T SRAM cell provide higher read noise margin and its area is also small but its WNM is very small. Hence it is more prone to failure during write operation. Besides this

[13]

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