12d

MICROSTRIP CIRCUITS
TERRY C. EDWARDS
Engalco
Bridlington, East Yorkshire
United Kingdom
1. THE BASIC MICROSTRIP STRUCTURE
The general geometry of microstrip is shown in Fig. 1.
Fundamentals and design equations for its manufacture
are discussed in the article, where the basic advantages
are also described in comparison with other types of MIC
and MMIC transmission lines. The most important di-
mensional parameters are the microstrip width w and the
height h (equal to the thickness of the substrate). Also of
main importance is the relative permittivity of the sub-
strate e
r
. In RFand microwave applications the thickness t
of the metallic, top conducting strip is generally of much
lesser importance and may quite often be neglected. How-
ever microstrip lines on chip and on MCMs are relatively
thick as a result of the need to keep resistance down while
still achieving a high wiring density by keeping the width
down. We shall consistently refer to the xyz coordinate
system as shown in Fig. 1.
Some of the particularly useful characteristics of
microstrip include the following:
1. DC as well as AC signals may be transmitted.
2. Active devices, diodes, and transistors may readily
be incorporated (shunt connections are also quite
easily made).
3. In-circuit characterization of devices is straightfor-
ward to implement.
4. Line wavelength is reduced considerably (typically
by one-third) from its free-space value, because of
the substrate elds. Hence distributed component
dimensions are relatively small.
5. The structure is quite rugged and can withstand
moderately high voltages and power levels.
Most of the material presented here has been developed
from Edwards and Steer [1].
2. QUASI-TEM MODE AND EFFECTIVE
MICROSTRIP PERMITTIVITY
It is clear from Fig. 1 that microstrip involves an abrupt
dielectric interface between the substrate and the air
above it. Any transmission line that is lled with a uni-
form dielectric can support a single, well-dened mode of
propagation, at least over a specied range of frequencies
(TEM for coaxial lines, TE for waveguides, etc.).
Transmission lines that do not have such a uniform di-
electric lling cannot support a single mode of propaga-
tion, and microstrip falls within this category. Although
this is true, the bulk of the energy is transmitted along
microstrip with a eld distribution that quite closely re-
sembles TEM; it is usually referred to as quasi-TEM.
The detailed eld distribution is quite complicated, but
the main transverse electric eld can be visualized as
shown in Fig. 2.
Gupta et al. [2] have used Maxwells equations to con-
vincingly demonstrate the necessity for longitudinal com-
ponents of electric and magnetic elds. This is clearly
inconsistent with a pure TEM or a TE propagating mode.
Representative views of the magnetic and electric eld
distributions are given in Fig. 3. (These are not precisely
determined eld contours, and they must be regarded only
as diagrammatic illustrations of the situation.) The longi-
tudinal components can be clearly seen, and these become
increasingly significant as the frequency is raised.
From either of these diagrams, note the abrupt change
in direction of the electric eld line as it passes through
the airsubstrate interface. These elds have been anal-
ysed by a number of workers using various static tech-
niques. We shall not study any of these techniques in
detail here, but the results are powerful and significant for
the circuit designer wishing to use microstrip. There are
two reasons for this:
1. For the majority of microstrip lines suitable for
MICs, the statically derived results are quite accu-
rate where the frequency is below a few gigahertz.
2. At higher frequencies, up to the limits for the useful
operation of microstrip, these static results can
still be used in conjunction with frequency-depen-
dent functions in closed formulas. This is developed
in some detail later.
The earliest work concerning microstrip is generally ac-
cepted as that reported by Grieg and Engelmann [3].
Many other workers investigated basic characteristics of
microstrip [4,5], but the major fundamental work on im-
portant and closely related parallel-strip transmission
air
=
o
Dielectric
substrate
=
o
r
Ground plane
(conducting)
Top conducting
strip
h
t
w
y
x
z
Figure 1. The general geometry of a microstrip line, including
choice of coordinates.
Figure 2. Transverse cross section of microstrip, showing electric
eld only.
MICROSTRIP CIRCUITS 2637
Previous Page
lines was due to Wheeler [6]. This led to analysis and syn-
thesis on the static TEM basis.
3. STATIC TEM PARAMETERS
The microstrip synthesis problem consists of nding the
values of width w and length l corresponding to the char-
acteristic impedance Z
0
, and electrical length y (in degrees
or radians) dened at the network design stage.
Initially a suitable substrate, of thickness h and
relative permittivity e
r
, will have to be chosen. A wide
range of substrates is available, suited to various types of
applications. Alumina is popular in many instances al-
though LTCC (low-temperature cored ceramic) tape is
becoming increasingly important. Microstrip circuits are
also designed on-chip (on-die) for MMICs and RFICs and
then it is the relative permittivity and thickness of the
semiconductor chip that form the starting data. A good
example in this respect is semiinsulating GaAs. The choice
of substrate, particularly passive substrates such as al-
umina, also depends on certain frequency limitations. The
synthesis actually yields the normalized width-to-height
ratio w/h initially, as well as an important quantity called
the effective microstrip permittivity e
eff
. This quantity is
unique to mixed-dielectric transmission-line systems and
provides a useful link between various wavelengths, im-
pedances, and propagating velocities. We shall shortly de-
ne the static TEM effective microstrip permittivity (e
eff
)
precisely.
3.1. The Characteristic Impedance Z
0
For any TEM-type transmission line the characteristic
impedance at high frequencies may be expressed in any
one of three alternate forms:
Z
0
L
C
_
1
Z
0
v
p
L 2
Z
0
1
v
p
C
3
Note that both (2) and also (3) involve the phase velocity v
p
of the wave traveling along the line. It is also recalled that
this phase velocity is given by
v
p
LC
p 4
When the substrate of the microstrip line is (effectively)
removed, we have an air-lled line along which the wave
will travel at c, the velocity of light in free space (c
2.99793 10
8
m/s). The characteristic impedance of this
air-lled microstrip Z
01
, is given by
Z
01
L
C
1
5
where L remains unaltered by the change in dielectric
constant and C
1
is the capacitance per unit length for this
structure. Alternatively
Z
01
cL 6
Z
01
1
cC
1
7
Combining Equations (1), (6) and (7) yields the following
very significant result:
Z
0
1
c
CC
1
p 8
This means that we have the required characteristic im-
pedance only if we can evaluate the capacitances per unit
(a)
(b)
Figure 3. Three-dimensional views of approximate magnetic
(a) and electric elds (partial view) (b) surrounding a shielded
microstrip line. For simplicity here, only the electric eld in the
air is shown in (b).
2638 MICROSTRIP CIRCUITS
length of the structure, with and without the presence of
the dielectric substrate. One way in which this has been
achieved will be outlined shortly.
3.2. The Effective Microstrip Permittivity e
eff
For the air-spaced microstrip line, the propagation veloc-
ity is given by
c
1
LC
1
p 9
and, dividing Eq. (9) by Eq. (4) and squaring, we obtain
C
C
1
c
v
p
_ _
2
10
The capacitance ratio CC
1
is termed the effective micro-
strip permittivity e
eff
, an important microstrip parameter.
From (10), e
eff
is given by
e
eff
c
v
p
_ _
2
11
Although this result has been derived on a static basis
here, it is fundamentally important for microstrip and will
be used again shortly, when v
p
is taken to be frequency-
dependent.
A useful relationship between Z
0
, Z
01
, and e
eff
can be
obtained by combining Eqs. (3), (7), (10), and (11). The
result is
Z
0
Z
01
e
eff
p 12
that is
Z
01
Z
0
e
eff
p
13
This expression is useful in several respects during mi-
crostrip circuit design procedures.
Upper and lower bounds can readily be found for e
eff
, in
the static low-frequency limit, by considering the effects of
very wide and very narrow lines as indicated in Fig. 4. For
the very wide lines nearly all of the electric eld is con-
ned to the substrate dielectric, the structure resembles a
parallel-plate capacitor, and therefore, at this extreme
e
eff
!e
r
14
In the case of very narrow lines the eld is almost
equally shared by the air (e
r
1) and the substrate so
that, at this extreme
e
eff
%
1
2
e
r
1 15
The range of e
eff
is therefore
1
2
e
r
1 e
eff
e
r
16
It may be convenient to express the effective microstrip
permittivity as follows
e
eff
1 qe
r
1 17
where the new quantity, the lling factor q, has the
bounds
1
2
q 1 18
Wheeler [6,7] has evaluated this lling factor in detail.
3.3. Synthesis: The Width-to-Height Ratio w/h
The width-to-height ratio (w/h) is a strong function of Z
0
and of the substrate permittivity e
r
. Wheelers results [7]
are particularly useful in this respect, although it has
been found that some modications are necessary for high
accuracy (within 1%) to be achieved [8]. Closed formulas
for w/h are available [1].
3.4. Microstrip Wavelength and Physical Length
For any propagating wave, the velocity is given by the ap-
propriate frequencywavelength product. In free space we
have c fl
0
and in microstrip the velocity is v
p
fl
g
. Sub-
stituting these products into (11), we obtain
e
eff
l
0
l
g
_ _
2
19
or
l
g
l
0
e
eff
p 20
where l
0
is the free-space wavelength and l
g
is the wave-
length of the dominant mode in the microstrip. More con-
veniently in practical design, where the frequency is given
in gigahertz and denoted by F, the wavelength can be ex-
pressed directly in millimetres as follows:
l
g
300
F

e
eff
p mm 21
The physical length l of a microstrip line to yield a spec-
ied electrical length y (in degrees) is easily determined.
We begin with the well-known expression for the electrical
length of a section of any transmission line of this physical
length, as a function of the phase coefcient (in radians),
bl y 22
w
(a) (b)
h
r
w
h
r
Figure 4. Microstrip lines: (a) extremely wide (wbh); (b) ex-
tremely narrow (w5h) lines.
and hence
2pl
l
g
y 23
With y in degrees this gives
l
yl
g
360
24
Thus, with l
g
evaluated using (21), we can simply
nd l.
An important aspect to mention at this juncture is that
all the way through we are specifically discussing open
microstrip, whereas in practice the circuits will be shield-
ed to some extent. Such shielding generally attracts more
electric eld into the airspace, above the substrate, and
therefore a greater proportion of this eld exists in air
with relative permittivity 1. The effective permittivity is
thereby decreased and the microstrip wavelength increas-
es with the square root relationship (see equations above).
So microstrip design lengths also increase. The closer the
shielding gets to the microstrip lines, the greater this
effect becomes.
4. DISPERSION AND ITS EFFECTS ON DESIGN
As we have seen in Section 3.2 above, because the electric
and magnetic elds are in more than one medium (a non-
homogeneous transmission line), as for the microstrip line
shown in Fig. 1, the effective microstrip permittivity e
eff
is
used. The characteristics of the nonhomogenous line are
then more or less the same as for the same structure with
a uniform dielectric of permittivity e
eff
.
Permittivity e
eff
changes with frequency as the propor-
tion of energy stored in the different regions changes. This
effect, called dispersion, causes a pulse to spread out as
the different frequency components of the pulse travel at
different speeds. Another way of looking at this situation
is to observe that the phase coefcient is a nonlinear func-
tion of the phase (propagation) velocity. As a direct conse-
quence, the microstrip wavelength l
g
is now a nonlinear
function of frequency. Therefore, we must account for the
dispersion effect if we are to design accurately at micro-
wave frequencies.
Because of its importance in microstrip circuit design,
over the years many researchers have analyzed and mea-
sured the basic microstrip structure and published dis-
persion results. Although intensive numerical analyses
have been employed in several instances, using substan-
tial computer power, currently much more convenient and
useful closed-formulas are available that predict disper-
sion. All aim at determining the effective microstrip per-
mittivitybut now as a nonlinear function of frequency
e
eff
f .
At DC there can be no dispersion, and all the static
TEM expressions already given can be directly used. The-
oretically, as the frequency approaches innity (well into
sub-millimeter-wave region and beyond), e
eff
f ap-
proaches e
r
. This situation can be summarized as follows:
1. e
eff
f always increases with frequency.
2. e
eff
f f !0 )e
eff
(calculated using static TEM
analysis)
3. e
eff
f f !1 )e
r
:
In addition to these three basic features, it is also noted
that e
eff
(f) is asymptotic at both limits, and the fourth fea-
ture concerns phase velocity v
p
(f). This suffers inection
at some frequency close to the cutoff frequency f
c
of the
TE
1
surface wave, Therefore this fourth feature is
@
2
v
p
=@f
2
0 when f f
c
.
Several earlier researchers utilized all or most of these
features to develop closed-form expressions for predicting
microstrip dispersion. However, more recent work has re-
sulted in more accurate formulas, notably from Kirschn-
ing and Jansen [9]. The approach adopted by these
workers begins with a function used by most investiga-
tors in this area, as follows
e
eff
f e
r
e
r
e
eff
1P f
25
and the form of the denominator frequency function is
Pf P
1
P
2
f0:1844P
3
P
4
10fhg
1:5763
26
where
P
1
0:27488
0:6315 0:525
10:157 fh
20
_ _
w
h
0:065683 exp
8:7513w
h
P
2
0:33622f1 exp0:03442e
r
g
P
3
0:0363 exp
4:6w
h
_ _
1 exp
fh
3:87
_ _
4:97
_ _ _ _
P
4
12:751 1 exp
e
r
15:916
_ _
8
_ _ _ _
_
_
27
These workers used computer-based matching in conjunc-
tion with the available hybrid-mode results (derived from
full electromagnetic numerical computations) to force the
correct asymptotic behavior of the function P(f). An accu-
racy of better than 0.6% is claimed for all frequencies up to
60 GHz (although a full check appears to have been con-
ducted up to only 30 GHz). The validity ranges are very
wide:
1 e
r
20
0:1
w
h
100
0
h
l
0
0:13
There are further formulations enabling the effects of dis-
persion in microstrip to be calculated at frequencies
through millimeter waves. Although the last word has al-
most certainly not yet been stated in the literature on this
subject, the position has been reached where reported ac-
curacies are within 1% (of measurements and indepen-
dent theoretical results over a wide range). Having said
this, it must be recognized that care is always required in
selecting an appropriate accurate dispersion expression.
5. OPERATING FREQUENCY LIMITATIONS
FOR MICROSTRIP
As the signal frequency applied to an MIC (or an MMIC) is
steadily increased, some characteristic frequency may be
reached at which undesirable effects occur. Two possible
spurious effects restrict the desirable operating frequen-
cies: (1) the lowest-order TM mode and (2) the lowest-or-
der transverse microstrip resonance. In practice, one of
these modes will be experienced at some frequency lower
than the other and will thus set the frequency limitation.
5.1. The TM-Mode Frequency Limitation
Vendelin [10] has indicated that the most significant mod-
al limitations in microstrip are associated with strong
coupling between the quasi-TEM mode and the lowest-or-
der TM mode. In the cited paper Vendelin gives the main
relationships quoted here (although the original analysis
is due to Collin in Ref. 6 of Vendelins paper).
We start with the substrate viewed as a dielectric slab,
having the coordinate notation shown in Fig. 5. This slab
is a fair approximation for the situation with narrow mi-
crostrip lines.
The analysis involves setting eigenvalues for air and
substrate and solving these either graphically or using the
computer. We will not pursue this analysis here, but the
nal result is given by Eq. (23) for the maximum safe
frequency under these conditions:
f
TEM1
c tan
1
e
r
2
p
ph

e
r
1
p 28
This is the frequency applying to strong coupling between
the basic microstrip quasi-TEM mode and the TM mode.
In the important case of relatively narrow microstrip
lines, where the relative permittivity is around 10 or
greater, Eq. (28) tends toward
f
TEM1
106
h

e
r
1
p 29
Using this equation, with thickness h directly substituted
in millimeters, the frequency comes out directly in giga-
hertz.
The maximum restriction on usable substrate thick-
ness is then easily obtained as
h
0:354l
0
e
r
1
p 30
Care should be exercised in the use of these expressions,
as Eq. (28) is more general and applicable to all types of
substrates. Operating frequencies should be kept well be-
low this maximum frequency. It is also recommended that
substrates should be as thin as possible because Eq. (28)
show that this makes the TM mode onset high. However, it
should also be noted that thinner substrates result in
lower Q factors, notably at lower frequencies.
5.2. The Lowest-Order Transverse Resonance in Microstrip
For a sufciently wide microstrip line, a transverse reso-
nant mode can exist that can also couple strongly to the
quasi-TEM microstrip mode. At the cutoff frequency for
this transverse resonant mode, the equivalent circuit is a
resonant transmission line of length (w2d), where d ac-
counts for the microstrip side-fringing capacitance: d
0.2 h. In this situation a half-wavelength must be sup-
ported by the length (w2d), stretching across the width
of the microstrip. Setting down the simple equation for
this transverse resonance and converting to the resonant
frequency, we obtain
f
CT
e
r
p
2w0:8h
31
This is the maximum operating frequency under this lim-
itation and it applies especially to relatively wide micro-
strips.
Vendelin [10] has indicated that slots, introduced into
the metal strip, can suppress the transverse resonant
mode. However, this may not always be practicable (e.g.,
when short stubs are involved), and it should be checked
by calculating from Eq. (31), whether the transverse res-
onance might be excited. Sometimes a change in the cir-
cuit conguration will enable the offending wide lines to
be avoided altogether.
In practice it is essential to check whether either the
Eq. (28) or Eq. (31) frequency limitation will apply to every
section of microstrip in a rst-cut circuit design. The de-
sign must then be altered accordingly such that the oper-
ating frequencies remain below the set conditions as
dened above.
air
c
1
h
x
y
z
Figure 5. An (isotropic) substrate viewed as a dielectric slab,
showing the nomenclature.
5.3. Power Losses and Related Effects
Four separate mechanisms can be identied for power
losses and parasitic effects associated with microstrip
lines:
1. Conductor losses
2. Dissipation in the dielectric of the substrate
3. Radiation losses
4. Surface-wave propagation
The rst two items are dissipative effects, whereas radia-
tion loss and surface-wave propagation are essentially
parasitic phenomena.
5.3.1. Conductor Losses. These losses occur as a result
of the current conduction effects in the metal of the mi-
crostrip line and depend on several parameters associated
with the microstrip and are probably best embodied in the
expressions originally due to Hammerstad and Bekkadal
[11]. The basic expression given by these workers is
a
c
0:072
f
_
wZ
0
l
g
dB=microstrip wavelength 32
where the frequency f is in gigahertz and Z
0
is in ohms.
In practice, Eq. (32) yields somewhat low results, and
surface roughness must be considered. Hammerstad and
Bekkadal [11] gave the following curve-tted formula to
accommodate this problem:
a
0
c
a
c
1
2
p
tan
1
1:4
D
d
s
_ _
2
_ _ _ _
33
where
D RMS surface roughness
d
s
1/(R
s
s), the skin depth at the appropriate operating
frequency, in which
R
s
surface resistance
s the conductivity of the metal
In order to observe the typical magnitudes involved, con-
sider a copper microstrip, where the skin depth at a few
gigahertz is 1mm. Also, assume the RMS surface rough-
ness to be of similar magnitude, namely, 1 mm (this is fairly
typical of rutile and some other hard substrates).
Equation (33) then shows that the attenuation coef-
cient becomes
a
0
c
% 1:6a
c
34
That is to say, the loss is approximately 60% increased
when surface roughness is taken into account. The in-
crease will be still greater for alumina and other sub-
strates where the roughness can exceed 10 mm.
5.3.2. Dielectric Loss. This type of loss has also been
analyzed by several groups of workers, including again
Hammerstad and Bekkadal [11] and also Gupta et al. [12],
who derived the following expression for the dielectric at-
tenuation coefcient, a
d
, per unit length
a
d
27:3
e
r
e
eff
1 tan d
e
eff
p
e
r
1l
0
dB=unit length 35
where tan d is the loss tangent for the substrate material
and the microstrip wavelength l
g
given by
l
g
l
0
e
eff
p 36
Equation (35) can also be written
a
d
27:3
e
r
e
eff
1 tan d
e
eff
e
r
1
dB=microstrip wavelength
37
which is the expression given by Hammerstad and
Bakkadal [11].
For microstrip lines on alumina, e
eff
!e
r
, at least very
approximately, and the attenuation coefcient is, roughly,
a
d
27 tand. In most cases tan dB10
3
(or less) and
therefore a
d
B0.027 dB/microstrip wavelength. This is a
factor of Z5 smaller than the conductor loss that was cal-
culated earlier. Conductor losses greatly exceed dielectric
losses for most microstrip lines on alumina or sapphire
substrates. However, where plastic substrates are used,
this will by no means always be the case, and (especially)
silicon or gallium arsenide substrates result in much
larger dielectric losses (B0.04dB/mm; i.e., 0.4dB/micro-
strip wavelength at 10 GHz for silicon).
5.3.3. Loss Due to Radiation. This type of loss also rep-
resents a significant microstrip effectagain increasing
as frequency rises. Microstrip is an asymmetric transmis-
sion line structure and is often used in unshielded or poor-
ly shielded circuits where any radiation is either free to
propagate away or to induce currents in the shielding.
Further power loss is the net result.
In particular, discontinuities such as abruptly open-cir-
cuit microstrip (i.e., open ends), steps, and bends will all
radiate to a certain extent. Such discontinuities form es-
sential features of a microwave integrated circuit and ra-
diation cannot therefore be avoided altogether. Efforts
must be made to reduce such radiation and its undesir-
able effects. In circuits such as lters and ampliers, this
radiation is an acknowledged nuisance.
Both radiation and surface-wave propagation may be
represented as a shunt admittance at the end of an open-
circuit microstrip stub or at the plane location associated
with some other abrupt discontinuity. This equivalent
admittance is given by the following expression:
Y G
r
G
s
jB 38
James and Henderson [13] show that, at frequencies
where the surface wave is highly trapped in the substrate
and with thin substrates and narrow lines relative to the
free-space wavelength, the radiation conductance G
r
is ap-
proximated by
G
r
Z
0
%
4phw
eff
3l
2
0
e
eff
p
39
in which w
eff
is an effective microstrip width dened by the
following expression:
w
eff
376:7h
Z
0
e
eff
p 40
The remaining terms in Eq. (38), G
s
and B, represent con-
ductance due to surface-wave propagation and suscep-
tance arising from the many eld inuences around the
discontinuity.
Various techniques may be adopted to reduce radiation:
1. Metallic shielding or screening
2. Introduction of a small specimen of lossy (i.e., ab-
sorbent) material near any radiative discontinuity
3. Utilization of compact, planar inherently enclosed
circuits (e.g., spurline lters or hairpin resonators)
4. Reduction of the current densities owing in the
outer edges of any metal sections so as to concen-
trate currents toward the center of the microstrip
5. Possibly shaping of the discontinuity in some way to
reduce the radiative efciency
5.3.4. Surface-Wave-Induced Loss. Surface waves also
emanate from microstrip, and their undesirable effects
have to be accounted for. Surface-wave propagation may
be reduced by technique 2 listed above or by cutting slots
into the substrate surface just in front of an open circuit.
However, this is an expensive process and is usually un-
realizable in MMICs. Parasitic coupling, where adjacent
circuitry couples energy from nearby sources, is an unde-
sirable consequence of surface-wave propagation. It is of-
ten necessary to minimize parasitic coupling (i.e., increase
the isolation), and this requires attention to the following
attributes:
1. Use relatively high permittivity substrates. Then e
eff
is relatively large (e.g., alumina is better than plas-
tic, which should be anticipated on physical
grounds).
2. Use fairly thin substrates (make the free-space
wavelength/thickness ratio as large as possible).
3. Employ high-impedance (Z
0
) stubs, for example,
wherever this is feasible.
6. DISCONTINUITIES IN MICROSTRIP
All microstrip circuits must be designed with discontinu-
ities fully accounted for. Several forms of discontinuity
emerge from circuit requirements:
1. Foreshortened open circuits
2. Series coupling gaps
3. Short circuits through to the ground plane
4. Right-angled corners or bends (unmitered and mi-
tered)
5. Step width changes
6. Transverse slit
7. T junction
8. Cross-junctions
An example of a microwave transistor amplier layout is
shown in Fig. 6, and at least three of the discontinuities
can be readily identied. Some of these are numbered on
the diagram, in accordance with the list above. Many oth-
er circuits, such as lters, mixers, and oscillators, involve
several discontinuities. All technologies, whether hybrid
MIC or MMIC, inherently involve such transmission dis-
continuities.
The various discontinuities are accommodated in the
design process by approaches including extra line exten-
sions and shifting the reference planes. In all cases the
effects are strictly frequency-dependent, but in practice
this results in only third-order adjustments at the most, so
quasi-TEM (often DC) calculations are usually sufcient
to quite accurately account for the effects of discontinu-
ities. We will restrict the presentation here mainly to
three types of discontinuity: the foreshortened open cir-
cuit, the right-angled bend, and the T junction.
With the foreshortened open circuit, the most common
method of accommodating this is by supposing the line to
be effectively longer than it is physically. We term this the
equivalent end-effect length, and an empirical expression
has been developed by Hammerstad and Bekkadal [11].
l
eo
0:412h
e
eff
0:3
e
eff
0:258
_ _
w=h0:262
w=h0:813
_ _
41
It appears that, over a wide range of materials and mi-
crostrip width-to-height ratios, this expression can often
give errors of Z5%. In practice, however, this level of error
Input matching circuit
Output matching circuit
GoAs FET on
"Chip on disc"
MIC mount
(5)
(5)
(4)
(1)
25ml Alumina
substrate
10.605 mm
Figure 6. Layout of a simple, single-ended, hybrid MIC micro-
wave amplier using a GaAsFET device and showing several dis-
continuities in the microstrip lines (DC bias lters are not shown
here).
almost always results in an acceptably small error in the
overall microstrip-line design. For example, consider a mi-
crostrip line physically 3 mm in length and assume that
the end-effect length extension calculates to 0.14mm us-
ing Eq. (41). If this 0.14mm is actually 6% high in error,
then the corrected end-effect length will be just over
0.13mm, giving a total effective length of 3.13mm instead
of 3.14mm. The overall error is therefore about 0.3% and
this is well within most acceptable design limits.
Series gaps represent a variation on the foreshortened
open circuit, and the effective length extensions may be
deduced by modifying Eq. (41). In general, because of the
increased electric elds across such gaps compared to the
foreshortened open circuit, the end-effect equivalent
length extensions are somewhat greater. Series gaps are
sometimes used in compact bandpass lters.
The right-angled bend (corner) is the second major
form of microstrip discontinuity that we are considering
here. Because the outer tip of the simple right-angled bend
presents such a known and severe discontinuity (radiation
and reection), we shall restrict our attention to the mi-
tered right-angled bend. Several techniques have been in-
vestigated for the compensation of microstrip bends,
greatly reducing the effect of the capacitance and hence
improving the VSWR and reducing the radiation. In par-
ticular, Anders and Arndt [14] have reported a moment
method to calculate the appropriate capacitances and in-
ductances for both curved and mitered bends.
Their results indicate that, at least up to a frequency of
B10 GHz, a mitered bend produces a performance as good
as, or better than, that of curved bends. This applies to a
wide range of bend angles, from 301 up to 1201. At least
70% mitering is recommended for an acute-angled bend of
1201, that is, one that acutely bends back on itself. Guid-
ance for the design of such mitered bends, but for an angle
of 901, is also available for the structure shown in Fig. 7.
The equivalent circuit shown in Fig. 7b is for the region
between planes P and P
0
, and the curves of Fig. 7c relate to
measured results [15]. Although these curves apply to the
specific instance dened, the considerable reduction of
susceptance B (and therefore also capacitance C) would
be expected in widely different substrates and structures.
As can be seen, the equivalent linelength parameter l
c
in-
creases with enhanced mitering. Because of this and the
substantial line narrowing in the center of the bend, the
degree of miter is generally restricted to around the value
calculated from the following expression:
1
b
2
p
w
% 0:6 42
With this restriction the extent of chamfer or miter pa-
rameter b becomes b % 0:57w, which means, for example,
that the miter on a line that is 0.5mm wide should opti-
mally amount to bB0.28 mm. It is instructive to observe
that, whether unmitered or mitered, the effect of the dis-
continuity is that of a lowpass lter.
T junctions in microstrip are important is many cir-
cuits, notably amplier-matching networks and stub-
based lters. The basic, uncompensated, T junction and
its equivalent circuit are shown in Fig. 8.
The immediate discontinuity effects, in the vicinity of
the junction itself, are somewhat similar to those associ-
ated with the right-angled bend, represented as series in-
ductance and shunt capacitance in the equivalent circuit.
Note that the branchline of width w
2
(feeding out to what
is termed a secondary load in Fig. 8a) is represented as a
line coupled via an equivalent transformer of transforma-
tion ratio n in Fig. 8b.
Although rarely implemented (somewhat surprisingly),
compensated T junctions are of considerable potential in-
terest. One simple way to at least compensate the capac-
itance of a T junction is to introduce a slit across the width
of the main through microstrip line, opposite the branch
arm. Kompa [17] has shown further that a comparatively
wide slot (bBw
2
) in this position, specifically, a wide slit,
strongly affects the transmission of higher-order modes in
the mainline and leads to enhanced skirt sensitivity of l-
ters composed of stubs with such modied T junctions. To
the best of the present writers knowledge, this kind of
approach has not yet been developed further, and more
investigation could prove very fruitful.
Dydyk [18] has described a T-junction compensation
technique that appears to work well in the case of a branch
line microstrip coupler circuit. Dydyks aim was to modify
the microstrip lines in the vicinity of the junction in order
to compensate for reference plane shifts, at least over a
specied range of frequencies. The analysis of such a junc-
tion can exclude any discussion of radiation loss with little
error in circuit performance results, up to a frequency of
lc
2
B
y
o
B
y
o
lc
h
b
2w
lc
jB
z
o
p
w
b
p
p
p
z
o
2
lc
2
and
0.3
0.2
0.1
0
0 0.2 0.4 0.6 0.8
Camfer fraction (1 )
(c)
(a) (b)
w
Figure 7. Mitered, right-angled bend together with its equiva-
lent circuit and parameter variations (as a function of the amount
of miter): (a) structure and nomenclature; (b) equivalent circuit;
(c) parameter trends. (Reproduced by permission of the Institu-
tion of Electronic and Radio Engineers from Easter et al. [15]).
17 GHz at least. The compensated T junction takes on the
form shown in Fig. 9.
A microstrip branch line coupler designed using these
principles yielded the following performance over the fre-
quency band 1618GHz:
Insertion loss: 3.54.0 dB over the entire band
Isolation: 420 dB over the entire band
Return loss: 10 dB (at 17.5GHz), otherwise 10 to
25 dB
The very at, almost frequency-independent, insertion
loss and isolation are attributed to the compensated junc-
tion design. Dydyk also describes an SPDT switch de-
signed according to these principles.
7. PARALLEL-COUPLED MICROSTRIPS AND
BANDPASS FILTERS
The arrangement shown in Fig. 10 illustrates the trans-
verse cross-section basic structure under consideration
here.
It will be assumed that both microstrip lines have the
same widths, which is nearly always the case in practical
applications. Some work has also been carried out on mul-
tiple arrays of such parallel, edge-coupled lines, but we
can usefully restrict the considerations to just two lines in
this treatment. There are two general areas of application
for these structures:
1. Directional couplersfor use in a variety of circuits
including balanced mixers, balanced ampliers,
phase shifters, attenuators, modulators, discrimina-
tors, and measurement bridges
2. Filters, delay lines, and matching networksoften
using arrays of parallel-coupled microstrips as res-
onant elements
In the rst instance (1), a prescribed amount of the inci-
dent power is required to be coupled out of the system.
Thus, for example, a 3-dB coupler is one in which half
of the power input is coupled from one microstrip line into
another and then on to separate circuitry. In practice,
however, this simple structure is inadequate for such ap-
plications and special couplers are realized. This topic is
outside the scope of the present discussion. Microstrip l-
ters application (2) employing the parallel-coupled struc-
ture are usually of the bandpass or bandstop type. An
outline example of a design approach employing resona-
tors coupled in this manner is given later here.
For each half-cycle of the RF wave, the two coupled
lines will have precisely opposite voltage polarities. In one
half-cycle the opposing lines will be similarly polarized
(e.g., equally positive), while in another half-cycle the
lines will be oppositely polarized (i.e., one positive and
one negative). In the rst instance we term the situation
even-mode; in the second instance, odd-mode. Each pa-
rameter associated with each polarisation has an extra
(a) (b)
From
generator
To "main"
load
Secondary load
Ideal
transformer
P
1
P
1
W
1
W
1
W
2 P
2
P
2
P
2
P
1
L
1
L
L
1
C
1
n
Figure 8. The T junction in microstrip: (a)
structure and nomenclature; (b) equivalent
circuit. (Copy right 1973 IEEE. Reprinted,
with permission, from Silvester and Benedek
[16]).
w
1
w
1 z
1
z
1
z
2
z
v
z
2
z
v
w
2
Figure 9. A compensated form of T junction. (Reproduced by
permission of MicroWaves from Dydyk [18]).
Mircrostrip lines
Ground plane
Substrate
Figure 10. A pair of parallel, edge-coupled microstrip lines.
subscript attributed; e for even-mode and o for odd-
mode.
The even- and odd-mode characteristic impedances
(Z
0,e
and Z
0,o
) are major design parameters for any paral-
lel-coupled transmission-line congurationwhatever its
application. These impedances are obtained at an early
circuit/system design stage and are functions of the degree
of coupling (C) and the single-line terminating character-
istic impedance (Z
0
). The relationships between Z
0,e
and
Z
0,o
and the physical dimensions of the coupled structure
(including the substrate permittivity) are therefore of
prime significance to the designer. As with single micro-
strip lines, in this coupled situation as well we can deter-
mine Z
0,e
and Z
0,o
from known physical dimensions, which
amounts to analysis. Alternatively, with greater difculty,
we may synthesize the physical structure from starting
values of the impedances. Both of these procedures are
useful in practice.
The electric (E) and magnetic (H) elds associated with
each mode are indicated in Figs. 11.
In the design of lters or matching networks using par-
allel-coupled lines, we usually begin with either insertion
loss as a function of frequency or VSWR requirements over
some band. In either event we still arrive at desired values
of Z
0,e
and Z
0,o
followed by a nal synthesis aimed at the
physical realization of the circuit. Input information
required includes
*
Bandwidth (B) and center frequency (f
0
)
*
In-band and attenuation-band insertion loss (both
dBfor lters)
*
Terminating characteristic impedance Z
0
(usually
50 O)
*
Permittivity and thickness of the substrate
From this information the designer must ultimately de-
termine the widths of the microstrip lines, the separation
between them, the length of the coupled region, and hence
ultimately the physical lengths of the microstrips.
For the present purposes we will not expound on the
precise details of parallel-coupled microstrip design (this
is covered in detail in Ref. 1). It should, however, be men-
tioned that dispersion is present in this structure, and this
affects the even and odd modes differently. The single mi-
crostrip models covered in Section 1 can be modied to suit
the parallel-coupled case.
With microstrip couplers, maximum coupling is ob-
tained between physically parallel microstrips when the
length of the coupled region is l
g
=4, or some odd multiple
thereof. To achieve resonance, each resonator element has
to be l
g
=2 in length, or any multiple thereof. Therefore the
microstrip circuit must have the general layout shown in
Fig. 12 where l
1
; . . . ; l
4
% l
g
=4.
We will assume, for the moment, that this fairly
straightforward cascade of parallel-coupled (or edge-cou-
pled) microstrip resonators can be designed on a basis of
all-parallel resonator networks together with intervening
circuits known as inverters.
F - field
H - field
+ + +
(a) (b)
Figure 11. Field distributions resulting from (a) even-mode and
(b) odd-mode excitation of parallel-coupled microstrip lines.
Input microstrip Output microstrip feed
feed
Figure 13. General top-view appearance of a practical parallel-
coupled microstrip BPF.
w
s
l
1
l
2
l
3
l
4
l
3
l
2
l
1
w
1
w
1
w
2
w
2
w
3
w
3
w
4
w
4
w
3
w
3
w
2
w
2
w
1
w
1
w
s
S
1
S
2
S
3
S
4
S
3
S
2
S
1
Figure 12. General microstrip conguration
for a seven-section, parallel-coupled bandpass
lter (BPF).
The four main design steps are outlined as follows:
1. Determine the one-type resonator network, to real-
ize the specication, from the original prototype;
2. From the network parameters, evaluate the even-
and odd-ordered characteristic impedances Z
0,e
and
Z
0,o
applicable to the parallel-coupled microstrip
(this is not discussed in detail here, but see ref. 1).
3. Relate the values of Z
0,e
and Z
0,o
to microstrip widths
and separations (w,s) (detailed microstrip design).
4. Calculate the entire resonator length 2 l
0
, slightly
less than l
g
=2 because of the semiopen end effects
(see Section 6), and therefore of the coupled section
length l
0
, which is slightly less than l
g
=4 for the end
effect reason again (Fig. 12).
Here l
g
is the midband and average microstrip wave-
length. Allowance must be made for the semi-open-circuit
microstrip end effects that exist for all elements in this
circuit.
In practice, most microstrip or related planar BPFs
have their topologies rotated for spatial convenience (on
chip or substrate) as shown in Fig. 13.
All the dense black features are microstrip lines, and
Fig. 13 is not to scale since it is only meant to provide the
concept of the layout.
BIBLIOGRAPHY
1. T. C. Edwards and M. B. Steer, Foundations of Interconnect
and Microstrip Design, Wiley, Chichester, UK, 2000.
2. K. C. Gupta, R. Garg, and I. J. Bahl, Microstrip Lines and
Slotlines, 2nd ed., Artech House, Dedham, MA, 1996.
3. D. D. Grieg and H. F. Engelmann, Microstripa new trans-
mission technique for the kilomegacycle range, Proc. Inst.
Radio Eng. 40(12):16441650 (Dec. 1952).
4. W. E. Fromm and E. G. Fubini, Characteristics and some ap-
plications of stripline components, Proc. Natl. Electronics
Conf., 10, III., Oct. 46, 1954, 5859.
5. J. M. C. Dukes, The application of printed circuit techniques
to the design of microwave components, Proc. Inst. Electric.
Eng. 105(Part B):155172 (March 1958).
6. H. A. Wheeler, Transmission-line properties of parallel wide
strips by a conformal mapping approximation, IEEE Trans.
Microwave Theory Tech. 12:280289 (May 1964).
7. H. A. Wheeler, Transmission-line properties of parallel strips
separated by a dielectric sheet, IEEE Trans. Microwave The-
ory Tech. 13:172185 (March 1965).
8. R. P. Owens, Accurate analytical determination of quasi-static
microstrip line parameters, Radio Electron. Eng. 46(7):360
364 (July 1976).
9. M. Kirschning and R. H. Jansen, Accurate model for effective
dielectric constant of microstrip with validity up to millime-
tre-wave frequencies, Electron. Lett. 272273 (March 18,
1982).
10. G. D. Vendelin, Limitations on stripline Q, Microwave J.
6369 (May 1970).
11. E. O. Hammerstad and F. Bekkadal, A Microstrip Handbook,
ELAB Report, STF 44 A74169, Univ. Trondheim, Norway,
1975, pp. 98110.
12. K. C. Gupta, R. Garg, I. J. Bahl, and P. Bhartia, Microstrip
Lines and Slotlines, 2nd ed., Artech House, Norwood, MA,
1996, pp. 9192.
13. J. R. James and A. Henderson, High-frequency behaviour of
microstrip open-circuit terminations, IEE J. Microwaves Opt.
Acoust. 3(5):205218 (Sept. 1979).
14. P. Anders and F. Arndt, Moment method of designing
matched microstrip bends, Proc. 9th European Microwave
Conf., 1979, 430434.
15. B. Easter et al., Theoretical and experimental methods for
evaluating discontinuities in microstrip, Radio Electron. Eng.
48(1/2):7384 (Jan./Feb. 1978).
16. P. Silvester and P. Benedek, Microstrip discontinuity capac-
itances for right-angle bends, T-junction and crossings, IEEE
Trans. Microwave Theory Tech. 21(5):341346 (May 1973).
17. G. Kompa, Reduced coupling aperture of microstrip stubs
provides new aspects in stub lter design, Proc. 6th European
Microwave Conf., 1976, 3943.
18. M. Dydyk, Master the T-junction and sharpen your MIC
designs, Microwaves, 184186 (May 1977).
MICROSTRIP LINES
ZHEWANG MA
EIKICHI YAMASHITA
KAZUHIKO ATSUKI
University of Electro-
Communications
1. TRANSVERSE ELECTROMAGNETIC
TRANSMISSION LINES
One of the most familiar waveguiding structures is the
conventional transmission line such as the two-wire line
and the coaxial line. The fundamental mode of propaga-
tion on a transmission line is essentially a transverse elec-
tromagnetic (TEM) wave, which owns neither electric nor
magnetic eld in the direction of propagation [1].
An ideal lossless uniform TEM transmission line can be
represented by a lumped circuit and consists of series in-
ductance L and shunt capacitance C, all dened per unit
length of the line, as shown in Fig. 1. The inductance L is
proportional to the permeability m of the surrounding me-
dium, and the capacitance C proportional to the permit-
tivity e of the medium. Their values depend on the
transverse geometry of the transmission line, and are de-
termined from the electrostatic analysis [1] of the cross-
section of the structure that solves a two-dimensional La-
place equation in the medium surrounding the conductors
of the transmission line.
The voltage and current waves, expressed by V
V
0
e
7jbz
and I I
0
e
7jbz
, along the transmission line are
solutions of the telegraphists or transmission-line equa-
tions [1]
d
2
V
dz
2
o
2
LCV 0 1
d
2
I
dz
2
o
2
LCI 0 2
MICROSTRIP LINES 2647
where o2pf (frequency) is the radian frequency and b is
the phase constant.
TEM transmission lines are characterized by line pa-
rameters such as phase constant, characteristic imped-
ance, and attenuation constant. Formulas for line
parameters of an ideal lossless transmission line are
given in what follows [1,2]:
Phase constant
bo
LC
p
o

me
p
o=v 3
Characteristic impedance
Z
0
L
C
_

1
vC
4
Voltage and current along line
Vz V
0
e
jbz
1 Gz 5
Iz
V
0
Z
0
e
jbz
1 Gz 6
Input impedance
Zz Z
0
Z
L
cos bz jZ
0
sin bz
Z
0
cos bz jZ
L
sin bz
7
In these expressions, v is the velocity of TEM waves in the
dielectric of line, v
0
is the amplitude of the incident volt-
age, z
L
is the value of the load impedance, and z is the
distance along the line from the load end.
2. STRIPLINES
A stripline, also referred to as a triplate line, consists of a
conducting strip lying between, and parallel to, two wide
conducting ground planes, as shown in Fig. 2. The region
between the strip and the planes is lled with a uniform
dielectric. Stripline is one of the most commonly used
transmission lines for passive microwave integrated cir-
cuits (MICs). The fundamental mode in a stripline is
a TEM mode, and its eld distribution is illustrated in
Fig. 3.
The line parameters of a stripline can be obtained com-
pletely by electrostatic analysis such as the conformal
mapping technique [1,3]. An approximate expression for
the characteristic impedance of a stripline with zero-thick-
ness strip is given by [2,3]
Z
0
30p
e
r
p
K
0
k
Kk
8
where e
r
is the relative permittivity of the dielectric lled
in the stripline, ktanh(pw/2 h), K represents a complete
elliptic function of the rst kind, and K
0
is its complemen-
tary function. The velocity of the TEM mode in a stripline
is v 1=

m
0
e
0
e
r
p
. Both the wave velocity and characteristic
impedance are independent of frequency.
An accurate but simple approximate expression for
K(k)/K
0
(k) is given by
Kk
K
0
k

p
ln21
k
p
=1
k
p

for 0 k 0:707
1
p
ln21
k
p
=1
k
p
for 0:707 k 1
_
_
9
An approximate expression for the attenuation constant
arising from the conductor surface resistance,
R
s
om
0
=2s
_
, is given by (1)
a
c
R
s
hZ
pw=h ln4h=pt
ln 2 pw=2h
_ _
Nps=m 10
where Z
m
0
=e
0
e
r
_
Z
0
=

e
r
;
p
Z
0
120p is the wave imped-
ance in free space and t is the thickness of the strip. Equa-
tion (10) is valid for w42h and toh/10.
The attenuation constant from lossy dielectric medium
with e e
0
je
00
is expressed by
a
d
Rejo

m
0
e
p
Rejo
m
0
e
0
je
00
_

%
o

m
0
e
0
p
2
e
00
e
0

o

m
0
e
0
p
2
tand Nps=m
11
where tand is the dielectric loss tangent.
t
h
w
r
Ground conductor
Ground conductor
Strip conductor
Figure 2. Geometry of a stripline. The strip conductor is sand-

wiched between two wide parallel conducting ground planes. The
region between the strip and the ground planes is lled with a
uniform dielectric.
V(z + dz, t )
I(z + dz, t ) dz
Ldz
Cdz
I(z, t )
V(z, t )
Figure 1. Lumped-circuit representation of an
ideal TEM transmission line. L is the series in-
ductance, C the shunt capacitance; both are de-
ned per unit length of the line.
2648 MICROSTRIP LINES
In addition to the dominant TEM mode, higher-order
transverse electric (TE) modes and transverse magnetic
(TM) modes can also propagate in a stripline. A TE mode
owns magnetic eld but no electric eld in the direction of
propagation. A TM mode contains electric eld but no
magnetic eld in the direction of propagation. The cutoff
frequency of the lowest order TE mode is [2]
f
c
15
h

e
r
p
1
w=hp=4
12
where f
c
is given in gigahertz and w and h are in centi-
meters.
More detailed and accurate formulas for the stripline
parameters, such as the characteristic impedance, and the
attenuation constant, can be found in Ref. 2.
3. MICROSTRIP LINES
3.1. General Descriptions
3.1.1. Microstrip Geometry and Advantages. A micro-
strip line [4] is a type of open planar transmission line
that consists of a dielectric substrate medium with a
ground plane on the lower side and a conducting strip
on the upper side. The geometry of a microstrip line is
shown in Fig. 4. The substrate provides mechanical rigid-
ity and permits the accurate positioning of the circuitry.
The transmission-line characteristic parameters, like the
phase constant and characteristic impedance, can be de-
termined from the substrate permittivity (e
r
) and the geo-
metrical dimensions (strip width w and thickness t,
substrate thickness h) in the transverse plane. For this
reason, various types of microstrip circuits can be fabri-
cated conveniently with high precisions by employing the
simple photolithographic and photoetching techniques.
Use of these techniques at microwave and millimeter-
wave frequencies has led to the development of hybrid
and monolithic microwave integrated circuits (MICs)
[511].
Microstrip line is now one of the most widely used
transmission lines for MICs. Active devices (diodes and
transistors), lumped circuit elements (capacitors, resis-
tors, inductors), dielectric resonators, and antennas can be
easily incorporated into the circuit. Compared with
the traditional bulky and heavy metallic waveguides and
coaxial lines, the planar microstrip structures are
small-size, lightweight, easy for mass production, and
inexpensive.
3.1.2. Dielectric Substrate. The properties of the dielec-
tric substrate material affect the overall performance of
the microstrip structures. Different substrate materials
possess characteristics that may make them better suited
for a given application. For instance, higher-dielectric-con-
stant materials are preferred in order to achieve a very
compact microwave circuit, while lower-dielectric-con-
stant materials are required for antenna structures to
ensure efcient radiation.
In general, the substrate material parameters, permit-
tivity e and permeability m, should be homogeneous (inde-
pendent of position), isotropic (independent of wave
propagation direction), and should have low dispersion.
The loss tangent should be small to reduce energy dissi-
pation. Furthermore, these parameters should have very
small variation with temperature to ensure circuit stabil-
ity. The substrate thermal conductivity should be high
enough to ensure efcient removal of heat from power
transistors, attenuators, and loads in high-power applica-
tions. In high-power applications, a high breakdown volt-
age is also desirable. The thermal expansion coefcient of
the material should be similar to that of the deposited
conductors and housing to withstand temperature uctu-
ations and improve reliability. The material must allow
drilling, cutting, machining, and etching for easy work-
ability and lower production costs. Also important is a
good surface nish to ensure good conductor adhesion and
reduce conductor loss.
A wide variety of dielectric substrates are now com-
mercially available. Characteristics, including mechanical
and thermal as well as electronic facets, of a number of
representative substrate materials, such as alumina,
fused quartz, silicon, gallium arsenide, synthetic, and
composite materials, are compared in Refs. 612.
Although the microstrip line appeared rst in 1952 [4],
the rapid increase of the use of microstrip circuits was
seen during the 1960s when high permittivity and low-loss
dielectric substrates became available. At the same time,
microwave semiconductor devices appeared, and minia-
ture lumped elements (capacitors, resistors, inductors)
r
Ground conductor
Ground conductor
E field
H field
Figure 3. Electromagnetic eld distribution in a stripline. The

fundamental TEM mode is considered. The electric eld goes from
the conductor strip to the grounded planes. The magnetic eld
surrounds the conductor strip.
r
Ground conductor
Strip
conductor
h
t
Dielectric substrate
w
Figure 4. Geometry of a microstrip line. The conducting strip is

placed above a dielectric substrate, which is supported on its bot-
tom by a conducting plate.
became available for implantation on plantar circuits.
Coupled with steady advances in photolithographic tech-
nology, the combination of microstrips, lumped elements,
and semiconductors led to the advent of microwave inte-
grated circuits (MICs) [511].
3.1.3. Field Conguration and Analysis Methods. The mi-
crostrip line is an inhomogeneous transmission line, in-
volving an abrupt dielectric interface between the
substrate and the air above it. The electromagnetic elds
extend over inhomogeneous regions, partly in the dielec-
tric substrate, and partly in the air, as shown in Fig. 5.
Waves propagating along the line cannot be purely TEM,
TE, or TM modes, but hybrid modes containing both elec-
tric and magnetic elds in the transverse and longitudinal
directions of propagation [6]. This may cause some com-
plication in microstrip analysis and design. However, in
many practical situations, the dominant mode of a micro-
strip line resembles closely a TEM mode. Therefore, it is
usually referred to as quasi-TEM mode.
The microstrip line has been analyzed by numerous
workers using various analytical and numerical tech-
niques. As with many other transmission lines, the anal-
ysis methods for a microstrip line are aimed at
determining the characteristic impedance and propaga-
tion constant (phase velocity and attenuation constant).
The various methods of microstrip line analysis can be
divided into two main groups [610]. In the rst group,
which comprises quasistatic methods, the nature of the
mode of propagation is considered to be pure TEM and the
microstrip characteristics are calculated from the electro-
static capacitance of the structure. The quasistatic meth-
ods commonly used include the conformal transformation
method [13], the variational method [14,15], the nite-dif-
ference method, and the integral equation method [610].
It is found that this quasistatic analysis is adequate for
designing circuits at lower frequencies where the strip
width and the substrate thickness are much smaller than
the wavelength in the dielectric material.
The methods in the second group are full-wave ap-
proaches, which take into account the hybrid nature of the
mode of propagation. They include the integral equation
method [16], the spectral-domain method [17], and the -
nite-difference time-domain (FDTD) method [610,17].
The full-wave analysis methods are more rigorous and
can predict frequency-dependent variation of the micro-
strip characteristics. However, they are analytically com-
plex, and usually require large computer memories and
long computation time, which may become prohibitive
when optimization process is demanded in the design of
circuits.
3.1.4. High-Frequency Problems and Quasi-TEM Wave
Results. Microstrip lines have been extensively used for
MICs at frequencies ranging from hundreds of megahertz
to tens of gigahertz. At high frequencies, particularly into
the millimeter wavelength ranges, conductor ohmic and
dielectric losses increase greatly. Surface waves of the di-
electric substrate and higher-order modes excited at dis-
continuities start to propagate or to radiate [610]. The
conductor and dielectric losses and radiation reduce the
amplitude of a signal propagating along the line and may
cause spurious coupling between neighbouring parts of a
circuit. The simultaneous propagation of several modes,
with different velocities, produces a distortion of the sig-
nal. The fabrication tolerances become very difcult to
meet. These factors prohibit the extensive use of micro-
strip lines at high frequencies.
For the majority of microstrip lines suitable for MICs,
the statically derived results are quite accurate when the
frequency is below a few gigahertz. At higher frequencies,
up to the limits for the useful operation of microstrip lines,
these static results can still be used in conjunction with
some quasiempirical functions in closed formulas to nd
the variations of microstrip characteristics with frequen-
cy. Therefore, results by the static techniques are powerful
and significant in the design of microstrip circuits.
3.1.5. Quasi-TEM Wave Parameters. Under the quasi-
TEM wave approximation, an ideal microstrip line can be
represented by the lumped circuit for the TEM transmis-
sion line shown in Fig. 1. The characteristic impedance is
expressed by
Z
0
L
C
_

1
vC
13
When the substrate of the microstrip line is replaced by
air, we have an air-lled line along which the wave will
travel at c, the velocity of light in free space. The charac-
teristic impedance of this air-lled line, dened as Z
a
, is
given by
Z
a
L
C
a

1
c
.
C
a
14
Combining Eqs. (13) and (14), we get
Z
0
1
c
C
.
C
a
p 15
Phase constant
b
o
v
o
LC
p

o
c
C
C
a
b
0
C
C
a
16
E
H
h
w
Figure 5. Electromagnetic eld distribution in a microstrip line.
The fundamental quasi-TEM mode is considered. The electro-
magnetic elds extend over inhomogeneous regions, partly in the
dielectric substrate, and partly in the air.
here b
0
is the wavenumber in free space. The normalized
phase constant is written as
b
b
0
c
v

l
0
l
g
C
C
a
17
here l
0
and l
g
are the wavelengths in free space and along
the microstrip line, respectively. Equations (15) and (17)
indicate that the characteristic impedance and phase con-
stant of a microstrip line can be obtained if we can eval-
uate the capacitance per unit length of the line, with and
without the presence of the dielectric substrate.
The effective permittivity e
e
is dened as the capaci-
tance ratio
e
e
C
C
a
18
From Eq. (17) we immediately get
e
e
c
v
_ _
2
19
b
e
e
p
.
b
0
20
The effective permittivity has a physical meaning that the
original inhomogeneous microstrip line is replaced by an
equivalent homogeneous line with conductors having ex-
actly the same geometry (w,h,t)
,
surrounded by a single
homogeneous dielectric of effective permittivity e
e
.
From Eqs. (17) and (18), we also have the formula
l
g
l
0
e
e
p 21
3.1.6. Formulas for Quasi-TEM Wave Parameters. As
stated previously, closed formulas are of significant im-
portance in the design of microstrip-line circuits. Various
workers have reported formulas for microstrip calcula-
tions [610]. These formulas may be classied into two
types, one for the analysis purpose, and the other for the
synthesis purpose. When the geometric and material pa-
rameters (w,h,t,e
r
) are known, we use the analysis formu-
las to evaluate the lines electrical characteristics e
e
, Z
0
,
and l
g
. Conversely, when Z
0
and e
r
are given and we want
to specify the widthheight ratio w/h of the microstrip
line, we employ the synthesis formulas.
3.1.7. Analysis Formulas (w/h and e
r
Given). Very accu-
rate formulas derived by Hammerstad and Jensen [18] are
provided below:
Effective permittivity e
e
.
e
e
e
r
1
2

e
r
1
2
1 10
h
w
_ _
aw=h
.
be
r
22
with
a
w
h
_ _
1
1
49
ln
w=h
4
w=52h
2
w=h
4
0:432
_ _
1
18:7
ln 1
w
18:1h
_ _
3
_ _
23
be
r
0:564
e
r
0:9
e
r
3
_ _
0:053
24
Characteristic impedance Z
0
.
Z
0
Z
0
2p

e
e
p
.
ln F
1
w
h
_ _
h
w

1
2h
w
_ _
2
_
_
_
_
25
with
F
1
w
h
_ _
6 2p 6 exp 30:666
h
w
_ _
0:7528
_ _
26
where Z
0
120p is the wave impedance in free space. The
accuracy of these expressions is better than 0.01% for w/
hr1 and 0.03% for w/hr1000.
3.1.8. Synthesis Formulas (Z
0
and e
r
Given) [7]. For nar-
row strips (when Z
0
4(44 2e
r
) O)
w
h

expA
8

1
4 expA
_ _
1
27
where
A
Z
0
2e
r
1
_

119:9

1
2
e
r
1
e
r
1
_ _
ln
p
2

1
e
r
ln
4
p
_ _
For wide strips (when Z
0
o(442e
r
) O)
w
h

2
p
B 1 ln2B 1
e
r
1
pe
r
lnB 1 0:293
0:517
e
r
_ _
28
where
B
59:95p
2
Z
0
e
r
p
3.1.9. Strip Thickness Correction. In correcting the re-
sults above, e
e
and Z
0
given by Eqs. (22) and (25), for non-
zero strip thickness t, a corrected strip width w
e
/h is
dened as follows [18]:
w
e
h

w
h

1
2p
t
h
1
1
cosh

e
r
1
p _ _
_ _
.
ln 1
4h exp1
t coth
2
6:517w=h
_

_ _
29
With this corrected strip width, the effect of strip thick-
ness on e
e
and Z
0
of microstrip lines can be included in the
Eqs. (22) and (25). We have therefore
e
e
e
r
1
2
e
r
1
2
1 10
h
w
e
_ _
aw
e
=h
.
be
r
30
Z
0
Z
0
2p

e
e
p
.
ln F
1
w
e
h
_ _
h
w
e
1
2h
w
e
_ _
2
_
_
_
_
31
where Z
0
120p is the wave impedance in free space. In
these expressions, the functions a(w
e
/h), b(e
r
), and F
1
(w
e
/h)
are dened in Eqs. (23), (24), and (26), respectively, with
the normalized strip width w/h replaced by the corrected
normalized strip width w
e
/h. It is observed that the effect
of the strip thickness on e
e
and Z
0
is insignificant for small
values of t/h. However, the effect of strip thickness is sig-
nificant on conductor loss in the microstrip line.
3.1.10. Effect of Dispersion. The effect of frequency (dis-
persion) on e
e
and Z
0
has been described in a number of
publications. The accurate expressions in Ref. 18 for Z
0
(f )
and in Ref. 19 for e
e
(f ) are
Z
0
f Z
0
.
e
e
f 1
e
e
1
.
e
e
e
e
f
_
32
e
e
f e
r
e
r
e
e
1 f =f
50
m
33
where
f
50
f
k;T
0
M
0
0:75 0:75 0:332=e
1:73
r
w=h
f
k;TM
0
c
.
tan
1
e
r
e
e
1
e
r
e
e
_ _ _
2ph

e
r
e
e
p
mm
0
m
c
m
0
1
1
1
w=h
_ 0:32
1
1
w=h
_
_ _
3
m
c
1
1:4
1 w=h
0:15 0:235exp
0:45f
f
50
_ _ _ _
for w=h 0:7
1 for w=h> 0:7
_
_
where Z
0
and e
e
are the quasi-TEM wave values obtained
earlier, and c is the velocity of light in free space.
3.1.11. Effect of Enclosure. Most microstrip circuit ap-
plications require a metallic enclosure for hermetic seal-
ing, mechanical strength, electromagnetic shielding,
mounting connectors, and ease of handling. Because the
fringing electromagnetic elds are prematurely terminat-
ed on the enclosure walls, both the top cover and side walls
tend to lower impedance and effective dielectric constant.
Equations for evaluating the effect of the topcover and
sidewalls on Z
0
and e
e
are provided in Refs. 6 and 7.
When the topcover and sidewalls are placed in close
vicinity of the microstrip line, the line parameters may
vary significantly. It is recommended to leave at least 10
times the substrate thickness between the circuit and the
cover [11].
A metal box is actually a microwave cavity, which res-
onates at some particular frequencies corresponding to its
resonant modes. The size of the box should be chosen in
such a way that the signal frequency does not coincide
with the resonant frequencies. When this cannot be done,
the resonant modes can be damped by placing absorbing
materials at carefully selected locations.
3.1.12. Attenuation. The attenuation constant of a
transmission line is usually dened as
a %
P
loss
2Pz

power loss per unit length
2power transmitted
34
Attenuation is microstrip lines is caused by three loss
components: conductor loss, dielectic loss, and radiation
loss. They are discussed briefly next.
3.1.12.1. Ohmic Losses. Within the conductors, these
result from the nite conductivity s of the metal. The fol-
lowing approximate expression (9) is found sufcient in
most situations
a
c
% 8:686
R
s
wZ
0
dB=m 35
where R
s
om=2s
_
is the metal wall surface resistance.
3.1.12.2. Dielectric Losses. Produced by the energy dis-
sipated within the substrate, these are proportional to its
dielectric loss tangent tand [9]
a
d
% 27:3
.
e
e
1
e
r
1
.
e
r
e
e
p
.
f
c
.
tan d dB=m 36
where c is the velocity of light in free space, and f is the
frequency. The dielectric loss due to the substrate is nor-
mally very small compared with the conductor loss. How-
ever, the dielectric loss in silicon substrates (used for
monolithic MICs) is usually of the same order as or even
larger than the conductor loss because of the large loss
tangent tand of the silicon wafers.
3.1.12.3. Radiation Losses. An innite straight micro-
strip line propagating the dominant quasi-TEM mode does
not radiate. However, at every discontinuity, higher-order
modes are excited, some of which will radiate part of the
power.
3.2. Frequency Range of Operation
Like any other transmission line, microstrip lines cannot
be utilized above a certain upper frequency limit. The
maximum frequency of operation of a microstrip line is
limited because of several factors such as effects of disper-
sion, excitation of higher-order modes, and radiation
losses.
The frequency at which significant coupling occurs be-
tween the quasi-TEM mode and the lowest-order TM sur-
face wave is given by [20]
f
T
300 tan
1
e
r
ph

2e
r
2
p 37
where f
T
is in gigahertz and h is in millimeters.
For a sufciently wide microstrip line, a transverse res-
onant mode can exist that can also couple strongly to the
quasi-TEM microstrip mode. By employing the transverse
resonance equivalent circuit model, and taking into ac-
count the microstrip side-fringing effect, the cutoff fre-
quency of the transverse resonant mode can be easily
derived [20] as follows
f
c
%
300
e
r
p
2w0:8h
38
where f
c
is in gigahertz and w and h are in millimeters.
For a microstrip line, radiation losses become signi-
cant at frequencies higher than [9]
f 2:14
.
e
r
0:25
h
39
where f is in gigahertz and h is in millimeters.
3.3. Power-Handling Capability
Although microstrip lines are not as well suited for high-
power application as are waveguides or coaxial lines of
comparable cross section, they can be used for some me-
dium-power applications. A 50-O microstrip on a 25-mil-
thick alumina substrate can handle a few kilowatts of
power [6].
The power-handling capacity of a microstrip line, like
that of any other dielectric-lled transmission line, is lim-
ited by dielectric breakdown and by heating caused by
ohmic and dielectric losses. An increase in the tempera-
ture due to conductor and dielectric losses limits the av-
erage power-handling capability of the microstrip line,
while the breakdown between the strip conductor and
ground plane limits the peak power-handling capability.
The average power-handling capability of microstrip
lines is determined by the temperature rise of the conduc-
tor strip and the dielectric substrate. The transmission-
line losses, the thermal conductivity of the substrate
material, the surface area of the strip, and the tempera-
ture of the medium surrounding the microstrip line are
the main factors determining the average power-handling
capability of microstrip lines. Therefore, dielectric sub-
strates with low-loss tangent and larger thermal conduc-
tivity will enhance the average power-handling capability
of microstrip lines.
The peak voltage that can be applied without causing
dielectric breakdown determines the peak power-handling
capability of microstrip lines. Thick substrates can
support higher voltages. Therefore, low-impedance lines
and lines on thick substrates have generally larger peak
power-handling capability.
3.4. Other Types of Microstrip Lines
Several derivatives of microstrip lines are being used in
MICs. These include inverted and suspended microstrip
lines, a multilayered microstrip, a thin-lm microstrip,
and a valley microstrip line. These structures are briefly
described in Refs. 6 and 7.
4. OTHER TOPICS
In actual microstrip circuits, various types of transmission
line discontinuities, such as open ends, gaps, steps in
width, bends, T junctions, and cross-junctions are fre-
quently encountered. In the design of microstrip circuits,
a complete understanding of the characteristics of micro-
strip discontinuities included in the circuits is necessary.
At low frequencies, discontinuities can be represented by
lumped-element equivalent circuits based on quasistatic
models. However, at high frequencies, a more rigorous
characterization of frequency-dependent parameters such
as the scattering parameters is required. Various methods
including quasistatic and full-wave analysis methods for
characterizing microstrip discontinuities are described in
Refs. 610 and 17.
Microstrip line is now the most widely used structure
for microwave systems in radar and communication pur-
poses. Examples of passive circuits include lters, imped-
ance transformers, hybrids, couplers, power dividers/
combiners, delay lines, baluns, and circulators. Ampli-
ers, oscillators, and mixers employing solid-state devices
(diodes and transistors) constitute the other class. Micro-
strip-based antennas have also found wide applications
[11,21,22]. Descriptions of the analysis and design of pas-
sive and active microstrip circuits and their applications
in MICs and monolithic MICs (MMICs) are contained in
numerous publications [610]. For further knowledge of
the design and fabrication process of MICs and MMICs,
see Refs. 23 and 24.
There have been a number of sophisticated microwave
computer-aided design (CAD) packages available on the
market. They can be used for analysis purpose (the user
describes a structure and determines its electrical re-
sponse) and synthesis purpose (the software determines
a physical structure meeting a special electrical behavior).
A survey of available CAD softwares for microwave cir-
cuits is given in Refs. 7 and 9.
In addition to the microstrip lines, two other types of
planar transmission lines are also widely used today in
various microwave systems. They are the slotlines and
coplanar lines (coplanar waveguides and coplanar strips).
Hybrid combination of these planer lines with microstrip
lines allows exibility of circuit design and improves the
performance of some circuit functions. Coplanar lines
have received particular attention because of their many
appealing properties. These include low dispersion, high
exibility in the design of characteristic impedance, and
ease of connecting shunt and series lumped elements, or
active devices without using via holes. Consequently, co-
planar lines are used commonly in MMICs in conjunction
with semiconductor devices, which are also coplanar in
nature. Descriptions of the analysis and design of slotline
and coplanar line circuits can be found in Ref. 6 for further
study.
It is worth mentioning nally that the major portion of
this article is devoted to the analysis and design aspects of
the microstrip line with applications to the microwave in-
tegrated circuits. However, high-speed digital circuits in-
clude, as do microwave integrated circuits, active and
passive circuit elements interconnected by sections of
strip and other microstrip transmission lines having a
wide range of characteristic impedances. The speed of dig-
ital circuits has steadily increased since the late 1980s;
hence, the inductive effects on interconnect line perfor-
mance due to line inductance that were previously as-
sumed to be insignificant may be important. Moreover, the
resulting junctions and discontinuities, and the electro-
magnetic coupling between the interconnects, contribute
to reections, signal delay and distortion, and crosstalk,
which can degrade the circuit and system performance.
The same problems are encountered in printed-circuit
boards, single- and multichip modules, and other packag-
es. Therefore, a high-speed circuit design and simulation
must incorporate these interconnections. The analysis of
the microstrip line in this article applies to the vast area of
electrical interconnections for printed-circuit boards, sin-
gle and multichip modules, and other packages. Examples
of these additional applications can be found in Refs. 25
29, listed below.
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MICROSTRIP TRANSITIONS
ERIC L. HOLZMAN
Northrop Grumman Corporation
Baltimore, Maryland
1. INTRODUCTION
Microstrip transmission lines are used widely in micro-
wave and millimeter-wave printed electronic circuits for
routing electromagnetic signals between components such
2654 MICROSTRIP TRANSITIONS
as oscillators, ampliers, and lters. As shown in Fig. 1,
microstrip is a two-conductor transmission line. An insu-
lating substrate separates the two conductors and sup-
ports a transverse eld that is similar to the transverse
electromagnetic (TEM) mode of a parallel-plate wave-
guide. A small portion of the transverse eld permeates
the air above the strip, thus making microstrip inhomo-
geneous. The dominant microstrip mode is a quasi-TEM
mode that is slightly dispersive (the propagation constant
is not a perfectly linear function of frequency). In general,
this mode is broadband, with a cutoff frequency of 0 Hz.
The rst higher-order mode is a surface mode that prop-
agates at a much higher frequency with a cutoff frequency
that depends on the substrates electrical thickness [1].
The TEM mode has two eld components, both directed
transversely. Figure 1 shows the electric eld, oriented
perpendicular to the conductors. The magnetic eld is
parallel to the conductors in the region between the strip
and ground plane. Longitudinal current ows both in the
strip and the ground plane. In the following discussion, we
assume that only the quasi-TEM mode is propagating
within the microstrip.
The characteristic impedance of a transmission-line
mode is dened as the ratio of the modes transverse elec-
tric and magnetic elds. Thus, two different transmission
lines, such as microstrip and coaxial line, could have the
same characteristic impedance but have very different
eld congurations. Typically, microstrip is dimensioned
for a quasi-TEM mode characteristic impedance of 50 O.
This impedance tends to decrease with frequency at a rate
that depends on the substrates electrical thickness. For
substrates that are thin relative to a wavelength, the
characteristic impedance is nearly constant over a wide
frequency bandwidth.
One of microstrips disadvantages is its lack of electri-
cal isolation; the strip conductor is not completely sur-
rounded by the ground plane. Consequently, microstrip
circuits generally have to be housed in a conductive en-
closure to prevent unwanted interference with other cir-
cuits in a microwave system. Coaxial or waveguide
transmission lines provide the interconnections between
different enclosed microstrip circuits. A microstrip transi-
tion is required to convert as efciently as possible the
microstrip electromagnetic properties to that of the inter-
connecting transmission line.
A well-designed microstrip transition converts the
transverse eld conguration and characteristic imped-
ance of microstrip to that of the other transmission line
over a desired frequency band of operation while main-
taining low insertion loss, minimal radiation, and high
input return loss. Insertion loss, the amount of power ex-
iting the transition, expressed as a fraction of the input
level, should be less than 0.25 dB. Return loss, the amount
of power reected at the transition, expressed as a fraction
of the input level, should exceed 15 dB. A good transition
also is easy to fabricate, mechanically robust and insensi-
tive to temperature variations.
Since the rst microstrip circuits were constructed, a
wide variety of transitions to other transmission lines
have been developed. These transitions can be sorted
into two main groups: (1) those that require a direct phys-
ical connection to the strip conductor and (2) those that
use electromagnetic coupling to the strip conductor. Tran-
sitions to other TEM transmission lines such as coax most
often use direct connections, which can provide very
broadband performance. Transitions to waveguide tend
to utilize electromagnetic coupling, which generally is
more mechanically tolerant than a direct connection but
is less broadband.
2. MICROSTRIP-TO-TEM TRANSMISSION LINES
Transitions between microstrip and other transmission
lines propagating the TEM mode can have very wide
bandwidth because the TEM-mode eld conguration
and characteristic impedance remain constant with fre-
quency. In general, the upper frequency of these transi-
tions is limited by the length of the electrical path
connecting the ground conductors and by the tendency of
the interconnections to radiate. In this section, we will
study a number of microstrip transitions to other TEM
structures.
2.1. Transitions to Coaxial Line
The coaxial transmission line provides an inexpensive and
mechanically exible means for making interconnections
below 20 GHz. Figure 2 shows the cross section and elec-
tric eld conguration of the dominant TEM mode in coax.
At rst glance, the eld conguration of coax seems quite
different than that of microstrip, but both have their pri-
mary eld conned between two conductors. Unlike mi-
crostrip, the coaxial eld is uniformly distributed around
Insulating
substrate
Carrier ground ()
Microstrip (+)
E
Figure 1. Microstrip transmission-line cross section.
E
Center conductor (+)
Outer conductor ()
Figure 2. Coaxial transmission-line cross section.
MICROSTRIP TRANSITIONS 2655
the center conductor. Eisenharts transition, shown in
Fig. 3, matches the two eld congurations by offsetting
the coaxial line center conductor in a controlled manner,
forcing the coaxial-line eld to concentrate below the cen-
ter conductor much like that in the microstrip line [2]. The
style of this transition is termed inline or edge launch,
since the coaxial line and microstrip have their longitudi-
nal or propagational axes in line. Eisenharts transition
attains very high performance: he has demonstrated
greater than 25 dB return loss up to 18 GHz. Such a tran-
sition is ideal for testing prototype microstrip circuits.
However, its significant length and relatively high cost
make it undesirable as a transition for inexpensive micro-
wave circuit boards.
Most microwave circuit interfaces require neither the
bandwidth nor the return loss of the Eisenhart transition.
Figure 4 shows a common edge launch transition between
a microstrip on a multilayer circuit board and a sub-min-
iature-A (SMA) coax. The board-mount SMA connector
includes much of the transition. The center conductor of
the coax line is extended out for solder attachment to the
microstrip. The coax ground contact is made with coax
ground pins attached to the connector. Commonly, two
pins are placed below the circuit board also. Because
the circuit board in Fig. 4 has multiple layers, and the
microstrip ground plane is not the bottom layer, this tran-
sition connects the ground pins to metalized pads on the
plane of the microstrip. The pads have drilled and plated
holes or vias that carry the ground currents through the
circuit board to the microstrip ground plane. The length of
the ground path, and in particular, the separation of the
ground pins determines the upper frequency of operation
for this transition. A tuning stub (see Fig. 4), printed on
the circuit board, can provide additional bandwidth. With-
out the stub, the return loss of this transition is better
than 15 dB past 5 GHz. With the stub, the bandwidth can
be extended to 7GHz. How much additional bandwidth a
stub provides depends on whether the transition can be
constructed in a consistent and repeatable manner. If the
stub length has to be adjusted on each circuit board, the
manufacturing process is not sufciently consistent. Liang
et al. have performed extensive analytical investigations
of edge-launched SMA coax-to-microstrip transitions [3].
They compensated capacitively for the parasitic induc-
tance of the soldered coax center pin by increasing the
microstrip linewidth. The measured return loss of their
transition exceeded 15 dB up to 13 GHz.
Occasionally, a connector like that in Fig. 4 may be in-
adequate. The connector ground pathlength limits the up-
per frequency of operation. A connectorless transition like
that shown in Fig. 5 has a much shorter path between the
coax and microstrip grounds. This transition has a return
loss of 15 dB up to 12 GHz for a 0.047-in. coax cable at-
tached to microstrip on a 0.008-in.-thick Rodgers 4003
substrate. The insertion loss at 12 GHz is less than
0.25 dB, which indicates that the transition is not suffer-
ing significant radiation. However, assembling the transi-
tion can be more difcult when miniature coax cable is
used.
Edge-launch transitions, as their name belies, are lim-
ited to placement at the edge of a circuit board. Vertical
mount or orthogonal launch transitions can be placed al-
most anywhere on a circuit board. Figure 6 shows a ver-
tical mounted SMA coax transition. As with the edge
launch connector, the vertical mount connector comes
with an extended center conductor probe and four ground
Center conductor (+)
Microstrip (+)
Carrier ground ()
Outer conductor ()
Figure 3. Microstrip-to-coax transition. (After Eisenhart [2].)
ground
currents
Microstrip
ground on
inner layer
Coplanar
ground pad
FR4
substrate
Coax
connector
housing
Coax ground pin
Soldered coax
center conductor
Microstrip
Tuning stub
Ground
currents
Figure 4. Multilayer circuit board mountable edge
launch microstrip-to-coax transition.
pins. The center conductor and ground pins pass through
vias in the circuit board and are soldered to pads on the
top layer. Within the circuit board, they propagate the
electromagnetic wave as a ve-wire transmission line. On
all intervening conductor layers, it is important to clear
metalization away so as not to short(-circuit) out the eld.
The transition shown in Fig. 6, with a 0.2-in. ground pin
spacing, has a return loss greater than 25 dB to nearly
6 GHz. As with edge launch connectors, the pin-to-pin
spacing establishes the maximum frequency of operation.
An SMP connector, with 0.1-in. ground pin spacing, can be
made to work up to 18 GHz. An indication that the spacing
is too great or the circuit board too thick is excess insertion
loss caused by radiation within the board. One can x this
problem and better conne the eld by inserting circuit
board vias close to the center conductor probe. The vias
effectively replace the connector ground pins as carriers of
the ground current within the circuit board.
2.2. Transitions to Other Planar Transmission Lines
Transitions from microstrip to other planar transmission
lines are often required on multilayer circuit boards,
where it may be desirable to propagate the microwave en-
ergy within the circuit board. Figure 7 shows a microstrip-
to-microstrip transition that passes vertically through a
multilayer circuit board. Essentially, the transition com-
prises a pair of transitions from microstrip to three-via
transmission line. The via separation and a microstrip
open-circuited stub serve to tune the transition. The re-
turn loss of the transition on a circuit board made from
three layers of FR4, 0.062 in. thick, exceeds 25 dB to
nearly 5 GHz.
Transitions from microstrip to coplanar waveguide
(CPW) are relatively common and straightforward to de-
sign. Via holes often are used to connect the microstrip
ground to the coplanar waveguide ground as shown in
Fig. 8. Such transitions are found on monolithic micro-
wave integrated circuits (MMICs), which require wafer-
probe-compatible CPW for their RF input and output [4].
Ellis et al. developed a CPW transition without vias for
MMICs using a slotline to form a CPW as shown in Fig. 9
Substrate
Microstrip
Center
conductor
probe
Ground via
Ground
currents
Figure 5. Inline, connectorless, microstrip-to-coax transition.
Tuning
stub
Center
via
Ground
via
Microstrip
Microstrip
Cleared of
metal
(b)
(c) (a)
via
Figure 7. Microstrip-to-microstrip transition through a multi-
layer circuit board: (a) top/bottom-layer metallization; (b) ground-
layer metallization clearance; (c) circuit board cross section.
Ground pin
Solder
Microstrip
0.062-in
3-layer FR4
Rodgers 4003
Microstrip
ground
50-ohm SMA coax
Ground plane
Ground
currents
Figure 6. Vertical mount, microstrip-to-coax transition.
[5]. Their transition is unusual because it relies on cou-
pling. The CPW is formed in the ground plane of the
microstrip, and the microstrip conductor is coupled or-
thogonally to a single slotline that forms the pair of gaps
in the CPW transmission line.
Transitions from microstrip to less commonly used pla-
nar transmission lines exist also. Drach and Koscica de-
veloped a transition between microstrip and inverted
microstrip line for millimeter-wave applications [6].
3. MICROSTRIP TO WAVEGUIDE
Microstrip-to-waveguide transitions are used for the same
reasons that transitions to coax are usedas intercon-
nects between sealed modules or modules and antennas.
However, unlike coaxial line, waveguides are used mostly
above 20 GHz, often in the millimeter-wave bands, where
their lower loss becomes a significant advantage.
Waveguide is formed from a single conductor, so its
properties are markedly different than those of coax line.
The dominant propagating mode, typically of the trans-
verse electric (TE) conguration, has a cutoff frequency
below which the waveguide is highly attenuative to EM
signals. Figure 10 shows rectangular and circular wave-
guides and their dominant-mode eld congurations.
Most transitions are designed to operate within the fre-
quency band of dominant-mode propagation only, which is
at most 2 : 1 for rectangular waveguide and 1.3 : 1 for cir-
cular waveguide.
The impedance characteristics of waveguide modes
tend to make transitions more challenging to design.
First, the dispersive behavior of waveguide means that
the characteristic impedance of its modes change with
frequency; moreover, the characteristic impedances of
standard guides are much higher than 50 O, typically a
few hundred ohms for TE modes. Consequently, the band-
width for most microstrip-to-waveguide transitions rarely
equals the dominant mode bandwidth.
3.1. Orthogonal Transitions to Waveguide
A transition to rectangular waveguide is often used as the
RF interface between a millimeter-wave transmitter or
receiver and the antenna. Figure 11 shows an orthogonal
or right-angle transition. The microstrip extends through
a narrow channel into the waveguide. The channel dimen-
sions are made sufciently small so that only the micro-
strip mode can propagate over the band of operation.
Within the waveguide, the microstrip ground is removed,
so the microstrip or probe behaves like an antenna. Be-
cause the probe will radiate equally well both up and down
CPW ground
via
Microstrip
CPW
Microstrip ground
Figure 8. Microstrip-to-coplanar waveguide
transition.
40 - 60 - 40
250
200
Slotline
80
Microstrip
90
260
Tapering
slot width
CPW
Figure 9. Microstrip-to-coplanar waveguide transition that op-
erates at 75110GHz. (Source: T. J. Ellis, J. P. Raskin L. P. B.
Katehi, and G. M. Rebeiz, A wideband CPW-to-microstrip transi-
tion for millimeter-wave packaging, 1999 MTT-S International
Microwave Symposium Digest, Vol. 2, pp. 629632. r1999 IEEE.
Reprinted with permission.)
(a) (b)
Figure 10. Commonly used waveguides with dominant-mode
electric elds: (a) rectangular and TE
10
mode; (b) circular and
TE
11
mode.
the waveguide, a backshort (waveguide short circuit) is
placed in the undesired direction approximately a quarter-
wavelength away from the probe. An impedance tuning
section on the probe circuit board, just at the input to the
waveguide, and a fan-shaped probe increase the transi-
tions bandwidth. This transition can be tuned to operate
over a 40% bandwidth with better than 25 dB return loss.
In fabricating this type of transition, one must be sure
that the microstrip ground plane makes electrical contact
with the channel surface to avoid undesired radiative ef-
fects. The probe shown in Fig. 11 is fabricated on a mul-
tilayer substrate, and the microstrip ground plane is not
the bottom layer. To guarantee contact between the mi-
crostrip ground and the channel oor, one can drill via
holes on both sides of the microstrip. Also, to reduce the
machining cost, the waveguide can be fully radiused as it
is in the gure.
The orthogonal transition works well for circular wave-
guide also as shown in Fig. 12. Circular waveguide is eas-
ier to machine than rectangular waveguide, and one can
use a commercially available, adjustable tuner, or simple
dowel as the backshort. The primary disadvantage of cir-
cular waveguide is bandwidth related. Since the circular
waveguide dominant (TE
11
)-mode and rst higher-order
(TM
01
)-mode cutoff frequencies are more closely spaced
than those in the rectangular waveguide, the transition
bandwidth will be less. The transition illustrated in
Fig. 12 can provide a return loss of more than 25 dB over
a 20% bandwidth. Also, unlike rectangular waveguide,
circular waveguides polarization is arbitrary, so disconti-
nuities will excite cross-polarized elds. A short section of
straight waveguide to the antenna is best.
The transitions in Figs. 11 and 12 require waveguide
backshorts spaced about one quarter-wavelength away
from the probe. The position of the backshort must be
controlled precisely to get the lowest insertion loss
through the transition. Further, the backshort can be
the tallest feature in an otherwise very thin module. Con-
sequently, transitions that do not require backshorts or
are insensitive to backshort position have been developed.
Park and Holzman developed two transitions shown in
Fig. 13 that use a slot printed in the microstrip ground
plane to excite the rectangular waveguide [7,8]. Neither
transition requires a precisely placed backshort, although
both enclose the transition in a rectangular cavity to con-
tain any unwanted radiation. The cavity dimensions are
chosen so that no modes are resonant in the frequency
band of operation. For standard rectangular waveguide
sizes, the characteristic impedance of the TE
10
mode is
several hundred ohms, so one cannot expect a good match
if a 50-O microstrip line is centered over the waveguide.
Since the slot eld amplitude varies sinusoidally across
To antenna
Waveguide
Waveguide
backshort
~g/4
Impedance
matching
Channel
walls
Microstrip
Probe
Figure 11. Transition from microstrip to full-
radius rectangular waveguide.
Waveguide
backshort
Waveguide
To antenna
Channel
walls
Microstrip
Substrate
Probe
Figure 12. Microstrip-to-circular waveguide
transition.
the length of the slot, while the magnetic eld is essen-
tially constant, one can offset the microstrip line as in Fig.
13a, and thereby lower the impedance presented to the
strip. In Fig. 13b, a dipole-like structure terminates the
microstrip line. Adjustment of the dipole position and
arm-length matches the transition. In both transitions,
all critical dimensions are photolithographically con-
trolled with high accuracy. The transitions are extremely
compact, but they also are narrowband, providing high
return loss over less than a 10% bandwidth. Villegas et al.
designed an end-launched transition that is much like
Park and Holzmans and achieved a bandwidth of 10%
centered around 45 GHz [9].
Davidovitz overcame the bandwidth limitation in the
ParkHolzman transitions by adding a waveguide taper
as shown in Fig. 14 [10]. Davidovitz reduced the wave-
guide height and mode impedance adjacent to the slot
so that a centered microstrip could be matched. He ared
the reduced height waveguide to the desired height
using a tapered structure. His transition has a measured
return loss exceeding 15 dB over a 50% bandwidth. Al-
though Davidovitz transition does not require a wave-
guide backshort, the length of his taper is about four
TE
10
mode wavelengths at the center of the band. To
(a) (b)
To antenna
Waveguide
Ground
plane
Printed slot
in microstrip
ground
Substrate
Microstrip
Cavity
wall
Figure 13. Microstrip-to-rectangular wave-
guide transitions using printed slot coupling:
(a) offset strip; (b) tee strip. (After Park and
Holzman [7,8].)

Microstrip
Substrate
Cavity
wall
Waveguide
taper
Ground
plane
Printed slot
in microstrip
ground
Figure 14. Microstrip-to-rectangular waveguide transition using
printed slot coupling and waveguide taper. (After Davidovitz [10].)
Input
Microstrip
Metal block
Waveguide
Microstrip
Output
Figure 15. Microstrip-to-microstrip transition using waveguide.
(After Davidovitz et al. [11].)
Microstrip
ground
Substrate
Waveguide
Microstrip
Figure 16. Inline, microstrip-to-waveguide transition. (After Ho
and Shih [12].)
save space, one could use a waveguide quarter-wave
transformer instead of a taper at the cost of reduced band-
width.
Davidovitz has used a similar approach to create a mi-
crostrip-to-microstrip transition through a thick metal
plate as shown in Fig. 15 [11]. A reduced-height wave-
guide provides strong coupling between two microstrip
lines but the bandwidth is very narrow, only a couple of
percent.
3.2. Inline Transitions to Waveguide
Another type of microstrip-to-waveguide transition is the
inline topology shown in Fig. 16 [12]. This particular
structure is constructed by inserting the microstrip sub-
strate in line with the waveguide, and a printed circuit
version of a current loop couples to the TE
10
waveguide
mode. The end of the loop must make electrical contact
with the oor of the waveguide. This transition has about
a 30% bandwidth.
The transition illustrated in Fig. 17 uses a section of
ridged waveguide to transition to standard rectangular
waveguide [13]. The principle of operation is similar to
that used by Eisenhart in his transition to coaxial line [2].
The electric eld concentrates under the ridge, and as the
ridge depth increases, the eld begins to resemble that of
the microstrip mode. Electrical contact is necessary be-
tween the microstrip line and the ridge.
Figure 18 shows another inline transition developed by
Holzman, in this case, to a parallel-plate waveguide feed-
ing a TEM horn radiator [14,15]. A microstrip and its
substrate protrude through a hole in a metalized face-
plate. The microstrip and its ground plane are shaped and
ared such that the electric eld is rotated 901, from the
microstrip mode into a parallel-plate TEM mode, which
Horn flare
Side view
Microstrip
Ground
plane
Ground
Substrate
Faceplate
Substrate
Parallel-plate
Waveguide
Faceplate
(ground)
Front view
Figure 18. Inline, microstrip-to-parallel-plate waveguide transition feeding a TEM horn antenna.
(Source: E. L. Holzman, Awide band TEM horn array radiator with a novel microstrip feed, IEEE
International Conference on Phased Array Systems and Technology Digest, May 2000, pp. 441444.
r 2000 IEEE. Reprinted with permission.)
Ridged
transition
Substrate
Microstrip
Waveguide
Figure 17. Inline, microstrip-to-waveguide transition using a
ridged waveguide transition.
excites the ared horn. Because both the microstrip and
parallel plate transmission lines propagate the TEM
mode, this transition is very broadband, achieving a pre-
dicted bandwidth of 5 : 1. The transitions length must be
at least a half-wavelength at the lowest frequency of op-
eration. Because the eld distribution is uniform in the
parallel-plate waveguide, the transition works just as well
whether the substrate is placed on the waveguide edge or
centerline (see Fig. 18). Further, two or more substrates
can be placed within a single parallel-plate waveguide,
and the energy will be combined over the bandwidth of the
transition. The inspiration for Holzmans transition was a
similar transition to rectangular waveguide developed by
van Heuven [16].
Figure 19 shows an inline transition that uses a printed
slot in the microstrip ground plane to couple to a wave-
guide [17]. The substrate ground plane forms the upper
surface of part of the rectangular waveguide.
4. CONCLUSION
Historically, transition design was an empirical effort, re-
quiring time-consuming building, testing, tuning, and it-
eration of prototype circuits. Today, most transitions are
designed with the aid of commercially available, highly
accurate and fast three-dimensional, generalized electro-
magnetic software [18]. The rst hardware prototype is
built only after the transition design has been optimized
on a computer. Further, the software affords those with
new ideas the opportunity to evaluate them quickly. Thus,
although many different microstrip transitions have been
described in this article, one can expect to see new designs
in the future.
BIBLIOGRAPHY
1. R. K. Hoffman, Handbook of Microwave Integrated Circuits,
Artech House, Norwood, MA, 1987, pp. 181187.
2. R. L. Eisenhart, A better microstrip connector, IEEE MTT-S
Int. Microwave Symp. Digest, 1979, pp. 318320.
3. H. Liang, K. Laskar, H. Barnes, and D. Estreich, Design and
optimization for coaxial-to-microstrip transition on multi-lay-
er substrates, IEEE MTT-S Int. Microwave Symp. Digest,
2001, Vol. 3, pp. 19151918.
4. A. M. E. Safwata, K. A. Saki, W. Johnson, and C. H. Lee,
Novel design for coplanar waveguide to microstrip transition,
IEEE MTT-S Int. Microwave Symp. Digest, 2001, Vol. 2, pp.
607610.
5. T. J. Ellis, J. P. Raskin, L. P. B. Katehi, and G. M. Rebeiz, A
wideband CPW-to-microstrip transition for millimeter-wave
packaging, IEEE MTT-S Int. Microwave Symp. Digest, 1999,
Vol. 2, pp. 629632.
6. W. C. Drach and T. E. Koscica, Transitioning between micro-
strip and inverted microstrip, IEEE Microwave Guided Wave
Lett. 1(3):4950 (1991).
7. P. K. Park and E. L. Holzman, End Launched Microstrip Line
(or Stripline) to Waveguide Transition Using a Cavity Backed
Slot Fed by an Offset Microstrip Line, U.S. Patent 5, 724, 049
(1998).
8. P. K. Park and E. L. Holzman, End Launched Microstrip Line
(or Stripline) to Waveguide Transition Using a Cavity Backed
Slot Fed by a T-Shaped Microstrip Line, U.S. Patent 5, 726,
664 (1998).
9. F. J. Villegas, D. I. Stones, and H. A. Hung, A novel wave-
guide-to-microstrip transition for low-cost millimeter-wave
and MMIC applications, IEEE MTT-S Int. Microwave Symp.
Digest, 1997, pp. 739742.
10. M. Davidovitz, Wide-band waveguide-to-microstrip transition
and power divider, IEEE Microwave Guided Wave Lett.
6(1):1315 (1996).
11. M. Davidovitz, R. A. Sainati, and S. J. Fraasch, A non-contact
interconnection through an electrically thick ground plate
common to two microstrip lines, IEEE Trans. Microwave The-
ory Tech. 43(4):753759 (1995).
12. T. Q. Ho and Y. Shih, Analysis of microstrip line to waveguide
end launchers, IEEE Trans. Microwave Theory Tech.
36(3):561567 (1988).
13. M. V. Schneider, B. Glance, and W. F. Botman, Microwave and
millimeter wave hybrid integrated circuits for radio systems,
Bell Syst. Tech. J. 48:17031726 (1969).
14. E. L. Holzman, A wide band TEM horn array radiator with a
novel microstrip feed, IEEE Int. Conf. Phased Array Systems
Technical Digest, 2000, pp. 441444.
15. E. L. Holzman, Broadband Antenna Element, and Array Us-
ing Such Elements, U.S. Patent 5,898,409 (1999).
16. J. H. C. van Heuven, A new integrated waveguide-microstrip
transition, IEEE Trans. Microwave Theory Tech. 30(3):144
147 (1976).
17. J. J. Lynch, Method and Apparatus for Coupling Strip Trans-
mission Line to Waveguide Transmission Line, U.S. Patent 6,
509, 809 B1 (2003).
Microstrip
Slot in
microstrip
ground
Substrate
Waveguide
Figure 19. Inline, microstrip-to-waveguide transition using aperture coupling. (After Lynch [17].)
18. D. G. Swanson and W. J. R. Hoefer, Microwave Circuit Mod-
eling Using Electromagnetic Field Simulation, Artech House,
Norwood, MA, 2003.
FURTHER READING
J. S. Izadian and S. M. Izadian, Microwave Transition Design,
MICROWAVE AND RADIO FREQUENCY
MULTIPLIERS
D.G. THOMAS Jr.
Panasonic
Atlanta, Georgia
G.R. BRANNER
University of California
Davis, California
B.P. KUMAR
Sacramento State University
Sacramento, California
Frequency multipliers are harmonic generators that pro-
duce various frequency multiples of an input (funda-
mental) frequency. These devices are employed in such
diverse applications as electronic instruments, designing
radar, communications, and electronic warfare systems.
High-frequency signals are generated from lower-frequen-
cy signals by harmonic multiplication, as demonstrated in
the simple representation depicted in Fig. 1. In the devel-
opment of such a device, the circuit designer typically
seeks to maximize the power delivered to the output load
at the Nth harmonic.
The capability of optimization of multiplier performance,
in and of itself, can improve the overall performance of a
system. Such potential for enhanced performance leads to
the optimization process becoming a crucial consideration
in the development of the system. Multiplier performance is
dependent on the nonlinear device producing the required
frequency harmonics and the design technique employed.
The most important design considerations in frequency
multipliers are conversion gain, harmonic suppression, out-
put power, efciency, DC bias requirements, and band-
width. Frequency multipliers exhibiting high conversion
gain, good harmonic suppression, wide bandwidth when
required, and high efciency are achieved from optimum
designs. As will be discussed in this article, many authors
give various, contradictory means of optimizing the perfor-
mance of frequency multipliers.
One of the dominant operating parameters of a fre-
quency multiplier is its conversion gain or conversion loss.
The conversion gain is the ratio of the output power at
the desired harmonic frequency to the input power at the
fundamental frequency. It has been demonstrated that
various parameters affecting the conversion gain include
the bias level, the input power, the harmonic termina-
tions, and the nonlinear device producing the frequency
harmonics [17]. Techniques that maximize the conver-
sion gain are necessary for the development of frequency
multipliers.
With the advent of newactive devices, such as the high-
electron-mobility transistor (HEMT), the pseudomorphic
high-electron-mobility transistor (PHEMT), and the he-
terojunction bipolar transistor (HBT), new multiplier de-
signs incorporating these devices are desired. This has led
to the emergence of new research areas where relatively
little information has been reported in the literature. This
presentation will address some of these areas. Some areas
considered are the development of accurate nonlinear cir-
cuit models, identifying pertinent properties of the tran-
sistor, optimizing multiplier designs, and improving some
of the existing design techniques.
1. APPLICATIONS OF FREQUENCY MULTIPLIERS
The extension of system operating frequencies into higher
frequency bands has led to considerable interest in gen-
erating RF power at lower frequencies and using a non-
linear device to achieve RF power at a higher harmonic
frequency. Harmonic generators provide a convenient
source of signals at higher frequencies, where direct gen-
eration from an oscillator is difcult or inconvenient. The
frequency multiplier produces an output signal at a har-
monic frequency multiple of the fundamental input
frequency and eliminates the requirement for a high-fre-
quency oscillator. The ability to design frequency multi-
pliers generating the higher harmonic frequencies has
made frequency multipliers important circuits in RF and
microwave components, and thus they nd a wide range of
use in the electronics arena. Applications include instru-
ment design, radar systems, communication systems, sub-
scriber radio systems, and low-phase-noise electronic
warfare (EW) applications.
1.1. Communication Systems
As an illustration demonstrating the convenience of a fre-
quency multiplier, consider a communication system re-
quiring a 15 GHz local-oscillator (LO) source as shown in
Fig. 2. The conguration shows a 15-GHz source driving
the LO chain of the mixer. Alternatively, the 15 GHz
source can be replaced by a 5-GHz local oscillator and fre-
quency tripler to obtain the required 15 GHz signal. Ad-
vantages in using the 5-GHz source over the 15-GHz
source lie in the cost associated with the two sources,
because high-frequency components usually are more
expensive than lower-frequency ones. Additionally, the
5-GHz source could possibly pose less of a design chal-
lenge than the 15-GHz source. With this change in the
conguration, the nal circuit is represented by Fig. 3.
Frequency multiplier applications have been extended
to monolithic microwave integrated circuit (MMIC)
f
in
f
out
= Nf
in
N
Figure 1. Simple harmonic multiplier.
MICROWAVE AND RADIO FREQUENCY MULTIPLIERS 2663
receivers in communication systems [811]. One such ap-
plication is shown in Fig. 4 [9]. In this conguration, two
doublers are used in series to supply the LO chain of the
mixer. Using these doublers in the topology allows a
6.5 GHz voltage-controlled oscillation (VCO) to be imple-
mented. The 6.5 GHz signal is led into the two frequency
doubler circuits, which produce an output signal at
26 GHz. Without the use of the two doubler circuits in
the block diagram, a 26-GHz VCO would have been
required.
1.2. Cellular Applications
Wireless applications operating in the 9002500 MHz
range frequently use frequency multipliers in their design
topologies. The systems include synthesizers, transmit-
ters, receivers, and transceivers [12]. A transmitter topol-
ogy demonstrating the use of frequency multipliers is
shown in Fig. 5. The modulated signal at 450MHz is mul-
tiplied by the doubler to produce a signal at 900MHz for
transmission.
The receiver topology using a frequency doubler is
shown in Fig. 6. The doubler is placed in the LO chain of
the downconverter. The downconverter produces an inter-
mediate frequency (IF), which is signal-processed to ob-
tain the desired information from the signal.
As a nal example, a block diagram of a transceiver
employing the use of a frequency doubler is shown in
Fig. 7 [12]. This topology uses a single LO source. The
doubler is used in the LO chain of the receiver and to pro-
duce the transmitting frequency in the transmitter.
2. PASSIVE FREQUENCY MULTIPLIERS
As mentioned previously, frequency multipliers are har-
monic generators that produce frequency multiples of an
input (fundamental) frequency. At radio- and microwave
frequencies, frequency multipliers typically employ a non-
linear device to generate the desired harmonic spectrum.
The choice of this nonlinear device divides multipliers into
two categories: passive multipliers and active multipliers.
In the case of the active multipliers, the nonlinear device
includes any of the devices in the transistor classes (BJT,
FET, MESFET, etc.), as will be discussed in the following
section. This section will discuss the development of pas-
sive multipliers. The discussion will include the basic the-
ory and operation of passive multipliers, various devices
LO
15GHz
IF RF
Mixer
Output
Figure 2. Conguration without frequency multiplier.
LO
Output
Frequency
tripler
15 GHz
5 GHz
IF RF
Mixer
Figure 3. Conguration with frequency multiplier.
LNA
RF Input
Output
26 GHz
amplifier
1326 GHz
doubler
6.5 GHz
VCO
DC
Control
PLL Controller
2
2
N
6.513 GHz
doubler
IF
Figure 4. Block diagram of 26GHz MMIC receiver Model.

Band-pass
filter
VCO
PLL Filter
Base
band
input
Power
amplifier
Frequency
doubler
Figure 5. Block diagram of 26GHz MMIC receiver model.
2664 MICROWAVE AND RADIO FREQUENCY MULTIPLIERS
that are typically used in the development of passive mul-
tipliers with their various advantages and disadvantages,
the nonlinear mechanism responsible for harmonic pro-
duction, power considerations, optimization of efciency,
realizations, and design topologies.
2.1. Background and Theory
As mentioned, frequency multipliers at radiofrequencies
typically require a nonlinear element to produce the de-
sired harmonic spectrum. For passive multipliers, this re-
quirement is fullled by the exploitation of the nonlinear
characteristics of nonlinear resistors, nonlinear inductors,
or nonlinear capacitors. The excitation of these devices by
an input fundamental frequency produces an output spec-
trum possessing the desired harmonic output of interest.
Typical nonlinear devices providing the aforementioned
properties in the development of passive frequency multi-
pliers include rectifying metalsemiconductor junctions
with their nonlinear currentvoltage characteristics, re-
verse-biased metalsemiconductor or p-n junctions with
their nonlinear capacitance, and nonlinear transmission
lines having distributed nonlinear capacitance [13].
As mentioned, harmonic generation is produced in a
passive frequency multiplier whenever a sinusoidal input
signal drives a nonlinear impedance. A variable resis-
tance, inductance, or capacitance whose magnitude var-
ies instantaneously with the applied voltage or current
characterizes this nonlinear impedance. Semiconductor
diodes have been reported throughout the literature as
an efcient means of providing the necessary nonlinear
characteristics for passive multiplier design [9,11,1341].
The diodes have various characteristics, which produce, as
expected, different performance.
Varactor diodes are commonly used by microwave de-
signers in the development of passive multipliers with
great success [1417]. The varactor diode is a variable-re-
actance element where the diode junction capacitance
changes nonlinearly as a function of the applied voltage,
as will be discussed in the following section. Varactors are
classied into two major categories: (1) p-n junction var-
actors, which are widely used at microwave frequencies,
and (2) Schottky junction devices, typically used for mil-
limeter-wavelength applications. It has been shown by
Manley and Rowe [42], as will be discussed later, and it
has been mentioned by other authors [19,43,44] that a
nonlinear capacitance (reactance) harmonic generator,
such as that developed with a junction varactor, can the-
oretically generate harmonics with efciencies ( P
out
/P
in
)
approaching 100%. On the other hand, passive frequency
multipliers utilizing passive nonlinear resistors for har-
monic generation have at most an efciency of 1/N
2
, where
N is the order of the harmonic, as shown by Page [45] and
referenced by other authors [15,16,19]. Therefore, in the
case of a frequency doubler, theoretically, the highest ef-
ciency achievable is 25% (N2).
The step recovery diode is also used in passive frequen-
cy multiplier design for lower frequencies (30GHz) [17].
The step recovery diode is another variable-reactance el-
ement, which is a variation of the varactor diode. Archer
[26] states that the step recovery diode is a p-n junction
diode explicitly designed to enhance the charge storage
capacitance associated with minority carrier injection
during forward conduction and that the charge storage
capacitance supplies the nonlinearity necessary for har-
monic generation. According to the available literature,
step recovery diodes are not as popular as varactor diodes
in the design of passive frequency multipliers because of
the complexity in reproducible control of the forward in-
jection of minority carriers. Therefore, the ensuing dis-
cussions will not focus on step recovery diodes.
2.2. Diode Model
As will be mentioned in the following section, one of the
most important tools of microwave circuit designers is the
+
VCO
Frequency
doubler
Amplifier
Filter
LNA LNA Filter Filter Demod
Filter PLL
Figure 7. Transceiver employing frequency multiplier.
Filter
RF IF
Analogto
digital
converter
LO
Mixer
Frequency
doubler
Amplifier Demodulator
Figure 6. Receiver employing frequency multiplier.
availability of device circuit models, which allows the per-
formance of the device to be predicted before and after
embedding with external networks. Since a diode model is
essential in the understanding and development of pas-
sive frequency multipliers utilizing these devices as the
source of nonlinearity, the following discussion will be
devoted to the circuit model of the diode.
An equivalent-circuit model for the varactor model is
shown in Fig. 8. This simple circuit model contains a fre-
quency-dependent series resistance R
s
and a voltage-de-
pendent nonlinear conductance g(v) in parallel with the
voltage-dependent junction nonlinear capacitance C
j
(v),
where v is the voltage over the junction [17,36]. The non-
linear conductance, which can produce resistive multipli-
cation, is dened as [36]
gv
@i
g
@v
1
i
g
I
sat
exp
qv
ZkT
_ _
1
_ _
2
where I
sat
is the diode saturation current, q is the magni-
tude of the electron charge, Z is the ideality factor of the
diode, k is the Boltzmann constant, and T is the diode
temperature. The nonlinear capacitance C
j
(v), which is
responsible for supplying the nonlinear reactance, is de-
ned as [36]
C
j
v
C
j0
1 v=f
bi
g
3
where C
j0
is the zero-bias junction capacitance, bi is the
built-in voltage potential, and is related to the doping pro-
le in the epitaxial layer. Raisanen [36] indicates that
typical values of these parameters for a varactor diode
with radius of 15 m are as follows: the zero-bias junction
capacitance C
j0
320 fF, series resistance R
s
520,
built-in potential bi 0.61.0V, ranging from 0.4 to 0.5.
The series resistance R
s
arises from the undepleted ma-
terials in the diode and the contact resistance [14].
As shown in this model, suitable nonlinear elements
exist for harmonic generation, namely, the nonlinear re-
sistor 1/g(v) and the nonlinear capacitance C
j
(v). As was
mentioned earlier and will be discussed later, harmonic
generation due to the nonlinear reactance produced by
C
j
(v) is theoretically more effective because it is possible to
convert all the available power applied to a lossless non-
linear reactive element to output power at any higher
harmonic frequency. An ideal resistive multiplier utilizing
the nonlinear resistor 1/g(v) theoretically has a maximum
efciency of only 1/N
2
, where N is the harmonic frequency.
2.3. Nonlinear Mechanism
As mentioned previously, high-frequency signals can be
generated from lower-frequency signals by harmonic mul-
tiplication. Frequency multipliers provide an efcient
means of exploiting the nonlinear characteristics of vari-
ous devices to provide the desired harmonic multiplica-
tion. The circuit designer of frequency multipliers seeks to
accentuate the device nonlinearity in a particular way
such that exciting the nonlinear device by a sinusoidal
input signal at a fundamental frequency produces an out-
put spectrum at harmonic frequencies of the input funda-
mental, which obviously includes the desired harmonic of
interest. This section will identify and discuss the general
nonlinear mechanisms responsible for harmonic produc-
tion in passive frequency multipliers.
It was noted in the previous section that nonlinear re-
sistors, nonlinear capacitors, and nonlinear inductors
could be exploited for their nonlinear characteristics. Typ-
ical nonlinear devices providing these nonlinear charac-
teristics essential for harmonic production include
rectifying metalsemiconductor junctions with the nonlin-
ear currentvoltage characteristics, reverse-biased metal
semiconductor or p-n junctions with their nonlinear
capacitance, and nonlinear transmission lines having dis-
tributed nonlinear capacitance [13]. As a simple example
demonstrating harmonic generation, consider a nonlinear
device whose nonlinear transfer function can be repre-
sented as a polynomial of the form
V
out
a
1
V
in
a
2
V
3
in
4
where a
1
and a
2
are constants. Inserting a sinusoidal in-
put (V
in
cos ot) into Eq. (4) gives
V
out
a
1
cos ot a
2
cos ot
3
a
1
cos ot a
2
1
4
cos 3ot
3
4
cos ot
_ _
a
1
3a
2
4
_ _
cos ot
a
2
4
cos 3ot
5
Equation (5) shows that an output harmonic is generated
at the fundamental frequency (o) and the third-harmonic
frequency [3]. Therefore, for the specific application of a
frequency tripler, this nonlinear device, as represented by
the transfer function given in Eq. (4), theoretically pro-
vides the nonlinear characteristics for the design of a fre-
quency tripler.
Throughout the literature, researchers and designers
have developed passive multipliers, typically with nonlin-
ear diodes. For this reason, the ensuing discussion focuses
on the nonlinear mechanism associated with semiconduc-
tor diodes, which are used throughout the microwave in-
dustry.
As mentioned, semiconductor diodes have been report-
ed throughout the literature as an efcient means of har-
monic production. To demonstrate the nonlinear
mechanism of the diode, consider an abrupt p-n junction
diode, shown in Fig. 9, excited by an applied voltage V
a
R
S
C
j
(v) g(v)
Figure 8. Varactor diode circuit model.
[46]. Muller and Kamins [46] show that
X
d
X
p
X
n
2e
q
f V
a
1
N
a
1
N
d
_ _ _ _
1=2
6
X
p
2ef V
a
qN
a
1 N
a
=N
d
_ _
1=2
7
X
n
2ef V
a
qN
d
1 N
d
=N
a
_ _
1=2
8
where
X
p
reactance of depletion region extension into p-
type semiconductor
X
n
reactance of depletion region extending into the
n-type semiconductor
X
d
reactance of total depletion region
f built-in potential
V
a
applied voltage
N
a
, N
d
semiconductor dopant concentrations
e permittivity
By charge neutrality, we obtain
N
a
X
p
N
d
X
n
9
QqN
d
X
n
qN
a
X
p
10
dQqN
d
dX
n
qN
a
dX
p
11
C
j
V
a

dQ
dV
a
dQ
dX
p
dX
p
dV
a
12
qN
a
e
2qN
a
1 N
a
=N
d
f V
a
_ _
1=2
13
qeN
a
N
d
2N
a
N
d
_ _
1=2
1
f V
a
_ 14
C
j0
1 V
a
=f
_ 15
where
C
j0
qeN
a
N
d
2N
a
N
d
_ _
1=2
16
Equation (15) shows that the magnitude of the junction
capacitance varies nonlinearly as a function of applied
voltage V
a
, which is essential for generating frequency
harmonics when a sinusoidal voltage is added to V
a
. Using
a binomial series expansion on Eq. (15) yields
C
j
V
a
C
j0
1 V
a
f
_ _
1=2
C
j0
1
1
2
V
a
f
_ _
3
8
V
a
f
_ _
2
5
16
V
a
f
_ _
3
_ _
17
a
0
a
1
V
a
a
2
V
2
a
a
3
V
3
a
18
i 0
a
i
V
i
a
19
where
a
0
C
j0
a
1
C
j0
2f
a
3

5C
j0
16f
3
.
.
.
From Eqs. (12) and (18), we obtain
dQV
a
C
j
V
a
dV
a
20
QV
a

_
C
j
V
a
dV
a
21
_
a
0
a
1
V
a
a
2
V
2
a
dV
a
22
a
0
V
a
1
2
a
1
V
2
a
1
3
a
2
V
3
a
1
4
a
3
V
4
a
23
i 0
a
0
i
V
i 1
a
24
where
a
0
0
a
0
a
0
1
1
2
a
1
a
0
2
1
3
a
2
.
.
.
Demonstrating the effect of applying a sinusoidal signal
across the p-n junction, the current across the diode can be
calculated from
It
dQ
dt
25
X
d
X
p
V
a
X
m
pregion nregion
+
Figure 9. p-n junction diode structure.
Inserting Eq. (23) into Eq. (25) with the p-n junction
excited by the sinusoidal signal V
a
cos ot gives
Qa
0
V
a
1
2
a
1
V
2
a
1
3
a
2
V
3
a

C
j0
cos ot
C
j0
4f
cos
2
ot
C
j0
8f
2
cos
3
ot . . .
26
C
j0
8f
2
C
j0
3C
j0
32f
2
_ _
cos ot
C
j0
8f
cos 2ot
C
j0
32f
2
cos 3ot
27
and inserting Eq. (27) and differentiating gives
It
dQ
dt
o C
j0
C
j0
32f
2
_ _
sin ot
2oC
j0
8f
sin 2ot
3oC
j0
32f
2
sin 3ot
28
This result illustrates the various frequency harmonics
produced by the p-n junction when excited by a sinusoidal
source and demonstrates the nonlinear mechanism by
which the semiconductor diode produces harmonic gener-
ation. This variable capacitance has led semiconductor di-
odes, varactors, and the like to be vital components aiding
microwave engineers in nonlinear circuit development.
2.3.1. VoltageCapacitance and ChargeCapacitance
Characteristics. As previously stated, harmonic generators
utilizing the nonlinear capacitance characteristics of var-
actors are often employed throughout the microwave in-
dustry by researchers and designers. The voltage and
chargecapacitance characteristics of the varactor diode
are important in analyzing and studying the behavior of
diodes. This section will discuss the relationships between
the voltage and the capacitance and between the charge
and the capacitance, since they are often utilized in study-
ing the performance and the design of passive frequency
multipliers.
We refer to the diode example above along with Eqs.
(12) and (15), which are restated below [18]:
C
j
v
dQ
du

C
j0
1 v=f
m
29
where
v voltage across the junction in the absence of any ap-
plied bias
f built-in potential
C
j
0 zero-bias junction capacitance
m index number (
1
2
for abrupt junctions, and for lin-
early graded junctions)
Scanlan (18) indicates that the minimum capacitance
(C
min
) occurs at the reverse breakdown voltage (v V
R
)
and the junction capacitance at this bias is
C
min
C
j
V
R

C
j0
1 V
R
=f
m
30
Letting V
0
V
R
f and rewriting Eq. (30) gives
C
j0
C
min
1
V
R
f
_ _
m
C
min
1
V
0
f
f
_ _
m
31
and inserting Eq. (31) in Eq. (29) gives
C
j
v
C
min
1
V
0
f
f
_ _
1
v
f
_ _
m
m
C
min
V
0
f v
_ _
m
32
From Eq. (29)
dQC
j
vdu 33
and inserting Eq. (32), we obtain
Qv
_
C
j
vdv

C
min
V
m
0
1 m
f v
1m
k
34
where k is the constant of integration. When v f, the
voltage across the junction is zero and the charge is zero,
which indicates that k 0 as well. This allows Eq. (34) to
be rewritten as follows, where the charge is represented as
a function of the voltage:
Qv
C
min
V
m
0
1 m
f v
1m
35
The depletion region reactances X
p
, X
n
and the electric
eld across p-n junctions increase as the reverse bias in-
creases [46]. Intuitively, there are physical limitations to
these increases, as governed by the structure of the junc-
tion and the dopant concentrations. As the reverse bias
increases, eventually a voltage is encountered where the
barrier to current ow is broken, and current ow in-
creases substantially. The voltage at which this occurs is
dened as the breakdown voltage (v V
R
). At the break-
down voltage, Eq. (35) gives
QV
R
Q
R

C
min
V
m
0
1 m
fV
R
1m
36
and recalling that V
0
V
R
f gives
QV
R
Q
R

C
min
V
0
1 m
37
Now, dividing Eq. (35) by Eq. (37) gives
Qv
Q
R
C
min
V
m
0
1 m
f V
R
1m
C
min
V
m
0
1 m
f u
V
0
_ _
1m
38
This expression relates the charge across the junction in
terms of breakdown characteristics (V
R
, Q
R
) and the min-
imum capacitance (C
min
).
Historically, in the literature, the capacitance is used in
dening the elastance [18,19]:
Sv
1
Cv
and S
max
1
C
min
39
This allows Eq. (32) to be rewritten in terms of the ela-
stance as shown below, where the elastance is written as a
function of voltage:
Cv
C
min
V
0
f u
_ _
m
S
max
S u
40
or
Sv
S
max
f u
V
0
_ _
m
41
Referring back to Eq. (38), the charge Q(v) is expressed as
a function of u. Alternatively, Eq. (38) can be rearranged to
give the voltage as a function of the charge:
vQ f V
0
Q
Q
R
_ _
1=1m
V
0
f V
0
Q
Q
R
_ _
1=1m
42
and therefore
v V
R
V
0
1
Q
Q
R
_ _
1=1m
_ _
V
0
1
Q
Q
R
_ _
g
_ _
43
where
g
1
1 m
Equations (29)(43) are mathematical expressions for the
characteristics between the voltage, charge, capacitance,
and elastance of p-n junction semiconductor diodes. Re-
searchers and designers often use these expressions,
among others, in analyzing diodes and incorporating di-
odes into multiplier designs.
2.4. Power Considerations
A discussion on power ow into and out of the nonlinear
device is very useful in understanding the behavior of
passive nonlinear devices and their usefulness in design-
ing passive frequency multipliers, as it can be used to pre-
dict optimum power and conversion efciency. Here we
will discuss the power ow at the various harmonics and
their relation to the performance of frequency multiplier
designs, which leads to a fundamental understanding of
the limitations imposed by diodes.
Manley and Rowe [42] have provided a general relation,
which is commonly used throughout the microwave indus-
try, for discussing the power ow of a particular class of
nonlinear elements. They derive general power relations
that govern single-valued nonlinear elements such as non-
linear inductors and capacitors. Their nal derivations, in-
dependent of input power, give two independent equations
characterizing the power content at various harmonics.
Manley and Rowe perform their derivation on an ideal
nonlinear capacitor, but state that a similar analysis can
be performed on a nonlinear inductor. Their analysis be-
gins by evaluating the voltage across the nonlinear capac-
itor, which is dened as some arbitrary function of the
charge. Then, they write an equation for the charge across
the capacitor represented in a Fourier series. From the
charge, they are able to calculate the current in Fourier
series form. Next, the voltage across the nonlinear capac-
itor is given in a Fourier series, from which the Fourier
coefcients for the voltage are calculated using orthogo-
nality. After further substitutions and integrations, they
conclude with the following equations
m
mP
mn
mf
1
nf
2
0 44
m
nP
mn
mf
1
nf
2
0 45
where m and n are integers representing various harmon-
ics and P
mn
is the average power owing into the nonlin-
ear reactances at the frequencies mf
1
and nf
2
. These
equations are significant in that they indicate that for
an ideal, lossless capacitance (with R
s
0 in Fig. 8), the
sum of all inward power ows at the different frequencies
must be zero. This indicates, theoretically, that on exciting
the nonlinear capacitor at a fundamental frequency, the
output power at the desired harmonic has the same mag-
nitude as the input power of the fundamental. This is
achieved provided all power at the undesirable harmonics
has been reactively terminated, which ensures that no
power is dissipated at these undesirable harmonics.
As an example demonstrating this procedure, consider
exciting a nonlinear capacitor at the fundamental fre-
quency f
1
(m1, n0). Then Eq. (44) gives
P
10
f
1
mP
m0
mf
1
0 46
or
P
10

1
m2
P
m0
47
or in general, the sum of all powers owing at the various
harmonic frequencies must be zero. Equation (47) indi-
cates that the input power P
10
at the fundamental is the
sum of the output powers at all harmonics combined.
Therefore, if external embedding circuitry to which the
nonlinear capacitor is connected is developed such that
the power at all undesirable harmonics is reactively ter-
minated, then the power delivered to the load at the de-
sired harmonic can, theoretically, represent conversion
efciencies of 100% (17). Practical diodes, however, exhib-
it nonzero series resistance R
s
O0 , so that practical con-
version efciencies are less than 100%.
2.5. Optimization of Efciency
Achieving optimum efciency is an essential goal in the
design of any component. In the case of passive multipli-
ers, proper techniques should be employed in efforts to
maximize the conversion efciency of the multiplier and
maximize the power delivered to the load at the desired
harmonic.
The ManleyRowe equations given above indicate that,
theoretically, an ideal nonlinear capacitor can achieve
100% conversion efciency. In practical applications, non-
linear capacitors (varactors) are not ideal components but
have some loss. Therefore, as a general example, the var-
actor utilized in passive multiplier design should exhibit
low series resistance (R
s
) at the frequency and power level
of operation [18,36]. Impedance matching at the input of
the nonlinear device is also required, to ensure that the
input power is efciently coupled to the diode. Similarly,
output impedance matching at the desired harmonic of
interest should be implemented so that power generated
in the nonlinear device at the output harmonic is efcient-
ly transferred to the load. Significant real power should
exist in the diode at the fundamental and the output har-
monic of interest and low-loss resonators should be uti-
lized as idler circuits [13,4244,47], which will be
discussed later in the article.
Archer and Batchelor [17] note that an equivalentcir-
cuit model of a varactor diode embedded in external
circuitry can be utilized to predict and optimize the per-
formance of a passive multiplier. They give an equivalent
circuit for a varactor multiplier, showing the connection
between the varactor and the embedding network, as in
Fig. 10. There, the embedding network models the imped-
ance presented to the diode at the fundamental frequency
and other harmonics. The two networks (embedding and
equivalent diode circuit model) are optimized to obtain
maximum power transfer between the embedding net-
work and the reactance of the diode at the input funda-
mental frequency and the output harmonics. This
optimization can be performed manually using the math-
ematical equations governing the response of the net-
works or through an optimization routine provided by a
commercial circuit simulator.
The conversion efciency is dependent on the large-sig-
nal diode currents and voltages, which are determined by
the impedances presented to the diode at the fundamental
and higher harmonic frequencies [17,18]. Simulations
can be performed to optimize the conversion efciency,
utilizing the impedances presented to the diode in con-
junction with the diode circuit model.
The steady-state large-signal voltage and current coef-
cients are V
k
and I
k
[17].
v
j
t
k
V
k
e
jk2pft
48
i
c
t
k
I
k
e
jk2pft
49
where f is the fundamental frequency. The predicted per-
formance and thus the optimization of efciency are de-
termined after solving Eqs. (48) and (49) subject to the
boundary conditions imposed by the diode and the embed-
ding network [the embedding impedance Z
e
(f)]. Such so-
lutions have been calculated and presented by various
authors [9,11,1418,2041], using idealized models, to ob-
tain the nonlinear large-signal behavior of specific multi-
pliers (doublers, triplers, etc.). They present data on the
efciency, power handling, input and load resistances, and
P
max
/P
in
, for example, versus frequency for various multi-
pliers. Using such plots and data, theoretical optimization
can be achieved for specific multiplier types.
In summary, it is important to optimize the perfor-
mance of frequency multipliers. Chang et al. [29] state
general guidelines for achieving this:
1. Good impedance matching should be provided at the
input and output of the nonlinear device over the
frequency range of interest, and all idler circuits
terminated reactively with low loss.
2. At frequencies other than the fundamental, desired
harmonic of interest, and idler harmonics, the non-
linear device should be mismatched to the embed-
ding circuitry to minimize power loss.
Diode circuit model
Z
L
(nf
0
)
Z
L
(f
0
)
nf
0
2f
0
Z
e
(f )
E
g
(f
0
)
Z
S
Embedding network
Figure 10. Equivalent network model of passive frequency mul-
tiplier.
3. The input and output networks should be isolated
physically and electrically.
2.6. Idlers
An important concept in the fundamental development of
passive frequency multipliers, as briefly mentioned in pri-
or sections, is that of idler currents and idler circuits. Idler
currents are currents owing at frequencies other than
the input fundamental frequency and output harmonic
frequency, which are required for a particular class of pas-
sive multipliers [47]. This section will discuss the property
of idlers and demonstrate the requirement of them for
particular multiplier designs.
In Section 2.3.1, the voltage and charge relations of
nonlinear varactors were discussed. Referring to Eq. (42),
it is observed that a square-law characteristic is exhibited
by an abrupt junction diode m
1
2
_ _
; the voltage is propor-
tional to the square of the charge [43]. Consider the con-
dition in which the charge across the junction of an abrupt
junction diode is sinusoidal at the fundamental frequency
o2pf
Qt Q
0
Q
1
cos ot 50
where Q
0
is the DC biasing component. Inserting Eq. (50)
into Eq. (42) and using the trigonometric identities gives
vQ f V
0
Q
Q
R
_ _
2
51
vt f V
0
Q
0
Q
1
cos ot
Q
R
_ _
2
52
f
V
0
Q
2
R
Q
2
0
Q
2
1
2
_ _
2V
0
Q
0
Q
1
Q
2
R
cos ot
V
0
Q
2
1
2Q
2
R
cos ot 53
From Eq. (53) it is observed that the voltage produced by
the charge across the abrupt junction diode has a DC
component, a component at the fundamental frequency,
and a component at the second-harmonic frequency, but
no component at any harmonic higher than the second,
such as required for frequency triplers, quadruplers, and
so on. The component at the second-harmonic frequency
indicates that this diode is suitable for a frequency dou-
bler, however. This example indicates that except for the
case of the doubler, if currents ow only at the input and
output frequencies, it is impossible to generate harmonics
higher than the second with an abrupt junction varactor.
This is an expected result due to the square law behavior
of the varactor. Thus, in order to achieve output harmonics
for n42, it is necessary for intermediate currents (idler
currents) to ow in the varactor at specific harmonic
frequencies.
The abrupt junction varactor can be regarded as pro-
viding a mechanism for frequency doubling (due to the
square-law relationship mentioned previously) and for
frequency mixing when idler currents are utilized [19].
In the case of mixing, currents owing at specific harmon-
ic frequencies are mixed with the fundamental frequency
and with each other (if more than one is introduced) to
produce additional currents at various harmonics. There-
fore, introducing an idler current into an abrupt junction
varactor at the second-harmonic causes the second-har-
monic to mix with the fundamental frequency to produce
an output at the third harmonic. This additional idler pro-
duces the component necessary for frequency tripler de-
sign.
Introducing additional currents into an abrupt junction
varactor provides a means for the device to generate high-
er harmonics. This extends the use of abrupt junction
varactors from frequency doublers to higher-order multi-
pliers.
2.7. Analysis Techniques
Passive frequency multipliers are nonlinear circuits re-
quiring solutions from large-signal circuit analysis. As
stated in preceding subsections, the efciency of passive
multipliers utilizing diodes is affected by the diode param-
eters: the embedding impedance Z
e
(nf
0
) at the fundamen-
tal and harmonic frequencies, the input power level P
in
,
and the bias voltage. Various techniques are utilized by
researchers and designers for analyzing and optimizing
nonlinear circuits and, specifically, passive multipliers. In
some simple cases, analytic closed-form solutions may be
obtained for optimizing the efciency; however, for most
cases the most convenient method is through numerical
analysis. Some of these techniques include power series
analysis, Volterra series analysis, and harmonic balance
techniques where time-domain current and voltage solu-
tions are sought that satisfy the diode boundary condi-
tions and frequency-domain solutions are sought that
satisfy the external circuit equations. Using these analy-
sis techniques along with an accurate equivalent circuit
model of the passive nonlinear device, the predicted per-
formance of the device embedded in external circuitry can
be obtained.
Since the analysis techniques for passive and active
frequency multipliers are similar, the author refers fur-
ther discussion on this topic to a later section, where a
detailed discussion is presented on the analysis techniques
mentioned above. The nal section of this article deals
with active frequency multipliers, but the analysis tech-
niques are applicable for passive nonlinear devices as well.
2.8. Pertinent Properties of Passive Devices
The RF performance of passive multipliers is governed by,
among other things, the pertinent properties of the non-
linear device. These properties can be divided into two
categories [41]: (1) those affecting the efciency of the
multiplier and (2) those affecting its power-handling ca-
pability. Tolmunen [41] notes that the efciency of the
nonlinear diode is affected mostly by the cutoff frequency,
which will be dened below, the strength of the nonlin-
earity, and the type of multiplication (resistive or reactive,
as discussed in Section 2.1>. The power-handling capabil-
ity is affected by the device area, the extent of the nonlin-
earity, and the breakdown voltage, which was discussed in
Section 2.3.1).
Focusing on varactor frequency multipliers, for efcient
varactor operation, it is necessary, as expected, for the re-
actance of the junction capacitance of the varactor to be
much larger than the device series resistance (R
s
in Fig. 8)
[17]. Therefore, this necessitates an upper frequency limit
(cutoff frequency) on the usefulness of a given varactor
[18]. The dynamic cutoff frequency is dened as [41]
f
cd
1=C
min
1=C
max
2pR
s
54
where C
min
and C
max
are the minimum and the maximum
capacitance of the varactor and R
s
is the diode series re-
sistance. Therefore, for optimum performance, the cutoff
frequency should be greater than the frequency of appli-
cation.
A sharp nonlinearity in the CV response of the varac-
tor results in efcient harmonic generation, since the non-
linearity of the device is responsible for harmonic
generation. The advantages of a sharp or steep nonlinear-
ity depend on the extent of the voltage swing across the
diode generated by the input power. Varactors have high
input impedance, thus enabling large voltage swings to be
generated across the device. A diode with high nonlinear-
ity, even at low input power levels, produces significant
voltage swings, and therefore is capable of achieving op-
timum performance. Typically, the optimum conditions
occur in applications where the nonlinearity extends
over voltages comparable to the voltage swing of the in-
put power signal.
Tolmunen [41] states that the power-handling capabil-
ity is proportional to the average capacitance of the device
area. As in the case of other high-power devices, diodes
with large surface areas are able to handle larger input
power levels and consequently produce larger RF current.
In practical diode applications, however, this may result in
matching problems, because matching the diode over a
broad voltage range is quite challenging, and thus trade-
offs have to be made. As will be shown in the discussion of
design techniques in the last section, another approach
commonly used to improve the power-handling capability
is to stack devices in series or parallel. This conguration
increases the total area of the diode, thus allowing it to
sustain larger voltage swings. Large device arrays are
useful in high-power applications.
2.9. Classical Realizations
The previous sections highlighted some of the basic
properties of passive multipliers and the fundamental
characteristics of nonlinear components, which are uti-
lized extensively in passive multiplier development. As
mentioned, the nonlinear component is embedded in ex-
ternal circuitry to accentuate the desired harmonic. As
seen throughout the literature, various topologies exist for
realizing passive multipliers, revealing the interaction be-
tween the embedding circuitry and the nonlinear device.
This section will highlight some of the classical realiza-
tions utilized extensively by microwave designers and
researchers.
Scanlan [18] and Leeson and Weinreb [20] have pre-
sented some simple, classical realizations for passive mul-
tipliers, as shown in Figs. 11 and 12. Scanlan identies the
passive multiplier topology shown in Fig. 11 as a series
model where the varactor diode is series-mounted with the
embedding network. The input and output networks F
1
and F
N
, respectively, represent ideal lters at the funda-
mental frequency and the Nth harmonic, which permit
voltages to exist at the fundamental frequency and the
Nth harmonic, respectively.
In other words, F
1
acts to short-circuit all frequencies
other than the fundamental frequency, and F
N
acts to
short-circuit all frequencies other than the harmonic fre-
quency of interest. Although more sophisticated lters
may be required, parallel LC networks can be synthesized
for F
1
1 and F
N
at their respective frequencies, as shown by
o
0
LC
p 55
Figure 12, on the other hand, shows the shunt diode to-
pology for passive frequency multiplier design using
a nonlinear diode. Again, the input and output networks,
F
1
and F
N
, respectively, represent ideal lters at the
F
1
Y
g
I
g
F
N
Y
L
Figure 11. Series-mounted passive diode frequency multiplier.
F
1
F
N
R
L
R
g
E
g
Figure 12. Shunt-mounted passive diode frequency multiplier.
Z
in
Z
g
Z
L
Z
1
Z
0
E
g
Z
d in
Z
d out
Z
out
Input
filtering
and
matching
network
Output
filtering
and
matching
network
Figure 13. Block diagram of series-mounted diode frequency
multiplier.
fundamental frequency and the Nth harmonic, which per-
mit currents to ow at the fundamental frequency and the
Nth harmonic, respectively. This indicates that F
1
acts to
open-circuit all frequencies other than the fundamental
frequency and F
N
acts to open-circuit all frequencies other
than the harmonic frequency of interest. Similarly, F
1
and
F
N
can be synthesized as series LC networks resonant at
the fundamental frequency and the output harmonic fre-
quency of interest.
Faber (13) has discussed the realizations presented by
Scanlan, with emphasis on achieving optimum efciency
of the multiplier. Block diagrams of the realizations (se-
ries-mounted and shunt-mounted) shown by Faber are
given in Figs. 13 and 14. Recall from the Section 2.4 that
the ManleyRowe power equations imply that it is theo-
retically possible to deliver all input power at the funda-
mental frequency to the output load at the desired
harmonic of interest, thereby achieving 100% efciency.
Achieving optimum efciency requires that should not be
dissipated at any of the undesired harmonics in either the
input network or the output network.
This indicates, with regard to Fig. 13, that
Re Z
d; out
f % 0 56
Re Z
d; in
nf % 0 57
when the input and output networks contribute to the de-
vice reactance compensation. If the conditions represented
by Eqs. (56) and (57) are met, power is not dissipated at
the fundamental frequency in the output network and
power is not dissipated at any of the harmonic frequencies
in the input network, respectively.
Similarly, for Fig. 14 the following conditions are
sought:
ReY
d; out
f % 0 58
ReY
d; in
nf % 0 59
Apart from the realizations mentioned previously, several
variations of these topologies have been utilized as well.
At RF and microwave frequencies several diodes connect-
ed in series or parallel have been utilized to handle cases
where there was insufcient power, voltage, or current-
handling capability of a single device or where the single-
device impedance levels were inconvenient. Connecting m
diodes in series (stacking) produces a breakdown voltage
m times as high, and m diodes in parallel provide m times
higher current [13]. Therefore, topologies such as those
shown in Figs. 15 and 16 are commonly encountered.
The circuit complexity of passive multipliers can be in-
creased even further. Some more complicated topologies
are shown in Figs. 1720 [13,17,18,30]. The antiparallel
topology of Fig. 17 produces currents containing compo-
nents at the fundamental frequency and higher odd-order
harmonics. This can substantially simplify the design of
input and output lters in the development of odd-order
multipliers.
Figure 18 shows the antiseries topology utilizing a
transformer between the input signal and the diode cir-
cuit. The transformer provides a 1801 phase shift between
the input signal voltages feeding the two diodes. There-
fore, the current components cancel in the load, producing
no voltage across the load at the fundamental frequency.
In contrast to the antiparallel topology, the antiseries to-
pology provides even-order harmonics and therefore leads
to less stringent requirements on the input and output
lters.
Figure 19 utilizes a transformer in the antiparallel se-
ries topology as well. Faber notes that the odd-order com-
ponents are in phase, so that when the odd-order
components ow through the transformer primary wind-
ing, they do not excite the load mesh. The even-order
components, on the other hand, are of opposite phase, so
they cancel in the input signal source branch but excite
current in the load mesh. This action causes the antipar-
allel series topology to produce even-order harmonic mul-
tiplication.
Z
in
Z
g
Z
L
Z
1
Z
0
E
g
Z
d in
Z
d out Z
out
Input
filtering
and
matching
network
Output
filtering
and
matching
network
Figure 14. Block diagram of shunt-mounted diode frequency
multiplier.
Z
g
Z
L
E
g
Figure 15. Series-connected diode multiplier topology.
Y
g
Y
L
I
g
Figure 16. Parallel-connected diode multiplier topology.
Y
g
Y
L
I
g
Figure 17. Antiparallel diode pairs.
Finally, Fig. 20 shows a bridge frequency multiplier.
Similarly to full-wave rectiers, bridge rectiers can be
used to produce even-order harmonic multiplication.
2.10. Passive Multiplier Design Techniques
2.10.1. Existing Design Techniques. Numerous tech-
niques exist for the design of passive multipliers utilizing
various topologies, many of which are presented in Section
2. This section presents, in perusal of the available liter-
ature, various existing design techniques, and in some
cases details their performance.
A fundamental topological representation for realiza-
tion of passive RF/microwave multiplier circuits is shown
in Fig. 21, where networks N
1
and N
2
are on the input and
output of the nonlinear device, respectively. As mentioned
in a previous section, multiplier performance is governed
by the embedding circuitry (networks N
1
and N
2
) and the
pertinent properties of the nonlinear device. Authors have
used various networks in the synthesis of N
1
and N
2
. Tra-
ditional synthesis have included short-circuited and open-
circuited stubs at the fundamental frequency and various
harmonics [16,24,25], impedance matching and lter
networks [15,2629], and waveguides and lters [11,14,
3133,3640].
As shown in Fig. 21, in the synthesis of N
1
and N
2
,
several authors have utilized short-circuited and open-cir-
cuited stubs for low-frequency and high-frequency appli-
cations. Gavan and Peled [16], for example, use microstrip
stubs in the development of a 12502500-MHz step recov-
ery diode frequency doubler. They synthesize N
1
with a 0/8
stub (at 2f
0
) on the input network to provide a short circuit
for the second-harmonic signal, and synthesize N
2
with a
0/4 microstrip stub (at f
0
), which provides a short circuit to
ground for the fundamental frequency. Using this design
technique, they achieve conversion gain efciency of 75%,
but do not present any data on harmonic suppression.
Chen et al. [24,25] perform a 4794-GHz Schottky barrier
varactor diode frequency doubler design utilizing MMIC
technology. They use a 0/2 short-circuited stub (at 2f
0
) on
the input network to create an RF short circuit at 94 GHz,
and a 0/4 short-circuited stub (at f
0
) on the output to create
an RF short circuit at the fundamental frequency. This
high-frequency MMIC design provided a maximum con-
version efciency of 25% (6 dB conversion loss).
Several authors have developed passive frequency mul-
tipliers utilizing impedance-matching networks and l-
ters in the input and output networks [15,2629]. The
impedance-matching networks are employed to match the
input and output impedances of the nonlinear device,
while the lters are used to attenuate specific harmonics.
Gavan and Peled [15] designed a 12502500-MHz varactor
frequency doubler utilizing the shunt varactor topology
shown in Fig. 14 along with a lowpass lter in the input
network and a two-section coupled bandpass lter at
2500 MHz in the output network. This design technique
yields a maximum conversion gain efciency of 71%.
Chang et al. [29] developed a varactor 4692-GHz fre-
quency doubler utilizing a topology similar to that shown
in Fig. 14. Input and output networks are synthesized
with lters and additional matching networks to achieve
optimum power transfer at the source and load. This de-
sign achieves a conversion loss of 89 dB over a 500MHz
bandwidth.
Furthermore, some authors have chosen to utilize a
balanced topology for the design of frequency multipliers
[3033]. A block diagram of a balanced design topology is
shown in Fig. 22. In typical balanced circuits, a 1801 phase
difference in the input signals feeding the nonlinear device
produces fundamental signals and other odd-harmonic
signals with opposite phase. By destructive interference,
the fundamental and other odd harmonics cancel, giving
good harmonic suppression, while the second-harmonic
signals, on the other hand, interfere constructively, there-
by enhancing the output signal at the second-harmonic.
This design technique will be revisited in the discussion of
active frequency multipliers.
Z
g
Z
L
E
g
+
Figure 18. Antiseries diode pairs.

E
g
Z
L
Z
g
+
Figure 19. Antiparallel series-connected diodes.

Z
L
Z
g
E
g
Figure 20. Bridge frequency multiplier.
Z
g
E
g
N
1
N
2
Z
L
Passive
nonlinear
device
Figure 21. Passive frequency multiplier realization.
Bitzer [30] utilized a balanced topology similar to that
shown in Fig. 19 and presented again in Fig. 23 to design a
broadband Schottky barrier diode frequency doubler. In
this structure, the input signal is fed antiphase to the di-
odes in order to switch on one diode patch every half-cycle.
The rectied output signal is coupled to the load via a
balun. As mentioned previously, the fundamental signals
and other odd-harmonic signals from the diodes have op-
posite phase and therefore, by destructive interference,
cancel, giving good harmonic suppression. The second-
harmonic signals interfere constructively, thereby en-
hancing the output signal at the second-harmonic.
Bitzers data show that from 618 GHz, the conversion
loss is 9.571dB and harmonic suppression 415 dBc.
Archer [33] developed a balanced varactor diode
85116-GHz frequency doubler similar to the typical to-
pology shown in Fig. 22. Archer uses a waveguide T junc-
tion as a power divider on the input to feed two varactor
diodes. On the output, a matched waveguide hybrid T
junction combines the power at the output port. Using this
design topology, a maximum conversion efciency of 16.5%
was achieved. Unfortunately, Archer does not present any
data on harmonic suppression.
Waveguide circuitry provides an efcient means of re-
alizing frequency multipliers [14]. Waveguides provide
low loss, possess desirable highpass lter characteristics,
and provide a good thermal path for dissipated power.
Energy is typically coupled/decoupled from the input and
output of the waveguide through a lowpass lter. Various
authors have utilized waveguide circuitry in high-fre-
quency multiplier designs [11,14,3133,3640]. Raisanen
[36] notes that for frequencies from 100B500GHz, for ex-
ample, the highest efciencies and highest output powers
have been achieved with waveguide multipliers.
Archer [38] has developed a varactor frequency doubler
at 260GHz utilizing waveguides and lters. The input
network consists of a lowpass lter and a waveguide. The
lowpass lter is a seven-section design that passes the
fundamental signal while attenuating higher-order har-
monics. The output network consists of a l
0
/4 impedance
transformer and a waveguide. Using this design tech-
nique, Archer achieves a conversion gain efciency of
20% for narrowband applications (5% bandwidth) and
conversion efciencies of 10% for wider-band applications
(8% bandwidth).
Mott [11] has developed a varactor frequency doubler
design at a lower frequency (1938 GHz), utilizing wave-
guides as well. Mott synthesized the input network with a
waveguide, a l
0
/4 impedance transformer, and a lowpass
lter and notes that the characteristic impedance of the
lter is synthesized so that it equals the real part of the
diode input impedance. The output network consists of an
output waveguide impedance transformer synthesized to
present the optimum load impedance to the output of the
diode. Mott achieves a conversion efciency of 60% (con-
version loss of 2.2 dB) over a 1 dB output bandwidth of
640 MHz.
At higher frequencies, frequency multipliers are capa-
ble of achieving high conversion efciency at low input
powers, but the output power tends to saturate at rather
low power levels [31]. The use of series arrays of diodes
provides an attractive approach to overcoming this defect.
Cascading multiple-diode junctions increases the beak-
down voltage and provides greater power-handling capa-
bility [9]. A series array of n identical diodes can handle n
2
times as much power as a single diode [31]. For these rea-
sons, various authors have utilized series- and parallel-
stacked diodes in passive design, as shown in Figs. 15 and
16, to improve the power-handling capability of passive
frequency multipliers [9,14,30,31,34,35]. Chu [34] devel-
oped an 1836-GHz stacked-diode frequency doubler uti-
lizing two series diodes. The input/output-matching
circuits consist of l
0
=4 impedance transformer sections
with open-circuited stubs resonant at the input and out-
put frequencies. This design produced a maximum output
power of 150mW with a conversion efciency of 24%, and
a peak conversion efciency of 35% at 95 mW of output
power.
2.10.2. State of the Art. In the development of passive
frequency multipliers as well as other technologies, re-
searchers and designers are constantly pushing the lead-
ing edge in attempts to achieve better performance. In
passive frequency multipliers, designers desire, among
other things, greater power-handling capability and great-
er conversion gain efciency. This section highlights state-
of-the-art developments in passive frequency designs.
The available literature indicates that the leading edge
of technology in passive designs is not focused so much on
developing new design topologies as on new methods of
fabricating new semiconductor diodes, particularly for
millimeter and submillimeter-wavelength applications
[25,36,39,41]. It has been demonstrated that the perfor-
mance of passive frequency multipliers is highly depen-
dent on the pertinent properties of the nonlinear device.
+
Z
g
Z
L
E
g
Figure 23. Antiparallel balanced diode conguration.
Passive
nonlinear
device
Passive
nonlinear
device
Combiner (2) (1)
Phase-shifter-
power splitter
Figure 22. Block diagram of typical passive balanced frequency
multiplier.
Therefore, it is reasonable to expect that efforts at improv-
ing the performance of passive frequency multipliers
would begin with the nonlinear device.
Over the years, the GaAs Schottky varactor diode has
served as one of the most important nonlinear elements
for frequency multipliers [36,41]. Consequently, growing
interest in novel diodes has brought to light new struc-
tures showing excellent theoretical performance compa-
rable to or better than the conventional Schottky varactor.
In comparison with the Schottky varactor, these new di-
odes have potential advantages, such as stronger nonlin-
earity or a special symmetry, which make them very
attractive for millimeter and submillimeter-wave frequen-
cy multiplication. Stronger nonlinearities allow more ef-
cient higher-order harmonic generation with smaller
input signal levels [36]. These novel diodes include sin-
gle-barrier varactors (SBVs), quantum barrier varactors
(QBVs), barrierintrinsicn
(BIN) diodes, and high-elec-

tron-mobility varactors (HEMVs).
The quantum well diode (QWD) has been studied since
1970 [41]. The QWD is a heterojunction diode in which a
thin undoped layer between two thin barriers forms the
quantum well. Its high speed and negative differential re-
sistance make it attractive for millimeter-wave oscillators.
Because of its symmetric structure, the highly nonlinear
antisymmetric IV curves and symmetric CV character-
istics result in odd-harmonic generation. Therefore, as ex-
pected, QWDs have been utilized in tripler designs, with
some designs going up to 200GHz. Raisanen [36] notes
that the resulting output powers from these tripler de-
signs are promising, but are lower than those achieved
from the best Schottky multipliers. Replacing the quan-
tum well with a single thicker barrier produces a QBVor a
SBV, where the nonlinear current is suppressed but the
nonlinear CV characteristic remains. Because the of sym-
metric CV characteristic, this diode is also attractive for
tripler and quintupler design. SBV triplers have been de-
veloped up to 280GHz, producing output powers of
2.5 mW [36].
The BIN diode has been proposed as an improved diode
for harmonic generation [41]. Unlike QWDs or SBVs,
which consist of a heterostructure and two ohmic contacts
as terminals, the BIN diode is essentially a Schottky var-
actor with an unique doping prole that yields a sharper
CV characteristic than the Schottky varactor. The BIN
diode consists of a Schottky contact, a barrier layer, and an
intrinsic layer. Tolmunen [41] notes that connecting two
BIN diodes back to back produces a symmetric CV char-
acteristic.
The HEMV is a modication of the planar Schottky
varactor where a heterostructure is used. The electrons in
this device have higher mobility, as in HEMTs (which are
modeled and used in active multiplier designs in the nal
section), thus making it attractive for high-frequency ap-
plications. In a varactor, this structure produces a strong-
ly nonlinear capacitance, but with an undesirable high
parasitic capacitance associated with its structure.
Tolmunen [41] has designed several multipliers utiliz-
ing the abovementioned novel devices at 200GHz. The
conclusions from his study reveal that the sharp CV
characteristic of the BIN diodes improves the performance
at low input powers (10 mW) and makes them the most
effective of all the devices. The SBV yields excellent the-
oretical performance, but is less efcient because of its
high resistive losses. It does however, provide the best
performance at high input power levels.
As researchers and designers continue to push the en-
velope of technology for higher-performance devices, these
novel devices will be utilized extensively, particularly at
submillimeter and millimeter frequencies.
3. ACTIVE FREQUENCY MULTIPLIERS
Another class of frequency multipliers encompasses those
that are designed and constructed utilizing active nonlin-
ear devices. As discussed earlier, multipliers require a
nonlinear element for harmonic production [133135].
Active frequency multipliers, as shown in the block dia-
gram in Fig. 24, utilize the nonlinear characteristics of an
active element properly biased to produce an output spec-
trum rich in harmonics when excited by a sinusoidal
source. Typically, the active element consists of any of
the transistor classes, which include the BJT, HBT, eld-
effect transistor (FET), MESFET, HEMT, and PHEMT.
Active multipliers offer various advantages over their
passive counterparts. An example, which will be discussed
in the following section, is in the conversion gain. Active
multipliers are capable of producing conversion gains
greater than 0 dB, whereas passive multipliers are not.
This section will also discuss the development of active
frequency multiplier technology, including the fundamen-
tal performance descriptions, and pertinent properties of
the active device (which include modeling and quantica-
tion of the nonlinear properties). Design techniques of ac-
tive frequency multipliers are discussed in Section 4.1.
In the systematic design of any linear microwave am-
plier, an essential initial step in modern engineering
practice, is the computer analysis of the proposed topolo-
gy utilizing such tools as the HP/Agilent ADS simulator.
An essential ingredient in this process is the use of real-
istic circuit models, some of which have required many
worker-hours of development as exemplied by the micro-
stripline models in that simulator. Simultaneously, real-
istic models of the transistor (FET, HEMT, HBT, etc.) are
utilized. This model may be in the form of a physical
model, measured S-parameter data, or an empirical mod-
el. In any case, some reasonable active device representa-
tion is used.
Such has not been the case for active microwave fre-
quency multipliers until quite recently. These recent com-
puter-based designs will be described in Section 4.2.
R
g
R
L
Input
network
Output
network
Active
nonlinear
device
E
g
Figure 24. Block diagram of active frequency multiplier.
Numerous authors have presented discussions of active
frequency multipliers that will be referenced throughout
this presentation. A systematic design approach for devel-
opment of active frequency multipliers, which is analo-
gous to that for linear ampliers, utilizes computer-based
simulation. As a result, one of the primary concerns is the
ability to accurately predict the linear and nonlinear per-
formance of the active device before embedding it into
other networks, which is typical in the development
and design of frequency multipliers. Several authors
[4886,129,158163] have presented details and tech-
niques for modeling the active devices. Each author de-
lineates the various advantages and disadvantage of their
study. Techniques for modeling HEMTs are presented as
an example in this discussion, since they are employed in
the illustrative multiplier designs in later sections.
3.1. Fundamental Performance Descriptions
As discussed previously, frequency multipliers are nonlin-
ear circuits that convert signals at an input fundamental
frequency (f
0
) into signals at a harmonic frequency mul-
tiple of the input frequency (nf
0
). Several performance de-
scriptions and parameters represent the effectiveness of
frequency multipliers for frequency conversion. The ob-
jective of this section is to identify and discuss the prom-
inent fundamental performance descriptions of active
frequency multipliers.
Active frequency multipliers utilize the nonlinear char-
acteristics possessed by any of the several properly biased
transistor classes (BJT, FET, etc.). Exciting the nonlinear
device with a fundamental frequency provides an output
spectrum rich in frequency harmonics. One of the main
advantages of active multipliers is their capability of pro-
ducing positive conversion gains (conversion gains greater
than 0 dB). The conversion gain of a frequency multiplier
is dened as the ratio of the output power for a particular
harmonic delivered to the load to the fundamental input
power. Maximizing the conversion gain is crucial in the
development and design of frequency multipliers. In the
specific case of frequency doublers, an input signal at the
fundamental frequency (f
0
) is converted into a signal at
the second-harmonic (2f
0
). Mathematically, the conversion
gain can be expressed as [87]
Conversion gain
P
out
2f
0
P
in
f
0
60
or
Conversion gain dB P
out;2 f
0
dBm P
in; f
0
dBm 61
Frequency doublers, which will be presented in the next
section, have been designed and developed exhibiting con-
version gains approaching 12dB. Alternatively, the con-
version gain can be expressed as a percentage [88]. This
percentage is dened as the ratio of the input power at the
fundamental to the output power delivered to the load at
the desired harmonic. Using the example of the frequency
doubler, this can be represented as
Z
P
in
f
0
P
out
2f
0
100% 62
Similarly, as in the consideration of RF ampliers, the ef-
fectiveness of the conversion of DC power into AC power is
also a meaningful parameter in discussing frequency mul-
tipliers. In the case of frequency doublers, the consider-
ation is focused on the effectiveness of converting DC
power into AC power at the second-harmonic. A general
expression for the DC-to-RF efciency can be represented
as [88]
DC to RF
P
out
harmonic
P
DC
100% 63
From this equation, it is observed that optimum DC-to-RF
efciency performance is achieved when maximum RF
power is produced from minimum DC power. For the class
of frequency multipliers presented in the next subsection,
DC-to-RF efciencies of up to 24% have been obtained.
The transfer of power from the fundamental frequency
at the generator to the desired harmonic at the load is
dependent, amongst other things, on the return loss or
voltage standing-wave ratio (VSWR) of the input port and
the output port of the multiplier circuitry. The return loss
is a measure of the impedance match of the input and
output ports of the frequency multiplier to the source im-
pedance and the load impedance. Computer simulations
for HEMT frequency doublers are performed in Section
3.4.3. (see Tables 3 and 4) delineating the advantages of
good impedance matching. In these simulations signi-
cant improvements in the conversion gain are achieved in
the cases where the input and output ports are imped-
ance-matched.
As discussed previously, frequency multipliers are har-
monic generators that produce an output harmonic (nf
0
)
when excited by a fundamental frequency (f
0
). In the gen-
eration of the desired harmonic, undesired harmonics are
generated as well. As an example, in the case of a fre-
quency doubler, the desired output harmonic is 2f
0
, but
other harmonics at f
0
, 3f
0
, 4f
0
, are generated. The ability of
the multiplier to suppress the undesired harmonics is an-
other key performance factor. This property of the fre-
quency multiplier is called harmonic suppression. It is
dened mathematically as
Suppression
mf
0
dBc P
0nf
0
dBm P
0mf
0
dBm 64
where nf
0
is the desired frequency harmonic and mf
0
is an
undesired harmonic. In the case of the frequency doubler,
n2 and m1,3,4, which indicates that the desired har-
monic is 2f
0
and harmonic suppression is calculated for
the fundamental frequency (f
0
), third-harmonic frequency
(3f
0
), and so on.
A previously discussed application of frequency multi-
pliers is their use in communication systems in receivers
and transmitters. A performance description of receivers
in communication systems, and therefore of frequency
multipliers used in receivers, is their dynamic range, de-
ned as the range of input or output power levels where
signals can be processed with high quality without signal
distortion. At low power levels, the dynamic range is lim-
ited by the sensitivity to the noise oor or the minimum
detectable signal as governed by the noise oor. At higher
powers, the dynamic range is limited by the acceptable
level of signal distortion or, specifically, by the power level
where the small-signal gain has been compressed by 1dB
[89,90].
Using these definitions for the dynamic range, the
optimum dynamic range for frequency multipliers is
achieved when the power range between the noise oor
and signal distortion is maximized. It involves tradeoffs
between the input signal drive level, the noise oor level,
and the output signal distortion.
Another important multiplier performance parameter
is the operational bandwidth. Bandwidth is dened as the
frequency band where specific performance specications
are met; typically, one uses the conversion gain. Specifying
a 3 dB bandwidth indicates the frequency band where
the conversion gain decreases by 3 dB from its peak. Op-
timizing multiplier bandwidth is an important task to the
designer. Typically, tradeoffs have to be made in the per-
formance of the devices to achieve high bandwidths. As an
example, higher conversion gains are achieved for narrow-
bandwidth designs, and usually wide-bandwidth designs
are accomplished at the expense of the conversion gain.
One explanation for this is the difculty of achieving im-
pedance matching over broad ranges. Consequently, the
conversion gain is reduced over the band to compensate
for the extended bandwidth. Over narrow frequency bands
impedance matching is less of a challenge and thus readily
facilitates optimization of conversion gain.
3.2. Pertinent Properties of the Active Device
3.2.1. Nonlinear Modeling. As pointed out previously,
accurate device models are an essential ingredient for the
efcient design of active microwave multipliers. This sec-
tion presents typical information on active devices neces-
sary in active multiplier design. Since most of the effort on
active multipliers employs FET-type devices, the remain-
ing portions of this presentation will stress this class of
active elements. Some multiplier realizations utilizing
Bipolar devices are addressed in Ref. 95,155,156, and 164.
3.2.2. Classication of Device Models. Active-device cir-
cuit models are developed and categorized according to
their specific applications. Depending on this classica-
tion, a specific model is typically employed, such as small-
signal models and S-parameter data for small-signal
amplier applications.
Alternatively, for frequency multiplier applications, ex-
cellent nonlinear models are required to predict both the
linear and nonlinear device performances.
The development of such models is a challenging un-
dertaking that requires more depth in its exposition than
space permits. The interested reader is referred to the lit-
erature [4978] and [158163] for in-depth treatment of
this topic.
3.2.3. Development of Precision Models. Because of the
necessity of precision nonlinear models for illustration of
accurate multiplier designs, we will utilize a high-elec-
tron-mobility transistor manufactured by Fujitsu
(FHX35LG) for that purpose.
Additionally, the frequency multiplier examples illus-
trated below are doublers, and thus, the highest frequency
harmonic that will be modeled is the third harmonic. Fur-
thermore, it has been pointed out in these applications,
that the rst three harmonics are of the greatest signi-
cance [99].
A number of authors [4878] have developed nonlinear
active-device models that are typically employable in ac-
tive multiplier development. The interested reader is re-
ferred to Refs. 49 and 56 for in-depth discussion of most of
these models.
For the purposes of our discussion, a general nonlinear
FET/HEMT model is shown in Fig. 25. In this model, the
nonlinear parameters include the following [49]:
D
gs
gate-to-source diode
D
gd
gate-to-drain diode
C
gs
gate-to-source capacitance
C
gd
gate-to-drain capacitance
C
ds
drain-to-source capacitance
I
ds
drain-to-source current
R
ds
output resistance
@I
ds
@V
gs
_ _
1
g
m
transconductance (not shown in model but is repre-
sented by the equation: g
m
@I
ds
/@V
gs
)
In-depth discussions of these parameters and their device
design implications are presented in Refs. 49 and 56.
3.3. Device Nonlinearities
It was discussed above that while the class of active
devices available for multiplier applications includes
BJT, MESFET, HEMT, and similar devices, this work
will employ HEMT transistors as a vehicle for design
illustrations.
The equivalent circuit for this device was shown in
Fig. 25 with the nonlinear elements displayed that are
exploited in the generation of frequency harmonics.
3.3.1. Analysis of Nonlinearities. In analyzing FET/
HEMT performance, several authors have addressed
the issue of identifying the elements that contribute to
the nonlinear behavior of FET transistors [49,75,76,79,
86,93,97,98,101]. Maas [86] has analyzed the nonlinear
behavior of MESFET transistors. In his study, Maas pro-
vided the magnitude of all parasitic components (L
s
, L
g
,
L
d
, R
g
, and R
d
) and intrinsic components (R
i
, R
ds
, C
gs
, C
gd
,
and g
m
) in tabular form for various bias voltages. This
provides insight into the nonlinear behavior of these com-
ponents. R
i
(not shown in Fig. 25) is the charging resis-
tance in series with C
gs
for a typical transistor. Maas data
for the parasitic inductors (L
s
, L
g
, and L
d
) show that the
magnitudes of these inductors are very small and are on
the order of hundredths of nH. Their values vary from 0.03
to 0.08 nH for L
s
, from 0.09 to 0.12 for L
g
, and 0.06 to
0.07 nH for L
d
or, in the worst case, their magnitudes
vary by only 0.05 nH over the bias ranges. This
indicates that at an arbitrary frequency of 1 GHz, the im-
pedance of this inductance variation is approximately
0.25. This implies that the parasitic inductors can be ap-
proximated with xed, constant values for all bias regions
and, therefore, do not contribute as a source of nonlinear-
ity to the MESFET. The magnitude of the parasitic resis-
tors (R
g
, R
s
, and R
d
) vary by only a few tenths of an ohm as
functions of applied voltage. Therefore, similar to the par-
asitic inductors, their magnitudes can be xed as con-
stants in the device models.
Maas data show that the output resistance of the ME-
SFET varies nonlinearly over bias from approximately 10
to 283 [86].
This variation is significant and indicates that, as a
result of this nonlinear characteristic, the output resis-
tance of the transistor is one of the potential contributors
to the nonlinear effects observed in the MESFET transis-
tor. The gate-to-source and gate-to-drain capacitors (C
gs
and C
gd
) also vary nonlinearly as functions of applied volt-
age. C
gs
is shown to vary from 0.415 to 0.636 pF, and C
gd
varies from 0.049 to 0.266 pF. This nonlinear variation in
C
gs
and C
gd
indicates that they are viable contributors to
the harmonic production of the MESFETas well. The nal
element considered by Maas is the transconductance. The
transconductance shows significant nonlinear variation
over bias, particularly in the saturation region as it varies
nonlinearly from 61.3 to 89.2 mS. This nonlinear variation
indicates that it also contributes to the nonlinear behavior
of the MESFET. In summary, Maas study reveals that the
elements significantly contributing to the nonlinear be-
havior of the MESFET are R
ds
, C
gs
, C
gd
, and g
m
. The re-
maining elements (L
s
, L
g
, L
d
, R
i
, R
g
, R
s
, and R
d
) do not
vary nonlinearly and can be considered to be constants in
the models. Maas study was performed on a MESFET;
however, his results can be employed in identifying the
nonlinear contributors to HEMT/PHEMT performance as
well.
Gopinath and Rankin [79,119] have performed a study
identifying the relative contributions of the various non-
linear elements of MESFETs valuable for harmonic gen-
eration. Their work emphasizes harmonic generation at
the second-harmonic using computer simulations and
identies the major contributors to the nonlinear behav-
ior of the MEFSET as (1) C
gs
and C
gd
; (2) drain current
nonlinearity, which results from the drain current clip-
ping when V
gs
swings below pinchoff or into forward con-
duction; (3) the nonlinearity of the drain current equation
representing I
ds
; and (4) output resistance nonlinearity.
On the basis of computer analysis, Gopinath and Ran-
kin conclude that, in the absence of other nonlinear con-
tributions, the second-harmonic power level due to C
gs
is
on the order of 1811 dB below the output power at the
fundamental. In evaluating the effect of I
ds
clipping, they
neglect the transfer characteristic of I
ds
and perform a
Fourier analysis of the half-wave rectied waveform with
V
gs
0 V. They nd that the second-harmonic output pow-
er level is 7.4 dB below the output power level at the fun-
damental. Gopinath and Rankin analyze the nonlinear
contributions from the I
ds
current equation nonlinearity
and the output resistance by simulating the harmonic re-
sponse of the FET with the drain current represented by
Eqs. (65) and (66), respectively. The simulations show that
the second-harmonic output power level is 16 dB below the
output power level at the fundamental using Eq. (65) to
represent I
ds
, and that the second-harmonic output power
level is 15 dB below the output power level at the funda-
mental when using Eq. (66) to represent I
ds
:
I
ds
I
dss
1
V
gs
V
p
_ _
2
65
I
ds
I
dss
1
V
gs
V
p
_ _
2
1
V
ds
R
do
I
dss
_ _
66
The conclusion is that the major contributor to the non-
linearity of the FET is the I
ds
nonlinear clipping effect,
which produced second-harmonic output power 7.4dB be-
low the output power at the fundamental. Slight contri-
butions to the nonlinearity of the FET came from the C
gs
nonlinearity, output conductance nonlinearity, and I
ds
transfer nonlinearity. It should be noted, however, that
the study uses approximations in the computer simula-
tions. The computer model neglects the gate-to-drain
branch of the circuit (C
gd
and D
gd
), the authors use a pre-
determined unknown resistive load (R
L
), and they indi-
cate that the results are valid only for R
L
5R
do
, where R
do
is the output resistance. A nal observation of this study is
that measured data indicating the accuracy and practi-
cality of the results are not presented.
With reference to the earlier work of Camargo [98],
Dow [97] discusses the nonlinear contributions of the ME-
SFET transistor using a graphical approach. He develops
an equivalent-circuit model from measured S parameters
to evaluate the bias-dependent nonlinear intrinsic circuit
elements, and, afterward, presents curves representing
g
m
, C
gs
, and G
ds
versus V
gs
and V
ds
to show the nonlinear
behavior of these parameters. Examining the curves, Dow
identies particular bias regions of V
gs
and V
ds
, where the
nonlinear variation of g
m
and G
ds
is more prominent and
significant for harmonic generation. With regard to the
contribution from C
gs
, Dow references the study per-
formed by Gopinath and Rankin, as previously discussed,
D
gd
R
g
D
gs
R
s
L
s
C
gs
C
ds
V
gs
V
ds
C
gd
R
d
Source
Drain
L
d I
ds
(V
gs
,V
ds
)
L
g
Gate
Figure 25. Nonlinear device equivalent circuit model.
in stating that second-harmonic generation is weakly de-
pendent on C
gs
nonlinearity. In summary, Dows study
concludes that harmonic generation is obtained from three
sources of the MESFET: (1) nonlinearity of the intrinsic
parameters C
gs
, g
m
, and G
ds
; (2) current rectication,
which occurs when the gate voltage swings into forward
conduction; and (3) current clipping occurring when the
gate voltage swings below pinchoff.
The previous discussions have stressed the determina-
tion of the nonlinear elements responsible for harmonic
generation in MESFETs. Focusing on the HEMT transis-
tor, Golio [49] indicates that the major nonlinear elements
of the HEMT device are (1) the drain-to-source current I
ds
,
from which the transconductance and output conductance
are derived; (2) the gate-to-source and gate-to-drain ca-
pacitors (C
gs
and C
gd
); and (3) the gate-to-source and gate-
to-drain diodes (D
gs
and D
gd
).
3.3.2. HEMT Characteristics. Modeled drain-to-source
current, transconductance, and output conductance data
for a Fujitsu FHX35LG HEMT are shown below to dem-
onstrate the nonlinear characteristics of these types of ac-
tive devices. Static IV curves are shown in Figs. 26 and 27
for the transistor using the modeling techniques previous-
ly discussed and the equivalent nonlinear model shown in
Fig. 28. From the static IV curves, the transconductance
and output conductance are derived and plotted against
the drain-to-source (V
ds
) and gate-to-source (V
gs
) voltages
as shown in Figs. 2932. These plots graphically display
the nonlinearity of the transconductance and output con-
ductance of the HEMT transistor as functions of the DC
bias voltages. As shown in these plots, these elements
show varying degrees of nonlinearity, which are depen-
dent on the drain-to-source (V
ds
) and gate-to-source (V
gs
)
voltages bias. The exploitation of these nonlinearities with
respect to the optimum bias conditions will be discussed in
the following section.
3.4. Nonlinearities Utilized for Frequency Multiplication
The preceding sections presented a general synopsis of
device nonlinearities. This section delineates the nonlin-
earities of specific importance for frequency multiplication
applications, given certain optimum bias conditions. Ad-
ditionally, the impact of terminating impedances on mul-
tiplier performance is detailed.
3.4.1. Optimum Bias Selection. Golio [49] has noted
that the drain-to-source current (I
ds
) contributes to the
nonlinear behavior of the HEMT transistor. In this accord,
static IV curves representing the drain-to-source current
are utilized to characterize two dominant nonlinear circuit
elements previously identied: the transconductance (g
m
)
and the output conductance (g
ds
). These parameters plot-
ted versus the drain-to-source (V
ds
) and gate-to-source
(V
gs
) voltages as shown in Figs. 2632, show the nonlin-
earity of the elements displayed as a function of the DC
bias voltages.
For the class of multipliers under consideration, the
nonlinear behavior of the drain-to-source current (I
ds
) pro-
duces harmonic generation through its clipping effect
[79,98]. In the case of harmonic generation, the conclu-
sion has been advanced that optimum harmonic genera-
tion occurs for either V
gs
0 or V
gs
V
p
[97,98,102,127].
If the FET is biased at V
gs
0, the input voltage wave-
form appearing across the gate-to-source capacitance (C
gs
)
is clipped and will be half-wave rectied because of the
conduction cycles experienced by the gate-to-source diode.
This rectied waveform is transferred to I
ds
through the
devices transfer properties as reected by the analytical
relation between I
ds
and V
gs
[55]. When the device is bi-
ased at the pinchoff voltage (V
gs
V
p
), however, the input
voltage at the gate causes the FET to turn on during the
positive half-cycle of the input voltage, and the output
voltage again becomes a half-wave rectied waveform.
35
30
25
20
15
10
5
0
0 0.5 1 1.5 2 2.5 3
V
gs
= 0 V
V
ds
(V)
I
d
s

(
m
A
)
V
gs
= 0.2 V
V
gs
= 0.4 V
V
gs
= 0.6 V
Figure 26. Modeled drain current of HEMT transistor versus
drain-to-source voltage.
35
30
25
20
15
10
5
0
0.6 0.5 0.4 0.3 0.2 0.1 0
V
ds
= 3 V V
ds
= 2 V
V
ds
= 1 V V
ds
= 2.4 V
V
gs
(V)
I
d
s

(
m
A
)
Figure 27. Modeled drain current of HEMT transistor versus
gate-to-source voltage.
Gate
Source
Drain
L
d
R
d
C
ds
C
gd
D
gd
R
g
R
s
L
s
L
g
D
gs
C
gs
V
gs
V
ds
I
ds
(V
gs
,

V
ds
)
Figure 28. HEMT/PHEMT nonlinear equivalent model.
When the gate voltage is biased between 0 V and pinchoff
(0ZV
gs
ZV
p
), and the input voltage swing is large enough
to cause clipping on both ends, the output current at the
drain will resemble a square wave. If the square wave is
symmetric, the second-harmonic component will be small,
but the third harmonic will be large, allowing frequency
tripling [97].
It has been shown that rich harmonic generation will
result for class A and class B operation of the transistor
[96,97,98]. Class A operation occurs for V
gs
0 Vand caus-
es drain current (I
ds
) rectication when the gate diode
swings into forward conduction. Class B operation occurs
for V
gs
V
p
, where V
p
is the pinchoff voltage, and causes
the drain current to clip when the gate voltage swings be-
low pinchoff.
Dow [97] and Camargo [98] conclude that class A FET
multipliers provide good multiplication gain and poor DC-
to-RF efciency, while class B FET multipliers have poor
multiplication gain and good DC-to-RF efciency.
Using the DC-to-RF efciency expression [Eq. (63)], the
efciency for typical HEMT frequency doublers, which was
simulated with V
gs
V
p
and V
gs
0 V, respectively, can be
computed. As an example, evaluating various simulation
data for V
gs
V
p
, the DC-to-RF efciency is 23.5%, and for
typical simulations for V
gs
0 V, the DC-to-RF efciency is
0.03%. In each simulation the DC supply voltage (V
ds
) was
3 V, which causes the DC power for the simulation with
V
gs
0 V to be considerably higher and, subsequently,
to reduce the DC-to-RF efciency. Usually, for class A
operation the device is biased at a lower V
ds
voltage
than the case presented here, thus reducing the DC pow-
er and increasing the DC-to-RF efciency.
More recent research has shown, however, that other
V
gs
values may provide better and more optimum results
[166,172]. These results demonstrate that other biases
provide improved performance from an output harmonic
power perspective. This conclusion was based on the use of
rather basic device models that contained no feedback,
parasitic elements, or nonlinear G
d
. Employing their an-
alytical approach, which was a revision of Maas [44],
OCiardha et al. [172] predict potentially realistic 8% im-
provement in output doubler power utilizing only modest
changes in bias and input power. Theoretical improve-
ments are shown to be up to 15%.
An investigation by Johnson [171] reveals that, while
this is true, these new biases require greater input power
and have inferior conversion gain.
Focusing on the Fujitsu FHX35LG HEMT device, mea-
sured and modeled measurements provide static IV
curves as shown in Fig. 33. From these data, measured
and modeled transconductance and output conductance
are derived.
Figures 3437 show the transconductance and output
conductances plotted as functions of the gate-to-source
(V
gs
) and drain-to-source (V
ds
) voltages. Recalling that
the optimum bias conditions are either V
gs
0 or V
gs
V
p
, the HEMT transconductance and output conductance
plots of Figs. 3437 show the nonlinear behavior of the
70
80
60
50
40
30
20
10
0
0 0.5 1 2 3 1.5 2.5
g
m

(
m
A
/
V
)
V
gs
= 0 V
V
gs
= 0.2 V
V
ds
(V)
V
gs
= 0.4 V
V
gs
= 0.6 V
Figure 29. Modeled transconductance of HEMT transistor ver-
sus drain-to-source voltage.
70
80
60
50
40
30
20
10
0.6 0.5 0.4
0.3
0.2 0.1 0
0
g
m

(
m
A
/
V
)
V
gs
(V)
V
ds
= 3 V
V
ds
= 2 V
V
ds
= 1 V
sus gate-to-source voltage.
70
80
60
50
40
30
20
10
0
0 0.5 1 2 3 1.5 2.5
g
m

(
m
A
/
V
)
V
ds
(V)
V
gs
=

0 V
V
gs
=

0.2 V
V
gs
=

0.4 V
Figure 31. Modeled output conductance of HEMT transistor ver-
20
10
0.6 0.5 0.4
0.3
0.2 0.1 0
0
V
gs
(V)
V
ds
= 0.6 V
V
ds
= 1.2 V
V
ds
= 3 V
g
d

(
m
S
)
Figure 32. Modeled output conductance of HEMT transistor ver-
sus gate-to-source voltage.
transconductance and output conductance at the optimum
bias regions.
In Figs. 34 and 36, oval circles representing the regions
(region I) of optimum nonlinearity are indicated for V
gs
0 V. These regions are identied as areas where the non-

linear variation in the transconductance and output con-
ductance is greatest. In Fig. 34, the variation in the
transconductance is actually greatest for V
ds
o 0.5 V, but
in this area of operation the transistor does not supply
appreciable gain, thus limiting its usefulness at these bias
levels for significant conversion gains. For V
ds
41 V, the
transconductance tends to atten with no significant vari-
ation for V
gs
0 V. This behavior is observed again in Fig.
36 with the output conductance.
In Figs. 35 and 37, regions (region II) for optimum non-
linearity are represented for V
gs
V
p
. Again, areas where
the nonlinear variation in the magnitudes of the trans-
conductance and output conductance is greatest are indi-
cated by oval circles. In Fig. 37, significant nonlinear
variation in the transconductance is also seen in the
vicinity of V
gs
0.3V. Operating in this vicinity is opti-
mum for frequency multipliers, where the third harmonic
(frequency tripler) is of interest [97]. Biasing in this vi-
cinity with large voltage swings at the gate of the FET
causes the I
ds
waveform to clip at both pinchoff and for-
ward conduction and causes I
ds
to resemble a square wave,
which enhances the third harmonic frequency [97]. In Fig.
37 significant variation in the output conductance also oc-
curs for V
gs
0 to 0.1 V for lower V
ds
values (V
ds
0.6V). As
mentioned previously, the gain of the transistor diminish-
es significantly in these bias areas, thus causing the
conversion gain of the frequency multiplier to reduce
as well. From these curves the prominent nonlinearity
regions for V
gs
0 is region I of Fig. 36, where g
ds
is dom-
inant and for V
gs
V
p
, region II of Fig. 35, with g
m
show-
ing the dominant effect.
3.4.2. Detrimental Parasitics: Denition of the Parasi-
tics. The equivalent-circuit topology for the nonlinear
FET transistor as given in Fig. 25 includes the parasitic
elements (L
s
, L
g
, L
d
, R
s
, R
d
, and R
g
). These parasitics arise
from the fabrication process in the development of semi-
conductor transistors and inuence the performance of
the transistor and thus warrant inclusion into the equiv-
alent-circuit model. The parasitic inductors (L
s
, L
g
, and
L
d
) primarily represent the inductance associated with
the metal contact pads deposited on the active-channel
layer of the FET. The source and drain parasitic resistors
(R
s
and R
d
) represent the contact resistance of the ohmic
contacts underneath the metal contact pads and any bulk
resistance leading up to the active channel, and the gate
parasitic resistance (R
g
) represents the metallization re-
sistance of the gate Schottky contact [49].
3.4.3. Optimum Bias Selection Referencing Harmonic
Terminations. A primary factor affecting optimum perfor-
mance of microwave multipliers employing nonlinear de-
vices is the proper termination of the fundamental and
other harmonic frequency components with regard to bias
selection. This section presents a quantitative analysis
leading to the assessment of optimum terminating imped-
ances in the design of active frequency multipliers, with
90
80
70
60
50
40
30
20
10
0
Measured
Region I
Simulated
0 0.5 1 2 3 1.5 2.5
V
ds
(V)
g
m

(
m
A
/
V
)
V
gs
= 0 V
V
gs
= 0.3 V
V
gs
= 0.5 V
Figure 34. Measured and simulated transconductance of
FHX35LG (region I).
70
60
50
40
30
20
10
0
0 0.5 1 2 3 1.5 2.5
g
d

(
m
S
)
V
ds
(V)
V
gs
=0.3 V
V
gs
= 0 V
V
gs
= 0.5 V
Simulated
Region I
Measured
V
gs
= 0.7 V
Figure 36. Measured and simulated output conductance of
FHX35LG (region I).
90
80
70
60
50
40
30
20
10
0
0.60 0.50 0.40 0.30 0.20 0.10 0
V
gs
(V)
V
ds
= 3 V
V
ds
= 1.2 V
Vd
s

=
2
V
Region II
Measured
Simulated
g
m

(
m
A
/
V
)
Figure 35. Measured and simulated transconductance of
FHX35LG (region II).
35.0
40.0
Measured
Simulated
30.0
25.0
20.0
15.0
10.0
5.0
0.0
0.0 0.5 1 2 3 1.5 2.5
I
d
s

(
m
A
)
V
ds
(V)
V
gs
= 0 V
V
gs
= 0.3 V
V
gs
= 0.5 V
V
gs
= 0.7 V
special attention given to harmonics other than those de-
sired. The analysis includes computer modeled HEMT
data and supporting measured data for corresponding cir-
cuit realizations. Circuit designs are presented utilizing
HEMT transistors as the active element to verify modeled
results. From the available literature, the results demon-
strate, for the rst time, the quantitative effects of har-
monic termination on active multiplier conversion gain
and fundamental and higher-harmonic suppression. An
experimental design, which will be discussed later, reveals
an improvement in multiplier gain of 77% over the
conventional approach, and data are presented that quan-
titatively illustrate the advantages of impedance termina-
tion considerations under optimal bias conditions.
3.5. Background and Motivation
Numerous techniques exist for the realization of frequency
multipliers, as will be discussed below [8788,91128,
130132,137139]. At radiofrequencies, these techniques
typically employ a nonlinear device to generate the desired
frequency multiple. In the design of passive multipliers,
the nonlinear element is typically a varactor diode. In the
active case, the nonlinear element typically includes any of
several transistor classes such as BJT and FET.
In many frequency multiplier design approaches, the
operating performance is improved by the proper selection
of input and output circuits terminating impedances
at the fundamental and harmonic frequencies [9195,
109,145].
This section presents a quantitative analysis of the op-
timization of active multiplier conversion gain and spec-
tral purity, as governed by fundamental and harmonic
terminating impedances and regions of nonlinearity. It is
believed that access to this quantitative information will
be of use for designers of future circuits. HEMT transistors
are employed to represent the class of nonlinear elements
to illustrate the approach. The optimum terminating im-
pedances are determined for the input and output ports of
the active device, utilizing a more recent nonlinear circuit
model for HEMT transistors. This is in marked contrast
with earlier studies, which used approximations in the
simulated performance predictions [79,93,98]. The results
presented in this section incorporate dependences be-
tween the input and output harmonic terminating imped-
ances that are not found in previous studies. For the
multipliers examined in this section, these impedances
include terminations at the fundamental, second-harmon-
ic, and third-harmonic frequencies. Measured data are
presented that validate the practicality of the designs and
the accuracy of the simulations.
3.5.1. Nonlinear Model. An accurate nonlinear circuit
model is required for the quantitative assessment of opti-
mum terminating impedances in the design of active fre-
quency multipliers. Such an equivalent-circuit model
permits supporting simulated data to accompany any
measured data that further authenticate results. An ac-
curate nonlinear model was presented earlier for the
Fujitsu FHX35LG HEMT, which will be employed below
for analyzing bias selection with regard to harmonic
terminations (case parasitics are included in the model
but not shown in the gure).
Static IV curves for this HEMT, obtained from the
model of Fig. 25 and laboratory measurements, are em-
ployed to characterize two dominant circuit element
nonlinearities: transconductance (g
m
) and the output con-
ductance (g
d
). These parameters (modeled and measured),
which were derived from the above mentioned sources, are
plotted versus the drain-to-source (V
ds
) and gate-to-source
(V
gs
) voltages shown in Figs. 3337. These plots graphi-
cally display the nonlinearity of the corresponding HEMT
elements as a function of the DC bias voltages. The con-
clusions for the HEMT multiplier are presented quantita-
tively below.
Utilizing the HEMT transconductance and output con-
ductance plots of Figs. 3337, the prominent nonlinear
regions for the optimum DC bias points (either V
gs
0 or
V
gs
V
p
) were identied in previous sections. Fundamen-
tal load-line analysis indicates that the optimum imped-
ance for region I (V
gs
0) is an open-circuit impedance
that allows a maximum V
ds
voltage swing, and for region
II (V
gs
V
p
) the optimum impedance is a short-circuit im-
pedance that allows a maximum I
ds
current swing [145].
These qualitative assertions will be substantiated quanti-
tatively in the ensuing discussion.
3.5.2. Harmonic Terminations. The preceding analysis
provides motivation for development of an optimal design
approach. We employ the following multiplier design as an
illustration. The basic topology of the frequency multiplier
used is illustrated in Fig. 38. In this conguration, SC
i
, i
1yn, and OC
j
, j 1ym, represent short-circuit and open-
circuit terminating impedances, respectively, for the
multiplier input network at the respective frequencies.
Similarly, SC
k
, k 1yo, and OC
1
, l 1yp, represent
short- and open-circuit terminating impedances for the
multiplier output network. An innite number of circuit
realizations exist that conform to the conguration of Fig.
38. This provides the motivation for development of a ma-
trix of various circuit congurations as illustrated in Table
1, which displays various harmonic terminating imped-
ances on the input and output ports of the multiplier re-
alization depicted in Fig. 38. Tables have been constructed
for multiplier operation (up to the third harmonic) utiliz-
ing the precision HEMT computer model with case
0
V
ds
= 0.6 V
V
ds
= 1.2 V
V
ds
= 3 V
Region II
Measured
Simulated
V
gs
(V)
g
d

(
m
S
)
20
10
0.6 0.5 0.4 0.3 0.2 0.1
0
Figure 37. Measured and simulated output conductance of
FHX35LG (region II).
parasitics. In Table 1, the left-hand vertical column repre-
sents various impedance terminations of the input net-
work at the fundamental, second-harmonic, and third-
harmonic frequencies. The top horizontal row represents
various impedances of the output network at the funda-
mental, second-harmonic, and third-harmonic frequencies.
To assess performance under various load termina-
tions, several load congurations were analyzed. On the
basis of previous discussions, fundamental and harmonic
loads of interest may be short-circuited, open-circuited,
matched, or 50.
As a rst case, the options shown in Tables 1 and 2 were
selected. Since only 50, short, and open loads are used,
this choice of terminations would appear to provide a con-
crete basis for assessing the effects of a variety of other
input and output harmonic load conditions. Table 1 illus-
trates the conversion gains obtained employing the
FHX35LG HEMT utilizing a harmonic balance program
with input and output networks synthesized with lumped
elements to realize the indicated harmonic terminations
with f
0
3 GHz. The HEMT in this table is biased at
pinchoff V
gs
V
p
and driven with 0 dBm at the gate ter-
minal (region II; Figs 35 and 37). This table is presented as
a basis by which to measure the quantitative impact of a
Input network
R
g
OC
1
OC
1
OC
m
OC
m
SC
1
SC
0
SC
n E
g
R
Output network
HEMT
SC
1
Figure 38. Frequency multiplier realization.
Table 1. Doubler Simulations with Lumped Components (V
gs
0.7V, P
in
0dBm, V
ds
3 V)
Output Power (dBm)
a
Input
Network (O)
a,b
Output
Network (O)
a,b:
50
50
50
_
_
_
_
_
_
_
_
0
50
50
_
_
_
_
_
_
_
_
1
50
50
_
_
_
_
_
_
_
_
0
50
1
_
_
_
_
_
_
_
_
1
50
1
_
_
_
_
_
_
_
_
50
50
0
_
_
_
_
_
_
_
_
50
50
1
_
_
_
_
_
_
_
_
0
50
0
_
_
_
_
_
_
_
_
1
50
0
_
_
_
_
_
_
_
_
50
50
50
_
_
_
_
_
_
_
_
5:96
0:9
14:7
_
_
_
_
_
_
_
_
73
0
14
_
_
_
_
_
_
_
_
66:5
1
17:8
_
_
_
_
_
_
_
_
73:2
0:3
72:5
_
_
_
_
_
_
_
_
66:5
0:7
107
_
_
_
_
_
_
_
_
5:9
1:3
94
_
_
_
_
_
_
_
_
5:9
0:7
104
_
_
_
_
_
_
_
_
73:2
0:2
94
_
_
_
_
_
_
_
_
66:5
1:4
97:2
_
_
_
_
_
_
_
_
50
0
50
_
_
_
_
_
_
_
_
6:2
0:3
11:8
_
_
_
_
_
_
_
_
72:9
1:5
10:6
_
_
_
_
_
_
_
_
66:3
0:1
17:2
_
_
_
_
_
_
_
_
72:8
1:8
68:9
_
_
_
_
_
_
_
_
66:3
0:2
106
_
_
_
_
_
_
_
_
6:2
0
92
_
_
_
_
_
_
_
_
6:3
0:7
100
_
_
_
_
_
_
_
_
72:9
1:2
91:1
_
_
_
_
_
_
_
_
66:3
0:5
97:7
_
_
_
_
_
_
_
_
50
0
0
_
_
_
_
_
_
_
_
6
1:2
13:4
_
_
_
_
_
_
_
_
72:9
1:5
10:6
_
_
_
_
_
_
_
_
66:3
0:1
17:2
_
_
_
_
_
_
_
_
72:8
1:8
99:1
_
_
_
_
_
_
_
_
66:5
0:9
109:6
_
_
_
_
_
_
_
_
6:2
0:3
11:8
_
_
_
_
_
_
_
_
6:3
0:7
100:6
_
_
_
_
_
_
_
_
72:9
1:2
91:1
_
_
_
_
_
_
_
_
66:3
0:5
97:7
_
_
_
_
_
_
_
_
50
50
0
_
_
_
_
_
_
_
_
5:9
2:2
17:1
_
_
_
_
_
_
_
_
73:2
1:3
16:8
_
_
_
_
_
_
_
_
66:5
2:3
15:8
_
_
_
_
_
_
_
_
73:2
1:2
108:2
_
_
_
_
_
_
_
_
66:5
1:7
106:6
_
_
_
_
_
_
_
_
5:9
1:3
94:5
_
_
_
_
_
_
_
_
5:9
2:1
108
_
_
_
_
_
_
_
_
73:2
0:1
94:1
_
_
_
_
_
_
_
_
66:7
2:7
90:5
_
_
_
_
_
_
_
_
50
1
50
_
_
_
_
_
_
_
_
6:1
1
15:9
_
_
_
_
_
_
_
_
73
0
15:3
_
_
_
_
_
_
_
_
66:6
1:2
21:2
_
_
_
_
_
_
_
_
73:1
0:1
104
_
_
_
_
_
_
_
_
66:6
1
109
_
_
_
_
_
_
_
_
6:1
1:1
96
_
_
_
_
_
_
_
_
6:1
0:8
105
_
_
_
_
_
_
_
_
73
0:2
96:1
_
_
_
_
_
_
_
_
66:5
1:5
100:4
_
_
_
_
_
_
_
_
50
1
1
_
_
_
_
_
_
_
_
6:1
0:9
15:7
_
_
_
_
_
_
_
_
73
0
15:1
_
_
_
_
_
_
_
_
66:5
1:1
20
_
_
_
_
_
_
_
_
73
0:3
104
_
_
_
_
_
_
_
_
66:5
0:9
108
_
_
_
_
_
_
_
_
6:1
1:2
96:2
_
_
_
_
_
_
_
_
6:1
0:7
105
_
_
_
_
_
_
_
_
73
0:2
96
_
_
_
_
_
_
_
_
66:5
1:4
99:8
_
_
_
_
_
_
_
_
50
50
1
_
_
_
_
_
_
_
_
6
0:8
14:3
_
_
_
_
_
_
_
_
73:1
0:1
13:6
_
_
_
_
_
_
_
_
66:5
0:9
17
_
_
_
_
_
_
_
_
73
0:4
102
_
_
_
_
_
_
_
_
66:5
0:7
105
_
_
_
_
_
_
_
_
6
1:3
94:4
_
_
_
_
_
_
_
_
6
0:5
103
_
_
_
_
_
_
_
_
73
0:2
93:9
_
_
_
_
_
_
_
_
66:5
1:4
96:9
_
_
_
_
_
_
_
_
a
At
f
0
2f
0
3f
0
_
_
_
_
_
_
_
_
.
b
0short circuit; Nopen circuit.
variety of terminations on multiplier conversion gain. The
numbers to the right of each entry in the table represent
the powers obtained at respective harmonics. It is instruc-
tive to consider a typical entry of interest in this table. The
entry located in the second row and second column, for
example, shows that a conversion gain of 1.5dB is ob-
tained if the input network terminates the fundamental f
0
and third harmonic 3f
0
in 50, while the second-harmonic
2f
0
is short-circuited. The output network for this entry
terminates the fundamental in a short circuit and all oth-
er harmonics in 50. Several authors [93,98,99,102] have
reported that the input network should terminate the sec-
ond-harmonic in a short circuit. For lumped input circuit
realizations, however, this table reveals that this provides
a 1.5 dB improvement over a 50 or an open-circuit termi-
nation at 2f
0
(row 1, column 2 and row 5, column 2, re-
spectively). While the conversion gains represented in this
table are not large and the dB values do not show great
variation, several trends are seen to emerge, and subse-
quent results will substantiate their implications. In par-
ticular, the impact of input network terminations from the
data in rows 2 and 3 show, that for doubler operation, a
short-circuit termination at 2f
0
provides the best conver-
sion gain in all cases considered.
Furthermore, a perusal of output network termination
responses shows that a short circuit at f
0
provides the best
performance using conversion gain as a basis.
Table 2 shows similar data when the HEMT is biased at
V
gs
0 (region I). This V
gs
value was chosen in accordance
with our previous discussion on optimum bias regions.
While an important outcome of the V
gs
0 table was typ-
ically lower conversion gains in comparison with Table 1,
where V
gs
V
p
, an even more significant observation is
the dramatic improvement (B12dB) obtained by employ-
ing an open-circuit termination at f
0
in the output net-
work, in contrast with a short circuit, which was the
Table 2. Doubler Simulations with Lumped Components (V
gs
0V, P
in
0dBm, V
ds
3V)
Output Power (dBm)
a
Input
Network (O)
a,b
Output
Network (O)
a,b:
50
50
50
_
_
_
_
_
_
_
_
0
50
50
_
_
_
_
_
_
_
_
1
50
50
_
_
_
_
_
_
_
_
0
50
1
_
_
_
_
_
_
_
_
1
50
1
_
_
_
_
_
_
_
_
50
50
0
_
_
_
_
_
_
_
_
50
50
1
_
_
_
_
_
_
_
_
0
50
0
_
_
_
_
_
_
_
_
1
50
0
_
_
_
_
_
_
_
_
50
50
50
_
_
_
_
_
_
_
_
12:5
10:1
13:9
_
_
_
_
_
_
_
_
66:2
10:9
10:7
_
_
_
_
_
_
_
_
62:1
2:4
7:1
_
_
_
_
_
_
_
_
66:2
10:6
98
_
_
_
_
_
_
_
_
62
2
92
_
_
_
_
_
_
_
_
12:5
10:2
94:3
_
_
_
_
_
_
_
_
12:5
10
101
_
_
_
_
_
_
_
_
66:3
11:2
91:8
_
_
_
_
_
_
_
_
62:1
2:2
89:5
_
_
_
_
_
_
_
_
50
0
50
_
_
_
_
_
_
_
_
12:4
11:1
14:1
_
_
_
_
_
_
_
_
66
14:7
11:1
_
_
_
_
_
_
_
_
62:2
2:6
7:3
_
_
_
_
_
_
_
_
66
14:1
98:4
_
_
_
_
_
_
_
_
62
2:1
92:7
_
_
_
_
_
_
_
_
12:4
11:3
94:8
_
_
_
_
_
_
_
_
12:5
10:8
101
_
_
_
_
_
_
_
_
66:2
15:3
92:2
_
_
_
_
_
_
_
_
62
2:7
89:8
_
_
_
_
_
_
_
_
50
0
0
_
_
_
_
_
_
_
_
12:4
11:2
18:6
_
_
_
_
_
_
_
_
66
15:3
14:6
_
_
_
_
_
_
_
_
62
3:2
5:9
_
_
_
_
_
_
_
_
66
15:4
105
_
_
_
_
_
_
_
_
62
2:2
94:2
_
_
_
_
_
_
_
_
12:4
10:8
82:7
_
_
_
_
_
_
_
_
12:4
11:1
109
_
_
_
_
_
_
_
_
66:1
13:8
81:8
_
_
_
_
_
_
_
_
62:4
2:8
78
_
_
_
_
_
_
_
_
50
50
0
_
_
_
_
_
_
_
_
12:4
10:2
18:3
_
_
_
_
_
_
_
_
66:3
11:2
14:9
_
_
_
_
_
_
_
_
62:1
3
5:7
_
_
_
_
_
_
_
_
66
11:2
37:1
_
_
_
_
_
_
_
_
62:1
2:1
93:9
_
_
_
_
_
_
_
_
12:5
10:4
82:4
_
_
_
_
_
_
_
_
12:4
10
109
_
_
_
_
_
_
_
_
66
10:9
82:2
_
_
_
_
_
_
_
_
62:3
2:4
78
_
_
_
_
_
_
_
_
50
1
50
_
_
_
_
_
_
_
_
12:6
9:3
13:7
_
_
_
_
_
_
_
_
66:1
10:3
10:3
_
_
_
_
_
_
_
_
62:1
2:1
7:1
_
_
_
_
_
_
_
_
66:1
10:1
97:8
_
_
_
_
_
_
_
_
62:1
1:7
92:4
_
_
_
_
_
_
_
_
12:6
9:3
94:6
_
_
_
_
_
_
_
_
12:6
9:2
101
_
_
_
_
_
_
_
_
66:1
10:7
91:5
_
_
_
_
_
_
_
_
62:1
1:9
89:6
_
_
_
_
_
_
_
_
50
1
1
_
_
_
_
_
_
_
_
12:6
9:3
13
_
_
_
_
_
_
_
_
66
10:3
9:7
_
_
_
_
_
_
_
_
62
1:9
7:3
_
_
_
_
_
_
_
_
66
9:9
96:5
_
_
_
_
_
_
_
_
62:1
1:7
91:6
_
_
_
_
_
_
_
_
12:6
9:3
94:8
_
_
_
_
_
_
_
_
12:6
9:2
100
_
_
_
_
_
_
_
_
66
10:7
91:5
_
_
_
_
_
_
_
_
62
1:8
90:7
_
_
_
_
_
_
_
_
50
50
1
_
_
_
_
_
_
_
_
12:5
10:1
13:3
_
_
_
_
_
_
_
_
66:2
10:8
10:1
_
_
_
_
_
_
_
_
62:1
2:2
7:3
_
_
_
_
_
_
_
_
66:1
10:4
96:8
_
_
_
_
_
_
_
_
62:1
2
91:6
_
_
_
_
_
_
_
_
12:5
10:2
95:1
_
_
_
_
_
_
_
_
12:5
9:9
100
_
_
_
_
_
_
_
_
66:2
11:2
92
_
_
_
_
_
_
_
_
62:1
2:1
90:7
_
_
_
_
_
_
_
_
a
At
f
0
2f
0
3f
0
_
_
_
_
_
_
_
_
.
b
optimum case for region II. Note that Table 1 predicts only
a 1.6dB improvement for the analogous comparison.
On the basis of the observations above, we present re-
sults only for the specific case where the input network is
short-circuited at 2f
0
in the ensuing discussion.
Table 3 presents the results obtained for region II op-
eration (V
gs
V
p
) when the input network was synthe-
sized to provide a matched load at the fundamental
frequency f
0
and a short circuit at 2f
0
. In comparison
with its counterpart in row 2 of Table 1, which had a 50
termination at f
0
, it is seen that, as expected, significant
improvements occur in conversion gains for all output
network impedance terminations. A perusal of the values
indicates that significant increases in conversion gain of
over 5 dB are typical in each case. Furthermore, the fol-
lowing quantitative results may be observed for various
output network terminations: (1) 3.0dB better conversion
gains are obtained by short circuiting as compared with
open circuiting the fundamental (i.e., 8.0dB vs. 5.0dB), (2)
1.5 dB better conversion gain will be obtained for a short
circuit at f
0
in comparison with a 50 ohm termination
(notwithstanding the fact that the 50 ohm case would re-
quire some form of output circuit fundamental suppres-
sion), (3) 1.2dB of additional conversion gain is obtained if
the third harmonic is open-circuited in contrast with the
frequently used short-circuited third harmonic (8.6 vs.
7.4 dB), and (4) 3.8dB additional conversion gain is ob-
tained over the case where an open-circuit fundamental
and short-circuit third-harmonic output network are em-
ployed (i.e., 8.6dB vs. 4.8 dB).
Table 4 presents the results obtained for region II op-
eration when the output network is synthesized to provide
a matched load at the second-harmonic (2f
0
) versus the
previous cases where a simple 50 ohm load was employed.
On the basis of these results, it can be seen that for output
network terminations, where the fundamental has been
Table 3. Doubler Simulations Matched on Input with Microstrip Transmission Lines (V
gs
0.7V, P
in
0dBm, V
ds
3V
Output Power (dBm)
a
Input
Network (O)
a,b
Output
Network (O)
a,b
:
50
50
50
_
_
_
_
_
_
_
_
0
50
50
_
_
_
_
_
_
_
_
1
50
50
_
_
_
_
_
_
_
_
0
50
1
_
_
_
_
_
_
_
_
1
50
1
_
_
_
_
_
_
_
_
50
50
0
_
_
_
_
_
_
_
_
50
50
1
_
_
_
_
_
_
_
_
0
50
0
_
_
_
_
_
_
_
_
1
50
0
_
_
_
_
_
_
_
_
50
50
50
_
_
_
_
_
_
_
_
5:96
0:9
14:7
_
_
_
_
_
_
_
_
217
0:3
221
_
_
_
_
_
_
_
_
210
0:7
231
_
_
_
_
_
_
_
_
215
0:2
270
_
_
_
_
_
_
_
_
208
0:4
270
_
_
_
_
_
_
_
_
5:5
3:9
232
_
_
_
_
_
_
_
_
4:1
0:3
237
_
_
_
_
_
_
_
_
216
3:3
270
_
_
_
_
_
_
_
_
209
4:2
270
_
_
_
_
_
_
_
_
M
0
54
_
_
_
_
_
_
_
_
13
6:5
6:7
_
_
_
_
_
_
_
_
65:7
8
4:1
_
_
_
_
_
_
_
_
62:3
5
7:9
_
_
_
_
_
_
_
_
65:7
8:6
92:1
_
_
_
_
_
_
_
_
62:5
5:2
92:2
_
_
_
_
_
_
_
_
13
6:1
87:6
_
_
_
_
_
_
_
_
13
6:9
94:9
_
_
_
_
_
_
_
_
65:6
7:4
84:7
_
_
_
_
_
_
_
_
62:2
4:8
92:6
_
_
_
_
_
_
_
_
a
At
f
0
2f
0
3f
0
_
_
_
_
_
_
_
_
.
b
0short circuit; Nopen circuit; Mmatched.
Table 4. Doubler Simulations Matched on Input and Output with Microstrip Transmission Lines (V
gs
) 0.7V, P
in
0dBm,
V
ds
3V
Output Power (dBm)
a
Input
Network (O)
a,b
Output
Network (O)
a,b
:
50
50
50
_
_
_
_
_
_
_
_
0
M
85
_
_
_
_
_
_
_
_
1
M
85
_
_
_
_
_
_
_
_
0
M
1
_
_
_
_
_
_
_
_
1
M
1
_
_
_
_
_
_
_
_
36
M
0
_
_
_
_
_
_
_
_
37
M
1
_
_
_
_
_
_
_
_
0
M
0
_
_
_
_
_
_
_
_
1
M
0
_
_
_
_
_
_
_
_
M
0
54
_
_
_
_
_
_
_
_
14:4
6:4
2:9
_
_
_
_
_
_
_
_
70:2
10:1
8:1
_
_
_
_
_
_
_
_
61:9
4:7
16:2
_
_
_
_
_
_
_
_
70
10:4
89:5
_
_
_
_
_
_
_
_
61:5
5
99:1
_
_
_
_
_
_
_
_
12:8
9:1
95:8
_
_
_
_
_
_
_
_
12:5
7:3
86:1
_
_
_
_
_
_
_
_
70
9:5
96:7
_
_
_
_
_
_
_
_
60:6
5:1
110:3
_
_
_
_
_
_
_
_
a
At
f
0
2f
0
3f
0
_
_
_
_
_
_
_
_
.
b
0short circuit; Nopen circuit; Mmatched.
short-circuited, an additional 2 dB has been obtained over
the results in Table 3 and approximately 9 dB over Table 1
results.
Tables 5 and 6 display the results obtained utilizing
microstrip-line circuits that were synthesized to provide
short-circuited, open and 50 terminations at respective
fundamental and harmonic frequencies as employed in
many traditional designs [79,92,95,97,98,100110].
With reference to Table 5 (region II, V
gs
V
p
), a com-
parison of the effect of the distributed input network (row
2, column 1) with a 50 input network at f
0
, 2f
0
, and 3f
0
(row
1, column 1) shows that 5.2dB improvement in conversion
gain performance may be obtained by employing the dis-
tributed structure with a short circuit at 2f
0
. Some addi-
tional conclusions obtained from a further perusal of this
table are as follows: (1) 8.6dB conversion gain improve-
ment may be obtained by providing a distributed output
network that is short-circuited at f
0
and 3f
0
as compared
with 50 ohm input and output terminations (row 1, col-
umn 1 vs. row 2, column 4); (2) with the distributed input
network terminated in a short circuit, 1.3dB improvement
in conversion gain may be obtained by short-circuiting the
output network at f
0
and 3f
0
(column 4) as compared with
open circuits at f
0
and 3f
0
(column 5); (3) the difference in
termination in the output network between open and
short circuits at f
0
is on the order of 1 dB; and (4) an ad-
ditional 2.3dB of conversion gain is obtained by introduc-
ing an additional short-circuited stub at 3f
0
.
Table 6 presents similar results for region I (V
gs
0)
operation. Several significant conclusions are evident
from these results: (1) optimal performance is consider-
ably less (2.8 vs. 7.7 dB) than that for region II operation,
Table 5. Simulated Doubler Response with Microstrip Elements (Region II; (V
gs
0.7V, P
in
0dBm, V
ds
3V)
Output Power (dBm)
a
Input
Network (O)
a,b
Output
Network (O)
a,b
:
50
50
50
_
_
_
_
_
_
_
_
0
50
0
_
_
_
_
_
_
_
_
1
50
0
_
_
_
_
_
_
_
_
0
62
0
_
_
_
_
_
_
_
_
1
63
1
_
_
_
_
_
_
_
_
27
49
1
_
_
_
_
_
_
_
_
50
50
50
_
_
_
_
_
_
_
_
5:96
0:9
14:7
_
_
_
_
_
_
_
_
27:1
0:7
26:3
_
_
_
_
_
_
_
_
10:4
0:9
36:2
_
_
_
_
_
_
_
_
25
0:4
52:9
_
_
_
_
_
_
_
_
17:3
0:8
60:1
_
_
_
_
_
_
_
_
4
0:6
37:7
_
_
_
_
_
_
_
_
50
0
50
_
_
_
_
_
_
_
_
10:7
4:3
10:2
_
_
_
_
_
_
_
_
27:4
5:4
22:6
_
_
_
_
_
_
_
_
22
4:5
21
_
_
_
_
_
_
_
_
19:9
7:7
46:9
_
_
_
_
_
_
_
_
13:5
6:4
61
_
_
_
_
_
_
_
_
9
7:2
32
_
_
_
_
_
_
_
_
a
At
f
0
2f
0
3f
0
_
_
_
_
_
_
_
_
.
b
Table 6. Simulated Doubler Response with Microstrip Elements (Region I; (V
gs
0V, P
in
0dBm, V
ds
3V)
Output Power (dBm)
a
Input
Network (O)
a,b
Output
Network (O)
a,b
:
50
50
50
_
_
_
_
_
_
_
_
0
50
0
_
_
_
_
_
_
_
_
1
50
1
_
_
_
_
_
_
_
_
0
62
0
_
_
_
_
_
_
_
_
1
63
1
_
_
_
_
_
_
_
_
27
49
1
_
_
_
_
_
_
_
_
50
50
50
_
_
_
_
_
_
_
_
12:5
10:1
13:9
_
_
_
_
_
_
_
_
20:2
11:4
26:3
_
_
_
_
_
_
_
_
15:1
2:5
25:4
_
_
_
_
_
_
_
_
22:9
10:9
49:3
_
_
_
_
_
_
_
_
12:5
4
55:4
_
_
_
_
_
_
_
_
11:1
10
33:9
_
_
_
_
_
_
_
_
50
0
50
_
_
_
_
_
_
_
_
14:7
12:5
8:4
_
_
_
_
_
_
_
_
18:4
13:1
18:4
_
_
_
_
_
_
_
_
14:4
1:8
25:6
_
_
_
_
_
_
_
_
21:3
10:4
41
_
_
_
_
_
_
_
_
11:1
2:8
52
_
_
_
_
_
_
_
_
13:2
10:6
2:8
_
_
_
_
_
_
_
_
a
At
f
0
2f
0
3f
0
_
_
_
_
_
_
_
_
.
b
(2) significant conversion gain improvement is obtained
when the output network is open circuited at f
0
in com-
parison with the short-circuited condition (1.8 vs. 13.1
to 15 dB, and (3) 1 dB of conversion gain performance
improvement is achieved by introducing an additional
open-circuited stub at the third harmonic.
This topic will be revisited in the next section in the
discussion of active multiplier design. Specific multiplier
designs are illustrated demonstrating the efcacy of har-
monic terminations and optimum bias selection.
4. ACTIVE MULTIPLIER DESIGN TECHNIQUES
4.1. Existing Active Multiplier Design Techniques
Since the 1980s, numerous researchers have discussed
numerous design approaches leading to various design
procedures utilizing various active devices and topologies
in different media and frequency ranges. This section
presents various existing design techniques and other
techniques implemented by the author.
A fundamental topological representation for realiza-
tion of active microwave multiplier circuits is shown in
Fig. 39. While this is not the most generalized topology, it
is one of the most frequently used. The physical realiza-
tion of an efcient frequency multiplier subject to design
criteria utilizing this conguration is strongly reliant
on the synthesis of networks N
1
, N
2
, and N
3
, which are
typically, but not always, passive. The criteria for speci-
cation of N
1
, N
2
, and N
3
rely, heavily as usual, on funda-
mental active-device parameters. In the case of
multipliers, this is heavily dependent upon bias condi-
tions, input power level, and frequency.
Only very seldom have designers intentionally em-
ployed feedback (N
3
) in multiplier designs in the realiza-
tion of such circuits [165]. Synthesis of N
3
is typically
avoided, due in part to potential stability problems
[93,106,147]. This network, however, has the potential of
providing useful improvement in conversion efciency by
proper combination of harmonics emerging from the ac-
tive device with the input fundamental, for example, at
the correct phase. The feedback network (N
3
) combines a
harmonic component from the drain (collector) of the tran-
sistor with the fundamental component on the gate (base).
Theoretically, this produces an enhanced component at
the desired output harmonic frequency on the drain (col-
lector), assuming that in the ideal case the phase of the
feedback is optimal [106,147].
Some designers have selected a balanced version of the
topology given in Fig. 39 for doubler design, with expec-
tations of superior doubler performance [91,109,111113,
148,149]. These seem to have been inspired by the advan-
tages actually realized in the design of diode doublers
[150]. Developers of such balanced active multipliers state
that these circuits are better because of the natural can-
cellation of the fundamental and all odd harmonics, thus
providing a virtual ground at the output of the active de-
vices and permitting the location of any matching net-
works closer to the drain (collector) of the devices [99].
Furthermore, they indicate that such designs have the
advantage of high conversion efciency, 3 dB better output
power, better isolation, good harmonic suppression, and
the elimination of the long (l/4) stubs that are common in
single-ended designs.
One of the design classes emphasizes the arrangement
of two or more transistors in one of several topological
congurations as shown in Figs. 40 and 41. The technique
shown in Fig. 40 utilizes two identical fundamental fre-
quency signals, which are fed 1801 out of phase to transis-
tors T
1
and T
2
. The circuit functions as a type of active full-
wave rectier in that when the voltage at port 1 is positive,
T
1
conducts and T
2
is turned off and current ows through
the emitter of T
1
to the load Z
L
. When the polarity of the
input signal V(f
1
) is reversed, T
2
conducts and T
1
is turned
off and current ows through the collector of T
2
, providing
an output to Z
L
. This process effectively provides a rectied
output at Z
L
with the corresponding strong second-har-
monic content. This approach has been demonstrated for
doubler action over a broad frequency range (17GHz) in
MMIC topology. Conversion gains range from 0 to 12dB,
utilizing input and output amplication stages. Funda-
mental rejections of less than 10dBappear to be realizable.
A block diagram of a typical balanced multiplier design
is shown in Fig. 41. At the input, the input signal of the
multiplier is fed through a powerdividerphase shifter,
N
3
Transistor N
2
Z
L
Z
g
E
g
N
1
Figure 39. Frequency multiplier realization.
T
1
(1)
(2)
(3)
Z
L
T
2
V(f
1
)
V(f
1
)
+
Figure 40. Block diagram of pushpush topology of frequency
multiplier.
which divides the power between the two transistors with
1801 phase difference between the input ports of the tran-
sistors. The drains (collectors) of the transistors are con-
nected on the output by a combiner. At the output, the
fundamental and odd harmonic signals have opposite
phase, and, by destructive interference, cancel, giving
good harmonic suppression. The second-harmonic signals
from the transistors have the same phase and thus inter-
fere constructively.
A perusal of the published literature on such balanced
designs reveals, however, that they require complex com-
ponents in their realization. In addition to two matched
active devices (some designers use more in their active
matching stages), balanced designs typically require large
baluns or powersplitterphase shifter combinations, T
junctions, and in some cases airbridges. Some realizations
also require complex transitions and additional lengths of
transmission lines to rotate the active device outputs to
achieve a pure reactance output. Finally, only frequency
doubler designs are typically reported; however, Fudem
and Niehenke [166] have realized a balanced tripler. It is
found that, with due consideration of the importance of
the particular active device characteristics and frequency
bands, these designs in almost all cases are narrowband
(10%) (Ref. 112, with 9 dB conversion gains, is one ex-
ception; it uses an additional active device), have modest
conversion gain ( 5 to 5dB; 3 to 12 dB in one case), and
frequently yield sparse data on fundamental suppression
(typically between 12 and 30 dB).
Hiraoka [148], for example, developed a broadband
MMIC balanced frequency doubler with a fundamental
frequency of 5 GHz, consisting of a common-gate FET and
a common-source FET directly connected in parallel, fol-
lowed by an output-matching network. A phase shifter
network precedes the common-gate FET to compensate for
the phase error between the outputs from the common-
gate FET and the common-source FET. A conversion loss
of 810dB was achieved for output frequencies between 6
and 16 GHz. Fundamental frequency isolation (suppres-
sion) better than 17 dB up to output frequencies of 20 GHz
was obtained. Unfortunately, the author did not provide
any data on the third-harmonic isolation (suppression).
Angelov [113] discusses a 2040-GHz balanced doubler
where two common-source PHEMTs are connected in par-
allel followed by sections of transmission lines on the gates
before combining into a 3-dB coupler. The input signal to
the doubler is fed to a power divider, which divides the
power equally between the two input ports with 1801
phase difference between the input ports. Sections of
transmission lines connect the power divider to the drain
of the PHEMTs. The completed doubler circuit provides
approximately 1 dB of conversion gain with a 3 dB
bandwidth of approximately 5%. The author notes that
the bandwidth is limited mainly by the 1801 ratrace cou-
pler. The author does not provide data on the fundamental
and the third-harmonic suppression.
Takenaka and Ogawa [111,112] developed a wideband
MMIC balanced frequency multiplier utilizing line-unied
HEMT congurations. In line-unied HEMT congura-
tions, coplanar lines such as slotlines and coplanar wave-
guides are used to connect the circuit electrically. A
coplanar waveguide precedes a common-gate HEMT fol-
lowed by a slotline series T junction, which acts as an out-
of-phase divider to drive two parallel, common-drain
HEMTs. The output of the two HEMTs is connected to a
coplanar waveguide followed by the load resistance. This
topology yields conversion loss of 810dB in the 440GHz
output frequency range, and fundamental frequency sig-
nal isolation of better than 21 dB above the input frequen-
cy of 7 GHz. The authors do not provide any data on third-
harmonic isolation.
One nal observation on balanced designs is the almost
universal disregard for the deleterious effects of channel
imbalances. It has been reported that for phase imbalanc-
es of 101, the output conversion gain at the second-har-
monic will decrease by 1 dB in a 4-dB design, while an
amplitude imbalance of 0.3dB produces the same 1dB de-
crease. A combination of imbalances of 101 and 0.3dB to-
gether results in a 3dB decrease in a 4-dB conversion gain
design [113,151,167]. For these reasons, balanced realiza-
tions are not considered further in this article, although
obviously some principles presented are directly transfer-
able to balanced circuits.
Numerous investigators have reported designs for sin-
gle-ended microwave multipliers. Referring to Figs. 25
and 39, these designs include networks N
1
and N
2
but ex-
clude an external network N
3
. Thus, single-ended designs
are based primarily on the realization of N
1
and N
2
. Tra-
ditional synthesis of N
1
and N
2
have followed the lines of
the passive case where N
1
is traditionally composed of a
bandpass or lowpass lter or matching network tuned to a
fundamental frequency, and N
2
is similarly a matching
network or bandpass or highpass lter tuned to the ap-
propriate harmonic frequency of interest. Synthesis of
these networks includes the use of cascades of lters and
matching networks [87,88,97,99,108,110,116123,124,
125,128,147,152154], and such methods have been real-
ized utilizing transmission lines and stubs to open-circuit-,
or short-circuit-specific harmonics [88,108,110,154], while
some authors have additionally considered these networks
as a cascade of matching and reection networks
[95,104,110,154]. Many of these techniques determine
optimal networks by utilizing load-line analysis [91,92],
intuitive reasoning based on previous results [92,124],
computer optimization of generalized models [106,108],
and experimental techniques based on stub tuner mea-
surements [88,154].
The following paragraphs illustrate some specific
examples of these classes of realizations. Dow [97]
Transistor
(1) (2)
Transistor
Phase-
shifter-
power
splitter
Combiner
Figure 41. Block diagram of typical balanced frequency multi-
plier.
developed a FET frequency doubler with a fundamental
frequency of 20 GHz utilizing matching networks and
tuners. Network N
1
includes a matching network at the
gate designed to match the fundamental frequency and an
output-matching network N
2
at the drain that was
designed to match the second-harmonic. In addition to
the matching networks, tuners were also included in both
N
1
and N
2
to optimize the performance of the frequency
doubler. A maximum conversion gain of 1.8dB was
achieved utilizing this topology.
Chen [87] developed a MESFET frequency doubler uti-
lizing lters and matching networks. A lowpass lter was
placed on the input of the circuit, which allows the funda-
mental frequency to pass through to the gate of the device,
and a highpass lter was placed on the output of the device
to allow the desired second harmonic to pass. A matching
network designed to match the second-harmonic frequency
was placed in series with the highpass lter. Utilizing this
topology, Chen achieved 8dB of conversion gain.
Borg [95] has developed BJT frequency doubler designs
utilizing transmission lines and stubs. In one of these, a 50
transmission line is placed on the input of the circuit, and
short-circuited stubs are employed on the output of the
device. This design produces 2.5 dB of conversion gain.
Rauscher [93] provides an FET frequency doubler utiliz-
ing transmission lines and stubs as well. On the input of
the device, transmission lines are utilized to form imped-
ance transformations and an open-circuited stub. On the
output, they are utilized to provide an open-circuited stub
at the fundamental frequency. Rauschers data show that
0.5 dB of conversion gain was achieved in this design.
Stancliff [91] and Gilmore [92] determine optimal net-
works utilizing load-line analysis for their FET multiplier
designs. Using the I
ds
V
ds
curves, they employ fundamen-
tal load-line analysis to demonstrate the output charac-
teristics for a fundamental frequency open-circuited load
line placed on the output of the FET. Stancliff utilizes this
approach in a balanced conguration, whereas Gilmore
uses it for the development of a single-ended multiplier.
Various authors have used computer optimization tech-
niques for generalized large-signal device models to de-
velop frequency multipliers [106,108]. El-Rabaie [108]
uses a harmonic balance analysis technique to optimize
a MESFET frequency doubler utilizing a large-signal ME-
SFET device model. This technique determines the termi-
nating impedance value that should be presented to the
multiplier for optimum performance, while the approach
utilized by Guo [106] determines optimum bias voltages
and optimum load impedances.
Le [88] utilizes experimental techniques based on stub
tuner measurements to design frequency multipliers. In
this approach, load-pull measurements are performed to
measure impedances at various harmonics at various bias
voltages, and utilizing these data, frequency multipliers
are designed optimizing conversion gain and efciency.
Le uses this approach in the development of a frequen-
cy tripler, which provided a conversion gain of 2.4dB.
Single-ended designs using the previously mentioned
design techniques have exhibited excellent performance.
Conversion gains approaching 9 dB, harmonic suppression
exceeding 40 dBc, and bandwidths approaching 35% have
been reported [140,142,168]. A significant drawback of
some single-ended designs is the potentially large size
constraints required by matching networks and harmonic
terminating stubs. Long stubs of lengths approaching l/4
are commonly used. Even though the performance of fre-
quency multipliers using these design techniques is ex-
cellent, they are unsuitable for applications where size
constraints are specied. In certain cases, however, it has
been shown that discrete networks are feasible for signif-
icant size reduction.
4.2. A Unied Design Technique
Existing frequency multiplier design techniques are pre-
sented in the previous sections. While these approaches
sufce to produce multipliers that work, they are not nec-
essarily efcient in that proper synthesis of N
1
and N
2
can
yield significant improvements in performance as mea-
sured by conversion gain. In this section, a consistent de-
sign technique is proposed for the design of active
frequency multipliers, using the topology shown in Fig.
42 stemming from research on terminating-impedance ef-
fects on active devices.
Because of the extraordinary complexity of nonlinear
circuit problems, it is proposed that the technique, while
heavily reliant on experimental measurements, be based
on in-depth computer-aided design. From a perusal of the
literature, there appears to be little discussion on this
topic for active multipliers other than an occasional ref-
erence to power limitation in overdriving the drain in
MESFET/HEMT realizations. As with any such active
design, the rst step requires the selection of an active
device possessing the appropriate performance character-
istics [113], and particularly, in this case, developing ac-
curate nonlinear computer oriented device models. (In the
present case, a particular device on hand has been select-
ed for convenience.) Here, for example, we consider the
effects of each devices nonlinearity (e.g., C
gs
, C
gd
, g
ds
, I
ds
,
V
gs
, V
ds
) on augmenting a particular device harmonic [97].
At this point the nonlinear device model should be accu-
rately developed, based on both DC and AC characteris-
tics, to match the measured performance of the transistor
[48,109,146].
The next step requires utilizing the device model and/or
measured data to determine optimum bias points and in-
put power levels, using both static and P
in
versus P
out
data. Examples of this process may be found in previous
publications [97,147]. At this stage, it is important to de-
velop the requirements on the termination networks
N
1
and N
2
of Fig. 39 leading to optimum multiplier per-
formance. This process requires the use of extensive
Synthesis of
Z
N1
,Z
N2
Device
characteristics
Termination
matrix
determination
Z
N1
,Z
N2
Bias point and
input power
level
Figure 42. Topology of active microwave multiplier.
Figure 43. Simulated output power of
FHX35LG HEMT versus V
gs
P
in
0 dBm;
V
ds
3V; f 3 GHz.
Figure 44. Simulated output of the sec-
ond-harmonic versus V
ds
for FHX35LG
HEMT P
in
0 dBm; f 3 GHz.
Figure 45. Simulated conversion gain of
gs
V
ds
3 V;
f 3 GHz.
Figure 46. Simulated conversion gain of
gs
V
ds
3 V;
f 3GHz.
computer analysis to be efcient timewise, although, as
has been done by several researchers [88,108], some lim-
ited results can be achieved by extensive time-consuming
measurements. As mentioned previously, El-Rabaie [108]
and Le [88] used computer optimization of generalized
nonlinear models to optimize frequency multipliers. The
outcome of this process is the prescribed driving-point re-
sponses for networks N
1
and N
2
when terminated in R
g
and R
L
, respectively, where R
g
is the source resistance and
R
L
is the load terminating impedance.
Figure 47. Simulated output power versus
input power of FHX35LG V
gs
V
p
0:7 V; V
ds
3 V; f 3GHz.
Table 7. Doubler Simulations with Ideal Transmission Lines (V
gs
0.7V, P
in
0dBm, V
ds
3V)
Output Power (dBm)
a
Input
Network (O)
a,b
Output
Network (O)
a,b
:
50
50
50
_
_
_
_
_
_
_
_
0
50
50
_
_
_
_
_
_
_
_
1
50
50
_
_
_
_
_
_
_
_
0
50
1
_
_
_
_
_
_
_
_
1
50
1
_
_
_
_
_
_
_
_
50
50
0
_
_
_
_
_
_
_
_
50
50
1
_
_
_
_
_
_
_
_
0
50
0
_
_
_
_
_
_
_
_
1
50
0
_
_
_
_
_
_
_
_
50
50
50
_
_
_
_
_
_
_
_
5:96
0:9
14:7
_
_
_
_
_
_
_
_
217
0:3
221
_
_
_
_
_
_
_
_
210
0:7
231
_
_
_
_
_
_
_
_
215
0:2
270
_
_
_
_
_
_
_
_
208
0:4
270
_
_
_
_
_
_
_
_
5:5
3:9
232
_
_
_
_
_
_
_
_
4:1
0:3
237
_
_
_
_
_
_
_
_
216
3:3
270
_
_
_
_
_
_
_
_
209
4:2
270
_
_
_
_
_
_
_
_
50
0
50
_
_
_
_
_
_
_
_
10:5
4:5
17:9
_
_
_
_
_
_
_
_
213
5:4
215
_
_
_
_
_
_
_
_
207
3:9
224
_
_
_
_
_
_
_
_
211
6
270
_
_
_
_
_
_
_
_
204
5:2
270
_
_
_
_
_
_
_
_
10:2
1:8
225
_
_
_
_
_
_
_
_
8:7
6:1
232
_
_
_
_
_
_
_
_
212
2:5
270
_
_
_
_
_
_
_
_
206
0:1
270
_
_
_
_
_
_
_
_
50
0
0
_
_
_
_
_
_
_
_
8:7
2:5
12:6
_
_
_
_
_
_
_
_
215
3:2
219
_
_
_
_
_
_
_
_
208
2
232
_
_
_
_
_
_
_
_
213
4:3
270
_
_
_
_
_
_
_
_
205
2:8
270
_
_
_
_
_
_
_
_
8:3
0:7
229
_
_
_
_
_
_
_
_
6:9
4:3
235
_
_
_
_
_
_
_
_
213
0:1
270
_
_
_
_
_
_
_
_
207
0:9
270
_
_
_
_
_
_
_
_
50
50
0
_
_
_
_
_
_
_
_
5:4
2
18:2
_
_
_
_
_
_
_
_
218
1:4
213
_
_
_
_
_
_
_
_
211
2:5
237
_
_
_
_
_
_
_
_
216
2:3
270
_
_
_
_
_
_
_
_
208
2:3
270
_
_
_
_
_
_
_
_
3:4
4:1
220
_
_
_
_
_
_
_
_
3:4
2:1
246
_
_
_
_
_
_
_
_
217
3:6
270
_
_
_
_
_
_
_
_
209
5:3
270
_
_
_
_
_
_
_
_
50
1
50
_
_
_
_
_
_
_
_
2:7
4:4
19:8
_
_
_
_
_
_
_
_
221
3:7
227
_
_
_
_
_
_
_
_
213
4:1
239
_
_
_
_
_
_
_
_
219
4:1
270
_
_
_
_
_
_
_
_
211
3:8
270
_
_
_
_
_
_
_
_
2:3
6:5
235
_
_
_
_
_
_
_
_
0:6
4:2
246
_
_
_
_
_
_
_
_
220
6
270
_
_
_
_
_
_
_
_
212
7
270
_
_
_
_
_
_
_
_
50
1
1
_
_
_
_
_
_
_
_
4:7
2:7
23:4
_
_
_
_
_
_
_
_
219
3:2
219
_
_
_
_
_
_
_
_
211
2:4
235
_
_
_
_
_
_
_
_
217
5
270
_
_
_
_
_
_
_
_
209
2:6
270
_
_
_
_
_
_
_
_
4:3
4:9
237
_
_
_
_
_
_
_
_
2:6
2:6
238
_
_
_
_
_
_
_
_
217
4:8
270
_
_
_
_
_
_
_
_
210
4:9
270
_
_
_
_
_
_
_
_
50
50
1
_
_
_
_
_
_
_
_
3
4:3
15:9
_
_
_
_
_
_
_
_
221
4
222
_
_
_
_
_
_
_
_
212
4:2
235
_
_
_
_
_
_
_
_
218
1:8
270
_
_
_
_
_
_
_
_
210
2
270
_
_
_
_
_
_
_
_
2:2
8:8
236
_
_
_
_
_
_
_
_
1:2
1:6
232
_
_
_
_
_
_
_
_
220
8:2
270
_
_
_
_
_
_
_
_
212
8:5
270
_
_
_
_
_
_
_
_
a
At
f
0
2f
0
3f
0
_
_
_
_
_
_
_
_
.
b
The nal step (Fig. 42) involves the synthesis of Z
N
1
and Z
N
2
to realize the prescribed impedances, where
Z
N
1
and Z
N
2
are the respective driving point impedances
of N
1
and N
2
.
4.2.1. Illustration of Unied Design Technique. Here we
describe the design of an experimental frequency doubler
based on the approach described above, utilizing a Fujitsu
FHX35LG HEMT transistor. This transistor was modeled
Table 8. Doubler Simulations with Ideal Transmission Lines (V
gs
0V, P
in
0dBm, V
ds
3V)
Output Power (dBm)
a
Input
Network (O)
a,b
Output
Network (O)
a,b
:
50
50
50
_
_
_
_
_
_
_
_
0
50
50
_
_
_
_
_
_
_
_
1
50
50
_
_
_
_
_
_
_
_
0
50
1
_
_
_
_
_
_
_
_
1
50
1
_
_
_
_
_
_
_
_
50
50
0
_
_
_
_
_
_
_
_
50
50
1
_
_
_
_
_
_
_
_
0
50
0
_
_
_
_
_
_
_
_
1
50
0
_
_
_
_
_
_
_
_
50
50
50
_
_
_
_
_
_
_
_
12:5
10:1
13:9
_
_
_
_
_
_
_
_
211
11:3
219
_
_
_
_
_
_
_
_
206
2
217
_
_
_
_
_
_
_
_
208
11
270
_
_
_
_
_
_
_
_
203
3:3
270
_
_
_
_
_
_
_
_
11:9
13:2
232
_
_
_
_
_
_
_
_
11:1
10:3
235
_
_
_
_
_
_
_
_
209
14:2
270
_
_
_
_
_
_
_
_
204
5
270
_
_
_
_
_
_
_
_
50
0
50
_
_
_
_
_
_
_
_
14:8
13:8
5:6
_
_
_
_
_
_
_
_
209
11:8
211
_
_
_
_
_
_
_
_
205
3:2
214
_
_
_
_
_
_
_
_
207
11:2
270
_
_
_
_
_
_
_
_
202
3
270
_
_
_
_
_
_
_
_
14:2
18:7
223
_
_
_
_
_
_
_
_
13:2
13:9
226
_
_
_
_
_
_
_
_
208
14:7
270
_
_
_
_
_
_
_
_
203
0:2
270
_
_
_
_
_
_
_
_
50
0
0
_
_
_
_
_
_
_
_
13:7
11:6
10:4
_
_
_
_
_
_
_
_
210
19:8
216
_
_
_
_
_
_
_
_
205
1:3
214
_
_
_
_
_
_
_
_
207
19:5
270
_
_
_
_
_
_
_
_
202
0:6
270
_
_
_
_
_
_
_
_
13:2
15:7
228
_
_
_
_
_
_
_
_
12:3
13:9
231
_
_
_
_
_
_
_
_
208
22:4
270
_
_
_
_
_
_
_
_
204
2
270
_
_
_
_
_
_
_
_
50
50
0
_
_
_
_
_
_
_
_
12:4
10
19:3
_
_
_
_
_
_
_
_
211
9:3
213
_
_
_
_
_
_
_
_
206
2:2
222
_
_
_
_
_
_
_
_
208
10:3
270
_
_
_
_
_
_
_
_
203
3:8
270
_
_
_
_
_
_
_
_
11:9
12:6
224
_
_
_
_
_
_
_
_
10:9
10:6
243
_
_
_
_
_
_
_
_
210
12:8
270
_
_
_
_
_
_
_
_
204
5
270
_
_
_
_
_
_
_
_
50
1
50
_
_
_
_
_
_
_
_
10:9
11:6
19:4
_
_
_
_
_
_
_
_
212
11:6
226
_
_
_
_
_
_
_
_
206
6:1
222
_
_
_
_
_
_
_
_
210
12:4
270
_
_
_
_
_
_
_
_
204
8:2
270
_
_
_
_
_
_
_
_
10:3
14:4
236
_
_
_
_
_
_
_
_
9:4
12:6
242
_
_
_
_
_
_
_
_
211
14:1
270
_
_
_
_
_
_
_
_
205
8:5
270
_
_
_
_
_
_
_
_
50
1
1
_
_
_
_
_
_
_
_
12:1
10:7
21:4
_
_
_
_
_
_
_
_
211
13
215
_
_
_
_
_
_
_
_
205
1:3
217
_
_
_
_
_
_
_
_
209
13:9
270
_
_
_
_
_
_
_
_
203
3:1
270
_
_
_
_
_
_
_
_
11:6
15:8
226
_
_
_
_
_
_
_
_
10:6
11:7
246
_
_
_
_
_
_
_
_
210
15:7
270
_
_
_
_
_
_
_
_
204
4:3
270
_
_
_
_
_
_
_
_
50
50
1
_
_
_
_
_
_
_
_
10:9
13:3
19:8
_
_
_
_
_
_
_
_
212
10:4
228
_
_
_
_
_
_
_
_
206
5:5
220
_
_
_
_
_
_
_
_
210
9:5
270
_
_
_
_
_
_
_
_
204
6:4
270
_
_
_
_
_
_
_
_
10:3
16:8
239
_
_
_
_
_
_
_
_
9:5
11:6
241
_
_
_
_
_
_
_
_
211
14:5
270
_
_
_
_
_
_
_
_
205
9:8
270
_
_
_
_
_
_
_
_
a
At
f
0
2f
0
3f
0
_
_
_
_
_
_
_
_
.
b
Figure 48. Transmission magnitude for in-
put network Z
N1
.
in a previous section where measured and modeled data
were presented showing the accuracy of the nonlinear
model subsequent to performing the rst step described
above.
We need to determine the optimum bias points and
input power levels from either measured or modeled data.
Figures 4347 show simulated data for various bias condi-
tions and input power levels of the FHX35LG transistor.
Figure 43 shows the simulated output power at 3GHz
versus the gate-to-source voltage V
gs
at the fundamental
frequency and the second-harmonic frequency, Fig. 44
shows the simulated output power at the second-harmon-
ic frequency versus the drain-to-source voltage V
ds
, Figs. 45
and 46 show the conversion gain at the second-harmonic
versus V
gs
for various input power levels, and Fig. 47 shows
the simulated output power versus input power. Figures
43, 45, and 46 show that good second-harmonic generation
occurs for V
gs
0Vand V
gs
V
p
0.7V. However, in the
present case, the conversion gain is greater by approxi-
mately 9dB ( 1dB vs. 10dB) when operating at V
gs
V
p
with P
in
0dBm (Fig. 46) than when operating at V
gs
0V. The results indicate that the optimum bias and input
power values for the doubler are V
gs
V
p
0.7Vand P
in
0dBm.
The next step requires the generation of matrix tables
for the design of a frequency doubler operating at 3 GHz
input. These matrix tables represent the simulated output
powers of the HEMT frequency doubler for various com-
binations of the input and output impedances (Z
N
1
and
Z
N
2
) presented to the HEMT. In this case extensive ter-
minating tables were generated for both V
gs
0 V and V
gs
V
p
0.7 V [79]. Several matrix tables are shown in
Tables 14.
Tables 1 and 2 show the output power simulations
where lumped elements (not always practical values)
were utilized to present the various impedances to the
Table 9. Doubler Simulations with Microstrip Transmission Lines (V
gs
0V, P
in
0dBm, V
ds
3V)
Output Power (dBm)
a
Input
Network (O)
a,b
Output
Network (O)
a,b
:
50
50
50
_
_
_
_
_
_
_
_
0
50
50
_
_
_
_
_
_
_
_
1
50
50
_
_
_
_
_
_
_
_
0
50
1
_
_
_
_
_
_
_
_
1
50
1
_
_
_
_
_
_
_
_
50
50
0
_
_
_
_
_
_
_
_
50
50
1
_
_
_
_
_
_
_
_
0
50
0
_
_
_
_
_
_
_
_
1
50
0
_
_
_
_
_
_
_
_
50
50
50
_
_
_
_
_
_
_
_
5:96
0:9
14:7
_
_
_
_
_
_
_
_
27:1
0:7
26:3
_
_
_
_
_
_
_
_
10:4
0:9
36:2
_
_
_
_
_
_
_
_
25
0:4
52:9
_
_
_
_
_
_
_
_
17:3
0:8
60:1
_
_
_
_
_
_
_
_
5:6
5:1
26:9
_
_
_
_
_
_
_
_
4
0:6
37:7
_
_
_
_
_
_
_
_
26:1
4:3
41:8
_
_
_
_
_
_
_
_
18:9
5:2
54:3
_
_
_
_
_
_
_
_
50
0
50
_
_
_
_
_
_
_
_
10:7
4:3
10:2
_
_
_
_
_
_
_
_
27:4
5:4
22:6
_
_
_
_
_
_
_
_
22
4:5
21
_
_
_
_
_
_
_
_
20:5
8:6
42:8
_
_
_
_
_
_
_
_
13:5
6:4
61
_
_
_
_
_
_
_
_
10:5
0:3
24
_
_
_
_
_
_
_
_
9
7:2
32
_
_
_
_
_
_
_
_
21:2
1:3
37:3
_
_
_
_
_
_
_
_
15:6
0:4
41:8
_
_
_
_
_
_
_
_
50
0
0
_
_
_
_
_
_
_
_
8:4
2:8
8:7
_
_
_
_
_
_
_
_
24:5
3:2
22
_
_
_
_
_
_
_
_
17:6
2:1
36:8
_
_
_
_
_
_
_
_
22:2
5:5
46
_
_
_
_
_
_
_
_
15
4:6
73:7
_
_
_
_
_
_
_
_
8
2
21:3
_
_
_
_
_
_
_
_
5:9
6:8
30:4
_
_
_
_
_
_
_
_
23:6
0:9
35:6
_
_
_
_
_
_
_
_
17
2:2
47
_
_
_
_
_
_
_
_
50
50
0
_
_
_
_
_
_
_
_
5:8
1:3
17
_
_
_
_
_
_
_
_
27:4
0:2
29:1
_
_
_
_
_
_
_
_
20
1:7
38:1
_
_
_
_
_
_
_
_
23
1
55:2
_
_
_
_
_
_
_
_
17:7
0:2
74
_
_
_
_
_
_
_
_
5:5
5
27:6
_
_
_
_
_
_
_
_
3:7
0:2
43:1
_
_
_
_
_
_
_
_
18
5:6
33:5
_
_
_
_
_
_
_
_
19:2
5:7
47:9
_
_
_
_
_
_
_
_
50
1
50
_
_
_
_
_
_
_
_
3:1
3:9
18:3
_
_
_
_
_
_
_
_
28:4
3:6
43:8
_
_
_
_
_
_
_
_
28:4
3:6
43:8
_
_
_
_
_
_
_
_
28:2
3
64:3
_
_
_
_
_
_
_
_
20:1
2:9
66:9
_
_
_
_
_
_
_
_
2:9
7:1
28:1
_
_
_
_
_
_
_
_
0:9
3:3
50:6
_
_
_
_
_
_
_
_
30
6:4
43:2
_
_
_
_
_
_
_
_
21:3
7:6
53
_
_
_
_
_
_
_
_
50
1
1
_
_
_
_
_
_
_
_
5:7
1:1
16:5
_
_
_
_
_
_
_
_
27:6
1
30:2
_
_
_
_
_
_
_
_
19:9
1
44:2
_
_
_
_
_
_
_
_
25:7
0:5
55:4
_
_
_
_
_
_
_
_
17:8
0:1
60:5
_
_
_
_
_
_
_
_
5:5
5:1
29:2
_
_
_
_
_
_
_
_
3:5
0
38:8
_
_
_
_
_
_
_
_
26:4
4:5
43:8
_
_
_
_
_
_
_
_
19
4:9
51:8
_
_
_
_
_
_
_
_
50
50
1
_
_
_
_
_
_
_
_
2:9
5:2
16:4
_
_
_
_
_
_
_
_
35:5
5
29
_
_
_
_
_
_
_
_
28:3
4:8
37:1
_
_
_
_
_
_
_
_
28:3
4:2
50:3
_
_
_
_
_
_
_
_
20:2
3:8
54:5
_
_
_
_
_
_
_
_
2:3
10:1
35:4
_
_
_
_
_
_
_
_
0:8
4:2
31:4
_
_
_
_
_
_
_
_
29:5
9:7
47:5
_
_
_
_
_
_
_
_
21:6
9:7
51:9
_
_
_
_
_
_
_
_
a
At
f
0
2f
0
3f
0
_
_
_
_
_
_
_
_
.
b
0short circuit; N open circuit.
input and output ports of the HEMT for V
gs
0 V and V
gs
V
p
. As an example, Table 2 shows an analysis with the
HEMT biased at V
gs
0 V. The table illustrates the wide
variation in the conversion gain based on resistive termi-
nation and polezero placement for both N
1
(Z
N
1
) as the
input network and N
2
(Z
N
2
) as the output network. In
particular, it is seen that if the device is driven from an N
1
that admits a real 50 ohmimpedance presented to the gate
and is terminated in a real 50 ohm impedance for N
2
seen
from the drain, then the conversion gain will have a value
of 10.1dB for operation as a doubler or 13.9 dB as a
tripler, with due consideration of unwanted harmonics.
However, if N
1
presents an impedance to the gate of the
HEMT of 50 at f
0
, a pole at 2f
0
, and 50 at 3f
0
, and N
2
presents a pole f
0
, 50 at 2f
0
, and a pole at 3f
0
, then the
conversion gain increases 8.4dB to a value of 1.7 dB.
In efforts to realize impedances with transmission
lines, ideal transmission lines were used to present the
various ideal impedances to the HEMT, without consider-
ing losses, to obtain a best-case scenario before proceeding
to practical microstrip lines. Tables 7 and 8 show the sim-
ulations of the output power of the doubler for V
gs
0V
and V
gs
V
p
, utilizing ideal transmission lines. Variations
in the conversion gain, as observed in the previous matrix
simulation tables, are observed in the simulations that
utilize ideal transmission lines as well.
Doubler simulations utilizing practical microstrip lines
are considered next. Figures 4448 show simulations uti-
lizing microstrip lines for V
gs
0 V and V
gs
V
p
for input
powers of 0 and 4dBm.
A perusal of the matrix tables (specifically Tables 912)
provides requirements for both input and output network
impedances to provide optimal conversion gain perfor-
mance for a frequency doubler. In Table 9, the optimum
conversion gain is shown to be 8.6dB (row 2, column 4),
where the required input termination is a short circuit at
gs
0V, P
in
0dBm, V
ds
3V)
Output Power (dBm)
a
Input
Network (O)
a,b
Output
Network (O)
a,b
:
50
50
50
_
_
_
_
_
_
_
_
0
50
50
_
_
_
_
_
_
_
_
1
50
50
_
_
_
_
_
_
_
_
0
50
1
_
_
_
_
_
_
_
_
1
50
1
_
_
_
_
_
_
_
_
50
50
0
_
_
_
_
_
_
_
_
50
50
1
_
_
_
_
_
_
_
_
0
50
0
_
_
_
_
_
_
_
_
1
50
0
_
_
_
_
_
_
_
_
50
50
50
_
_
_
_
_
_
_
_
12:5
10:1
13:9
_
_
_
_
_
_
_
_
20:2
11:4
26:3
_
_
_
_
_
_
_
_
15:1
2:5
25:4
_
_
_
_
_
_
_
_
22:9
10:9
49:3
_
_
_
_
_
_
_
_
12:5
4
55:4
_
_
_
_
_
_
_
_
12
13:9
28:9
_
_
_
_
_
_
_
_
11:1
10
33:9
_
_
_
_
_
_
_
_
19:3
15:1
39:1
_
_
_
_
_
_
_
_
14:3
6
36:3
_
_
_
_
_
_
_
_
14:7
12:5
8:4
_
_
_
_
_
_
_
_
18:4
13:1
18:4
_
_
_
_
_
_
_
_
14:4
1:8
25:6
_
_
_
_
_
_
_
_
21:3
10:4
41
_
_
_
_
_
_
_
_
11:1
2:8
52
_
_
_
_
_
_
_
_
14:2
17:1
22
_
_
_
_
_
_
_
_
13:2
10:6
2:8
_
_
_
_
_
_
_
_
17:5
17
31:8
_
_
_
_
_
_
_
_
13:6
2:5
34:5
_
_
_
_
_
_
_
_
50
0
0
_
_
_
_
_
_
_
_
13:6
11:5
9:3
_
_
_
_
_
_
_
_
19:2
19
22:4
_
_
_
_
_
_
_
_
14:6
0:5
21:8
_
_
_
_
_
_
_
_
21:9
15:3
45
_
_
_
_
_
_
_
_
11:7
0:4
59:6
_
_
_
_
_
_
_
_
13:2
17:1
24:8
_
_
_
_
_
_
_
_
12:3
11:2
28:8
_
_
_
_
_
_
_
_
18:3
22:8
35:3
_
_
_
_
_
_
_
_
13:9
3
32:3
_
_
_
_
_
_
_
_
50
50
0
_
_
_
_
_
_
_
_
12:6
10:3
17:5
_
_
_
_
_
_
_
_
20:2
11:3
29:7
_
_
_
_
_
_
_
_
15
2:6
29:5
_
_
_
_
_
_
_
_
22:9
11:1
53
_
_
_
_
_
_
_
_
12:3
4
53:4
_
_
_
_
_
_
_
_
12:1
13:7
33:9
_
_
_
_
_
_
_
_
11:1
10:4
36:5
_
_
_
_
_
_
_
_
19:3
14:7
42:8
_
_
_
_
_
_
_
_
14:2
5:9
41
_
_
_
_
_
_
_
_
50
1
50
_
_
_
_
_
_
_
_
11:2
11:4
18:9
_
_
_
_
_
_
_
_
21:6
11:6
32:4
_
_
_
_
_
_
_
_
15:6
6:8
32:3
_
_
_
_
_
_
_
_
24:4
11:9
54:6
_
_
_
_
_
_
_
_
13:1
8:5
60:4
_
_
_
_
_
_
_
_
10:6
14:6
32:7
_
_
_
_
_
_
_
_
9:7
12:1
39:8
_
_
_
_
_
_
_
_
20:7
14:8
45:2
_
_
_
_
_
_
_
_
14:7
9:6
42:6
_
_
_
_
_
_
_
_
50
1
1
_
_
_
_
_
_
_
_
12:7
9:4
13:5
_
_
_
_
_
_
_
_
20:2
11:1
26:1
_
_
_
_
_
_
_
_
14:8
1
23:2
_
_
_
_
_
_
_
_
22:9
11:2
50:2
_
_
_
_
_
_
_
_
12:1
2:9
52:2
_
_
_
_
_
_
_
_
12:2
13:1
29:4
_
_
_
_
_
_
_
_
11:2
10:5
33:1
_
_
_
_
_
_
_
_
19:3
14:3
39:2
_
_
_
_
_
_
_
_
13:9
4
34
_
_
_
_
_
_
_
_
50
50
1
_
_
_
_
_
_
_
_
11
12:1
18:8
_
_
_
_
_
_
_
_
25
16:4
45:2
_
_
_
_
_
_
_
_
15:8
6:1
27:7
_
_
_
_
_
_
_
_
24:4
10:9
57
_
_
_
_
_
_
_
_
13:3
8:3
55:1
_
_
_
_
_
_
_
_
10:5
16:2
35:6
_
_
_
_
_
_
_
_
9:6
11:9
38:4
_
_
_
_
_
_
_
_
20:7
14:3
47:3
_
_
_
_
_
_
_
_
15
10:2
39:5
_
_
_
_
_
_
_
_
a
At
f
0
2f
0
3f
0
_
_
_
_
_
_
_
_
.
b
the second-harmonic frequency and the output network
consists of an open-circuit termination at the third-har-
monic frequency along with a short-circuit termination at
the fundamental.
After the optimal impedances (Z
N
1
and Z
N
2
) have been
determined, the impedances have to be synthesized in or-
der to construct a physical frequency doubler to evaluate
the efcacy of the results. In this analysis, the synthesis is
performed using microstrip transmission lines. Figures 48
and 49 show the transmission response of the input
network (short circuit at the second-harmonic) and the
output network (short circuit at the fundamental and open
circuit at the third harmonic), respectively. The measured
and simulated responses for |S
21
| indicate that the de-
sired short-circuit effect is established at the second-har-
monic (6 GHz) for Z
N
1
as shown in Fig. 48, and similarly
for the measured and modeled response of Z
N
2
in Fig. 49.
The complete experimental frequency doubler was re-
alized on 50 m (20mil) duroid, and its response is shown in
Figs. 50 and 51. Figure 50 shows the conversion gain of
the doubler using the technique outlined here, and Fig. 51
shows the harmonic suppression. Figure 50 shows that
the maximum conversion gain is 8.5dB with a 3 dB
bandwidth of approximately 8% and with harmonic sup-
pression greater than 20dBc.
Conventional doubler designs have employed a short-
circuit termination at the second-harmonic frequency on
the input network along with a short-circuit termination
at the fundamental on the output network. This conven-
tional design approach (row 2, column 2 of Table 9) shows
the simulated conversion gain as 3.2 dB less than the op-
timal case outlined by this new approach. For comparison,
a frequency doubler utilizing the conventional approach
mentioned is developed on 20mil duroid as well. The
gs
0.7V, P
in
4dBm, V
ds
3V)
Output Power (dBm)
a
Input
Network (O)
a,b
Output
Network (O)
a,b
:
50
50
50
_
_
_
_
_
_
_
_
0
50
50
_
_
_
_
_
_
_
_
50
0
0
_
_
_
_
_
_
_
_
0
50
0
_
_
_
_
_
_
_
_
0
50
50
_
_
_
_
_
_
_
_
50
50
1
_
_
_
_
_
_
_
_
1
50
1
_
_
_
_
_
_
_
_
0
50
1
_
_
_
_
_
_
_
_
1
50
0
_
_
_
_
_
_
_
_
50
50
50
_
_
_
_
_
_
_
_
0:5
6:7
21:3
_
_
_
_
_
_
_
_
32:7
6:1
34:3
_
_
_
_
_
_
_
_
0
10:8
33:3
_
_
_
_
_
_
_
_
31:6
10
48
_
_
_
_
_
_
_
_
25:1
6:8
46:6
_
_
_
_
_
_
_
_
1:5
4:9
43:4
_
_
_
_
_
_
_
_
22:8
5:1
65:9
_
_
_
_
_
_
_
_
35:9
4:8
60:6
_
_
_
_
_
_
_
_
24:2
11:1
60:2
_
_
_
_
_
_
_
_
50
0
50
_
_
_
_
_
_
_
_
6
6
13:7
_
_
_
_
_
_
_
_
26:9
1
26:6
_
_
_
_
_
_
_
_
5:8
4:2
25:5
_
_
_
_
_
_
_
_
25:9
3:2
39:4
_
_
_
_
_
_
_
_
20:8
1
34:5
_
_
_
_
_
_
_
_
4:5
3
36:2
_
_
_
_
_
_
_
_
18:2
1:5
61:9
_
_
_
_
_
_
_
_
29:5
4:3
49
_
_
_
_
_
_
_
_
19:9
5:2
46:3
_
_
_
_
_
_
_
_
50
0
0
_
_
_
_
_
_
_
_
4
11:8
28:2
_
_
_
_
_
_
_
_
29:9
2:2
28:6
_
_
_
_
_
_
_
_
2:7
7:4
27:3
_
_
_
_
_
_
_
_
28:9
41:6
6:4
_
_
_
_
_
_
_
_
22:8
3:6
41:6
_
_
_
_
_
_
_
_
1:5
0:3
37:3
_
_
_
_
_
_
_
_
20:4
1
72
_
_
_
_
_
_
_
_
32:7
0:8
50:2
_
_
_
_
_
_
_
_
22
7:9
52:9
_
_
_
_
_
_
_
_
50
50
0
_
_
_
_
_
_
_
_
0:2
7:1
23:7
_
_
_
_
_
_
_
_
33
6:1
34:9
_
_
_
_
_
_
_
_
0:1
10:6
32:7
_
_
_
_
_
_
_
_
31:9
9:5
45:8
_
_
_
_
_
_
_
_
25:4
7:6
43:8
_
_
_
_
_
_
_
_
1:9
5:6
53:8
_
_
_
_
_
_
_
_
23:1
6:1
77:4
_
_
_
_
_
_
_
_
36:3
4:4
65:1
_
_
_
_
_
_
_
_
24:5
11:6
54
_
_
_
_
_
_
_
_
50
1
50
_
_
_
_
_
_
_
_
2:4
10:1
26:2
_
_
_
_
_
_
_
_
35:8
9:4
39:7
_
_
_
_
_
_
_
_
2:8
13:4
36
_
_
_
_
_
_
_
_
34:7
12:8
50:7
_
_
_
_
_
_
_
_
27:7
10:1
50:6
_
_
_
_
_
_
_
_
4:6
9:1
57:5
_
_
_
_
_
_
_
_
25:6
9
75:2
_
_
_
_
_
_
_
_
39:1
8:2
69:5
_
_
_
_
_
_
_
_
26:8
13:9
60
_
_
_
_
_
_
_
_
50
1
1
_
_
_
_
_
_
_
_
0:2
7
23:1
_
_
_
_
_
_
_
_
33:1
6:7
37:2
_
_
_
_
_
_
_
_
0
10:8
35:8
_
_
_
_
_
_
_
_
32
10:1
50:2
_
_
_
_
_
_
_
_
25:3
7:1
49:6
_
_
_
_
_
_
_
_
2
5:7
46:2
_
_
_
_
_
_
_
_
23:3
6
68:7
_
_
_
_
_
_
_
_
36:5
5:4
66:1
_
_
_
_
_
_
_
_
24:4
11
58
_
_
_
_
_
_
_
_
50
50
1
_
_
_
_
_
_
_
_
2:6
11:1
25:1
_
_
_
_
_
_
_
_
35:9
10:9
38:5
_
_
_
_
_
_
_
_
3:2
15:8
45:3
_
_
_
_
_
_
_
_
35:1
15:3
57:6
_
_
_
_
_
_
_
_
27:7
11:1
46:5
_
_
_
_
_
_
_
_
4:7
9:7
39:3
_
_
_
_
_
_
_
_
25:6
9:7
62:9
_
_
_
_
_
_
_
_
39:2
10:4
58:3
_
_
_
_
_
_
_
_
27
15:8
62:1
_
_
_
_
_
_
_
_
a
At
f
0
2f
0
3f
0
_
_
_
_
_
_
_
_
.
b
0short circuit; N open circuit.
measured and simulated conversion gain for the HEMT
doubler utilizing this conventional approach is shown in
Fig. 52. The circuit is seen to have a conversion gain of
approximately 5dB around the center frequency of 3 GHz,
rising to 6.7 dB at 3.08 GHz. As indicated previously, the
conversion gain produced by the conventional design ap-
proach exhibits approximately 3dB less conversion gain
than doublers designed with the unied approach.
gs
0.7V, P
in
4dBm, V
ds
3V)
Output Power (dBm)
a
Input
Network (O)
a,b
Output
Network (O)
a,b
:
50
50
50
_
_
_
_
_
_
_
_
0
50
50
_
_
_
_
_
_
_
_
1
50
50
_
_
_
_
_
_
_
_
0
50
1
_
_
_
_
_
_
_
_
1
50
1
_
_
_
_
_
_
_
_
50
50
0
_
_
_
_
_
_
_
_
50
50
1
_
_
_
_
_
_
_
_
0
50
0
_
_
_
_
_
_
_
_
1
50
0
_
_
_
_
_
_
_
_
50
50
50
_
_
_
_
_
_
_
_
9:1
15:5
23:5
_
_
_
_
_
_
_
_
23:3
14:5
38:7
_
_
_
_
_
_
_
_
17:5
17:2
42:6
_
_
_
_
_
_
_
_
26
14:2
61:3
_
_
_
_
_
_
_
_
15
17:4
68:6
_
_
_
_
_
_
_
_
8:7
18:8
38:8
_
_
_
_
_
_
_
_
7:8
15:1
44
_
_
_
_
_
_
_
_
22:3
18:2
51:7
_
_
_
_
_
_
_
_
16:6
20:8
54
_
_
_
_
_
_
_
_
50
0
50
_
_
_
_
_
_
_
_
12:2
13:4
17:8
_
_
_
_
_
_
_
_
20:2
16:9
29:5
_
_
_
_
_
_
_
_
15:8
6:8
31
_
_
_
_
_
_
_
_
22:9
14:2
51:8
_
_
_
_
_
_
_
_
13:2
5:8
55:7
_
_
_
_
_
_
_
_
12
16:7
32:5
_
_
_
_
_
_
_
_
10:9
12:3
37:6
_
_
_
_
_
_
_
_
19:3
20:7
42:5
_
_
_
_
_
_
_
_
15
11:1
45:3
_
_
_
_
_
_
_
_
50
0
0
_
_
_
_
_
_
_
_
10:5
14
19:4
_
_
_
_
_
_
_
_
21:9
16:1
34:5
_
_
_
_
_
_
_
_
16:6
12:1
38:9
_
_
_
_
_
_
_
_
24:7
13:3
57:5
_
_
_
_
_
_
_
_
14:1
10:7
75:9
_
_
_
_
_
_
_
_
10:1
17:7
35:7
_
_
_
_
_
_
_
_
9:1
12:9
39
_
_
_
_
_
_
_
_
21
20
47:5
_
_
_
_
_
_
_
_
15:8
15:9
49:2
_
_
_
_
_
_
_
_
50
50
0
_
_
_
_
_
_
_
_
9:2
15:5
24:8
_
_
_
_
_
_
_
_
23:3
14:7
39:1
_
_
_
_
_
_
_
_
17:2
16:2
38:5
_
_
_
_
_
_
_
_
26:1
14:8
61:8
_
_
_
_
_
_
_
_
14:8
16:9
63
_
_
_
_
_
_
_
_
8:8
18:5
40:9
_
_
_
_
_
_
_
_
7:8
15:7
44:4
_
_
_
_
_
_
_
_
22:4
17:9
52:7
_
_
_
_
_
_
_
_
16:3
19:5
51:8
_
_
_
_
_
_
_
_
50
1
50
_
_
_
_
_
_
_
_
7:7
17:8
27:6
_
_
_
_
_
_
_
_
25:1
17:4
43:3
_
_
_
_
_
_
_
_
18:3
20:9
46:8
_
_
_
_
_
_
_
_
27:8
17:9
65
_
_
_
_
_
_
_
_
15:9
21:8
71:5
_
_
_
_
_
_
_
_
7:1
20:9
41:4
_
_
_
_
_
_
_
_
6:2
18:6
49:2
_
_
_
_
_
_
_
_
24:2
20:4
56:4
_
_
_
_
_
_
_
_
17:4
23:9
58:7
_
_
_
_
_
_
_
_
50
1
1
_
_
_
_
_
_
_
_
9:4
14:3
22:9
_
_
_
_
_
_
_
_
23:3
14:3
38:2
_
_
_
_
_
_
_
_
16:9
15:7
40:3
_
_
_
_
_
_
_
_
26:1
14:6
61:8
_
_
_
_
_
_
_
_
14:5
17
67
_
_
_
_
_
_
_
_
9
17:5
39:3
_
_
_
_
_
_
_
_
7:9
15:2
42:9
_
_
_
_
_
_
_
_
22:4
17:3
51:8
_
_
_
_
_
_
_
_
16:1
18:6
51:3
_
_
_
_
_
_
_
_
50
50
1
_
_
_
_
_
_
_
_
7:5
1:9
26:9
_
_
_
_
_
_
_
_
30:3
16:4
45:2
_
_
_
_
_
_
_
_
18:6
22:3
45:3
_
_
_
_
_
_
_
_
27:8
17:5
67:4
_
_
_
_
_
_
_
_
16:2
23
69:5
_
_
_
_
_
_
_
_
7
22:9
43:8
_
_
_
_
_
_
_
_
6:1
18:6
47
_
_
_
_
_
_
_
_
24:1
20:8
58:1
_
_
_
_
_
_
_
_
17:7
26:6
57:5
_
_
_
_
_
_
_
_
a
At
f
0
2f
0
3f
0
_
_
_
_
_
_
_
_
.
b
0
10
20
30
40
50
60
70
S
2
1

(
d
B
)
Frequency (GHz)
2 3 4 5 6 7 8 9 10 11 12 13
Simulated
Measured
Figure 49. Transmission magnitude for out-
put network Z
N2
.
4.3. Reector Method
Another single-ended design technique [93,95,104,109,
141145,168171] is based on the use of reector net-
works. This section presents examples of doubler designs
operating in the S and C frequency bands incorporating
such reector networks to provide optimized performance.
In this presentation, reector networks are employed si-
multaneously on both the input and output of HEMT-
based designs. In a common-source conguration, the in-
put reector network passes the fundamental frequency
but reects the desired higher-harmonic signal back into
the gate of the device at an optimum phase. The output
reector network passes the desired harmonic while
reecting the fundamental frequency back into the drain
of the device at the proper phase angle for maximizing
the conversion gain. Measured and simulated results are
given to strengthen this design philosophy.
4.3.1. Reector Networks. Numerous techniques exist
for the realization of frequency multipliers. All techniques
at radiofrequencies employ a nonlinear device to generate
the desired frequency multiple. The basic conguration of
the single-ended frequency multiplier realization is illus-
trated in Fig. 24. As mentioned previously, the input net-
work allows the fundamental frequency to pass through to
the gate of the transistor, in a common-source congura-
tion, while suppressing higher-harmonic frequencies.
Similarly, the output network suppresses the fundamen-
tal and other unwanted harmonics, while allowing the de-
sired harmonic to pass. The frequency multiplier reector
network design philosophy implemented in this section is
applied to an HEMT (Fujitsu FHXLG) frequency doubler
with a fundamental frequency of 3 GHz.
As stated above, a primary objective of the output and
input networks is to suppress select harmonics. In the
process of suppressing the undesired signals, it appears
that relatively little attention is given to the possibility
that the unwanted signals can be reected back into
the device from the input and output networks simulta-
neously. The nonlinearity of the device causes these har-
monics and the fundamental to mix with other frequency
Fundamental frequency (GHz)
C
o
n
v
e
r
s
i
o
n

g
a
i
n

(
d
B
)
9
8
7
6
5
4
3
2
1
0
2.8 2.9 3 3.1 3.2 3.3
Simulated
Measured
Figure 50. Conversion gain of HEMT doubler using the unied
technique (P
in
0 dBm, V
gs
0.7 V, V
ds
3.0V).
Figure 51. Harmonic suppression of HEMT
doubler using the unied technique (P
in
0 dBm, V
gs
0.7V, V
ds
3.0 V).
Figure 52. Conversion gain of HEMT dou-
bler using conventional design (P
in
0dBm,
V
gs
0.7 V, V
ds
3.0V).
l
2
(l
4
)
l
1
(l
3
) R
L
= 50 (R
g
= 50)
Z
in
2

out
( Z
in
1
,
in
)
Figure 53. Fundamental output (input) reector network.
components. This mixing process can either enhance or
degrade the signal at the desired second harmonic. There-
fore, it is important for the reected signal to be properly
phased, such that it interferes constructively with the de-
sired harmonic (second harmonic in the case of the fre-
quency doubler examples presented below). Thus, the
input and output networks of Fig. 24 can be designed in
such a way that in addition to their primary function of
ltering, they are reector networks meeting the above
criteria. Owing to the complexity in calculating the actual
effects of the reector networks, there has not been a sig-
nificant amount of analytical discussion on this topic until
2000 [157,168,169,171].
4.3.2. Consideration of Reection Phase Angle. As stat-
ed, the input and output networks of Fig. 24 should be
designed such that they are reector networks, in addition
to their primary function of ltering. The reector net-
works developed in this section are analyzed on a frequen-
cy doubler with a fundamental frequency of 3 GHz. For a
frequency doubler, the input network of Fig. 24 should be
designed to reect the second-harmonic back into the gate
of the HEMT at the proper phase angle for constructive
interference and optimum conversion gain. Similarly, the
output network is designed such that it reects the fun-
damental signal back into the drain of the HEMT at the
optimum phase. The network of Fig. 53 is a logical choice
for the output and input reector functions described
above, although it is not optimal in the input case. In
this gure, Z
in
2
; G
out
; l
1
; l
2
; R
L
and Z
in
1
; l
3
; l
4
; R
g
denote out-
put and input reector networks, respectively [157], and l
1
and l
3
are xed at a quarter wavelength of the fundamen-
tal frequency and a quarter-wavelength of the second-har-
monic frequency, respectively.
4.3.3. Effect of Reection Angle on Conversion Gain.
Optimization of the conversion gain of a HEMT (FHXLG)
doubler can be obtained by varying the reection angles
on both input and output, using l
4
and l
2
, respectively.
Computer analyses, substantiated by experimental mea-
surements, show that conversion gain variation of over 20
and 27 dB result by changes of l
4
and l
2
, respectively.
Maximum to minimum gain variations have been found to
occur for l
4
, varying from 0 to 2001 and l
2
varying from 0
to 1801.
4.4. Doubler Designs Based on Prior Analysis
It has been shown that optimum multiplier designs in
terms of conversion gain can be developed. These designs
are based on the proper synthesis of input and output
networks with the requisite transfer, input magnitude
jZ
in
2
j
, and phase jZ
in
2
j
. Narrow, medium, and wideband
designs have been demonstrated employing this approach
[136,157]. Figure 54 shows a wideband design employing
this technique.
4.5. Summary
This section has presented design techniques for single-
ended frequency multiplier designs. These techniques in-
corporate reector networks providing excellent perfor-
mance characteristics, which includes effective conversion
gain and harmonic suppression as demonstrated by the
results. These results show the improvement in conver-
sion gain using reector networks with proper phase an-
gles on the input and output networks simultaneously,
which are useful for narrowband and wideband applica-
tions. Because of bandwidth constraints imposed by the
use of single stubs, incorporating lters into the designs
achieves bandwidth extension and improves harmonic
suppression. This improvement in bandwidth and har-
monic suppression, however, comes at the expense of con-
version gain, as shown by the wideband designs. Another
advantage of these designs is that they are single-ended,
thus alleviating the requirement for complex baluns or
transformers.
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1958).
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MICROSTRIP CIRCUITS

Figure 2. Geometry of a stripline. The strip conductor is sand-

Figure 3. Electromagnetic eld distribution in a stripline. The

Figure 4. Geometry of a microstrip line. The conducting strip is

Figure 4. Block diagram of 26GHz MMIC receiver Model.

Figure 18. Antiseries diode pairs.

Figure 19. Antiparallel series-connected diodes.

(BIN) diodes, and high-elec-

0 V. These regions are identied as areas where the non-

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