Asynchronous Sequential Logic

Introduction
Introduction
I. Synchronous Sequential circuits :
The change of internal state occurs in response to synchronized clock pulses. The memory elements are clocked flip-flops.

II. Asynchronous Sequential circuits :

The change of internal state occurs where there is a change in input variable. The memory elements are either unclocked flip-flops or timing-delay elements.

The Huffman Model

Simplify the analysis and design of asynchronous sequential circuit. 1954, David A. Huffman. Huffman Model
Feedback delay :
A delay element is placed in each feedback line. All gates and other lines are assumed to have zero propagation delays.
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 Delay uncertainty : In a state change that involves 2 or more secondary variables, the variables can change value in arbitrary order. Fundamental mode : A primary input signal can change value only after the circuit has reached a stable state. Single input changes : Primary input signals are assumed to change value one at a time.
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Asynchronous Sequential Logic Block diagram of an asynchronous sequential circuit :

Inputs x1 x2 xn Secondary variables (present state) . . . y1 y2 . . . yk x1 x2 xn Combinational circuit . . . Y1 . Y2 . . Yk z1 z2 zm Excitation variables (next state) Outputs

Delay Delay Delay

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Asynchronous Sequential Logic

Analysis Procedure
Transition Table
Example :
x y1 Y1

Y2 y2 One input : x Two excitation variables : Y1 and Y2 (next state) Two secondary variables : y1 and y2 (present state)
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Asynchronous Sequential Logic Y1 = x y1 + x y2 Y2 = x y1 + x y2

x y1 y2 00 01 11 10 0 0 1 1 0

Y1 1 0 0 1 1 y1 y2

x 0 00 01 11 10 0 1 1 0

Y2 1 1 1 0 0 y1 y2

Y1Y2 0 1 01 01 10 10

00 00 01 11 11 11 10 00

Transition table
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Asynchronous Sequential Logic

The circled entries indicate a stable condition. An uncircled entry represents an unstable state. The effect of a change in the input variable :
x y1 y2 Y1Y2 0 1 1. Initial : x = 0 , y = 00 , Y = 00 2. y = 00 , x : 0 1 Y : 010 3. y = 00 01 , x = 1 Y = 01

00 00 01 00 01 01 11 11 11 10 00 01 01 10 10

Asynchronous Sequential Logic Total state : combine the internal state with input together .
Stable total state : y1 y2 x = 000, 011, 110, and 101. Unstable total state : y1 y2 x = 001, 010, 111, and 100.

State Table :

Present state 0 0 1 1 0 1 0 1

Next state x=0 x=1 0 1 0 1 0 1 0 1 0 0 1 1 1 1 0 0

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Asynchronous Sequential Logic

The procedure for obtaining a transition table :

1. Determine all feedback loops in the circuit. 2. Designate the output of each feedback loop with variable Yi and its corresponding input with yi for i = 1, 2, , k 3. Derive the Boolean functions for all Ys as a function of the external inputs and the ys. 4. Plot each Y function in a map. 5. Combine all the maps into one table. 6. Circle those values of Y that are equal to the value of y in the same row.

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Asynchronous Sequential Logic

Flow table :
A flow table is similar to a transition table except that the internal states are symbolized with letters rather than binary numbers. Example 1 :
x 0 a b c d a c c a 1 b b d d

a = 00 , b = 01 , c = 11 , d = 10 Primitive flow table : Only one stable state in each row.

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Asynchronous Sequential Logic Example 2 :

x1 x2 00 a b a ,0 a ,0 01 a ,0 a ,0 11 a ,0 b ,1 10 b ,0 b ,0

Two states : a , b Two inputs : x1 , x2 One output : z

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Asynchronous Sequential Logic

In order to obtain the circuit described by a flow table it is necessary to assign to each state a distinct binary value. x1 x2 01 11 0 0 0 1 x1 x2 01 11 0 0 0 1

y 0 1

00 0 0

10 1 1

y 0 1

00 0 0

10 0 0

Transition table

Output map

Y = x1 x2 + x1 y

z = x1 x2 y

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Asynchronous Sequential Logic

z

x1 x2 Y

Logic Diagram derived from the flow table in example2

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Asynchronous Sequential Logic

Race Condition :
A race condition is said to exit when two or more binary states change value in response to a change in an input variable. Because unequal delays a race condition may cause the state variables to change in unpredictable manner. Noncritical Race : the final stable state does not depend on the order in which the state variables change. Critical Race : the final stable state depends on the order in which the state variables change.

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Asynchronous Sequential Logic Example 3 : Noncritical race

x y1 y2 01 11 10 0 1 11 11 11 11 y1 y2 01 11 10 00 00 x 0 1 11 01 01 11 00 00

Start with y1 y2 x = 000, then x : 0 1 Possible transitions : 00 11 00 01 11 00 10 11

Start with y1 y2 x = 000, then x : 0 1 Possible transitions : 00 11 01 00 01 00 10 11 01

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Asynchronous Sequential Logic Example 4 : Critical race

x y1 y2 01 11 10 0 1 11 01 11 10 y1 y2 01 11 10 00 00 x 0 1 11 11 11 10 00 00

Start with y1 y2 x = 000, then x : 0 1 Possible transitions : 00 11 00 01 00 10

Start with y1 y2 x = 000, then x : 0 1 Possible transitions : 00 11 00 01 11 00 10

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Asynchronous Sequential Logic Races may be avoided by making a proper binary assignment to state variables. Only one state can change at any one time when a state transition occurs in the flow table. Races can be avoided by directing the circuit through intermediate unstable states with a unique state-variable change. When a circuit goes through a unique sequence of unstable states, it is said to have a cycle.

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Asynchronous Sequential Logic Examples of cycles

x y1 y2 01 11 10 0 1 01 11 10 10 y1 y2 01 11 10 00 00 x 0 1 01 11 11 10 00 00

Start with y1 y2 x = 000, then x : 0 1 00 01 11 10

Start with y1 y2 x = 000, then x : 0 1 00 01 11

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Asynchronous Sequential Logic Examples of cycles

x y1 y2 01 11 10 0 1 01 11 10 01 00 00

Unstable

Start with y1 y2 x = 000, then x : 0 1 00 01 11 10

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Asynchronous Sequential Logic

Stability Considerations
Example 5
y x1 x2 Y

The excitation function : Y = x1 x2 + x2 y

y 0 1 00 0 0 x1 x2 01 11 1 1 1 0 10 0 0

x1 x2 = 11 state transition 10101...

Transition table
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Asynchronous Sequential Logic

Circuit With Latches

Asynchronous sequential circuits can be implemented by employing a basic flip-flop commonly referred to as an SR latch. SR Latch
R (Reset) Q y

Q Y=Q

(Set) S

S (Set)

R (Reset)
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Asynchronous Sequential Logic The Boolean function for the output is Y = [( S + y ) + R ] = ( S + y ) R = S R + R Y The transition table :
y 0 1 00 0 1 SR 01 11 0 0 0 0 10 1 1

Transition table SR = 11, Q = Q = 0 SR = 10, Q = Y = 1 : set SR : 11 01 00 S:10Q=1 Q=Y=0 SR : 11 10 00 SR = 01, Q = Y = 0 : reset Q:01 R:10Q=Y=0
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Asynchronous Sequential Logic Going from SR=11 to SR=00 produces an unpredictable result. In normal operation, make sure that 1s are not applied to both S and R inputs simultaneously. The condition can be expressed by : SR = 0 Because SR + SR = S ( R + R ) = S reduce SR = S when SR = 0 Excitation function : Can be expressed as Y = S + R Y when SR = 0

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Asynchronous Sequential Logic

SR Latch
S (Set) Q y

Q Y=Q

R (Reset) y 0 1 00 1 1 SR 01 11 1 1 0 1

R (Reset)

S (Set)

10 0 0

Excitation function : Y = S + R Y when SR = 0

Transition table
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Asynchronous Sequential Logic

Analysis Example
x1 R1 Y1

S1 y2 y1 R2 x2 Y2

S2

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Asynchronous Sequential Logic The Boolean function for S and R S1 = x1 y2 S2 = x1 x2 R1 = x1 x2 R2 = x2 y1 Check the condition : S R = 0 S1 R1 = x1 y2 x1 x2 = 0 S2 R2 = x1 x2 x2 y1 = 0 Derive the excitation functions : ( Y = S + Ry ) Y1 = S1 + R1 y1 = x1 y2 + ( x1 + x2 ) y1 = x1 y2 + x1 y1 + x2 y1 Y2 = S2 + R2 y2 = x1 x2 + ( x2 + y1 ) y2 = x1 x2 + x2 y2 + y1 y2

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Asynchronous Sequential Logic Derive the transition table :

x1x2 00 y1 y2 00 00 01 01 11 00 10 00 Y1Y2 01 11 00 01 11 10 01 11 11 11 10 00 11 10 10

Critical race condition : y1 y2 x1 x2 = 1101 1100 1. Y1 changes to 0 before Y2 y1 y2 x1 x2 = 0100 2. Y2 changes to 0 before Y1 y1 y2 x1 x2 = 00100
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Asynchronous Sequential Logic

Procedure for Analysis

1. Label each latch output with Yi and its feedback path with yi , for i = 1, 2, , k . 2. Derive the Boolean functions for Si and Ri . 3. Check whether SR = 0 for each NOR latch or whether SR = 0 for each NAND latch.
( Condition not satisfied may not operate properly)

4. Evaluate Y = S + R y for each NOR latch or Y = S + R y for each NAND latch. 5. Plot the transition table.
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Implementation Example
y 0 1 00 0 0 0 0 x1 x2 01 11 00 00 00 11 10 11 11 y Y 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1

Asynchronous Sequential Logic

S R 0 0 1 1 0 0 x x x x 0 0 1 1 0 0

Transition table

Y = x1 x2 + x1 y
y 0 1 00 0 0 x1 x2 01 11 0 0 0 x 10 1 x

Latch excitation table x1 x2 01 11 x 1 x 0

y 0 1

00 x 1

10 0 0

Map for S

Map for R

S = x1 x2

R = x1
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Asynchronous Sequential Logic Logic Diagram

x1 R Y

x2

x2

S Y

x1

R
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Asynchronous Sequential Logic

Design Procedure
Design Example :
Design a gated latch circuit with
Two inputs : G(gate), D(data) One output : Q G=1Q=D G = 1 Q = Q0

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Asynchronous Sequential Logic Total state : the internal state combined with input. Total state table : inputs output state D G Q a b c d e f 0 1 0 1 1 0 1 1 0 0 0 0 0 1 0 0 1 1

Comments D=Q because G=1 D=Q because G=1 After state a or d After state c After state b or f After state e
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Asynchronous Sequential Logic Primitive flow table :

A flow table with only one stable total state in each row. 1. Fill in the stable state. DG 2. Both inputs are not allowed 00 01 11 to change simultaneously. a c,- a,0 b,Enter dash marks in each row that differs in 2 or more b -,- a,- b,1 variables. c c,0 a,- -,3. Fill in the unstable state. d c,- -,- b,Example : e f,- -,- b,state c , after state a and d column 00, row a and d filled f f,1 a,- -,with unstable state ( c, - )

10 -,e,d,d,0 e,1 e,-

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Asynchronous Sequential Logic Reduction of the Primitive flow table :

The table can be reduced to a smaller number of rows if two or more stable states are placed in the same row of the flow table. The grouping of stable states from separate rows into one common row is called merging. Two or more rows in the primitive flow table can be merged into one row if there are non-conflicting states and outputs in each of the columns.

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Asynchronous Sequential Logic

DG 01 11 DG 01 11

00 a b c d e f

10 -,Grouping a c d

00

10 -,d,-

c,- a,0 b,-,-

c,- a,0 b,c,0 a,c,-,-,-

a,- b,1 e,-,d,-

c,0 a,c,f,f,1 -,-,a,-

b,- d,0

b,- d,0 b,- e,1 -,e,b e f 00 DG 01 11 10

-,- a,f,f,1 -,-

b,1 e,b,- e,1 e,36

a,- -,-

Asynchronous Sequential Logic

00 a c d DG 01 11 10 -,d,b e f 00 -,f,f,1 DG 01 11 a,-,10

c,- a,0 b,c,0 a,c,-,-,-

b,1 e,b,- e,1 e,-

b,- d,0

a,- -,-

00 a, c, d b, e, f DG 01 11 10 d,0 c,0 a,0 b,f,1 a,b,1 e,1

merging DG 01 11

00 a b

10 a,0

a,0 a,0 b,b,1 a,-

b,1 b,1

Reduced table ( two alternatives)

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Asynchronous Sequential Logic Transition Table and Logic Diagram

Assign to each state a distinct binary value. ( a = 0 , b =1 ) This assignment converts the flow table into a transition table.

y 0 1

00 0 1

DG 01 11 0 0 1 1

10 0 1

y 0 1

00 0 1

DG 01 11 0 1 0 1

10 0 1

Map for Y

Map for Q

Y = DG + Gy

Q=y
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Asynchronous Sequential Logic

Logic Diagram D Y Q G y Using SR Latch 00 0 1 DG 01 11 0 0 1 1 10 0 1 00 0 x DG 01 11 0 0 1 x S = DG 10 0 x 00 x 0 DG 01 11 x 1 0 0 10 x 0

y 0 1

y 0 1

0 1

Map for Y

R = DG
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Asynchronous Sequential Logic

Logic Diagram

S Q

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Asynchronous Sequential Logic

Assignment Outputs to Unstable States :

1. Assign a 0 to an output variable associated with an unstable state that is a transient state between two stable states that have a 0 in the corresponding output variable. 2. Assign a 1 to an output variable associated with an unstable state that is a transient state between two stable states that have a 1 in the corresponding output variable. 3. Assign a dont-care condition to an output variable associated with an unstable state that is a transient state between two stable states that have different values (0 and 1 or 1 and 0) in the corresponding output variable.

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Asynchronous Sequential Logic

Example:

a b c d

0 a , 0 b , -c , -- b , 00 c , 1 d , -1 a , -- d , 11 Flow table

0 x 1 x

0 0 1 1 If assign 1

State change (a, 0) (b, 1) (b, 0)

Output assignment

Output 010
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Asynchronous Sequential Logic

Summary of Design Procedures :

1. Obtain a primitive flow table from the given design specifications. 2. Reduce the flow table by merging rows in the primitive table. 3. Assign binary state variables to each row of the reduced flow table to obtain the transition table. 4. Assign output values to dashes associated with the unstable state to obtain the output map. 5. Simplify the Boolean function of the excitation and output variables and draw the logic diagram.

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Asynchronous Sequential Logic

Reduction of State and Flow Tables

Present State a b c d Next State x=0 x=1 c b d a a d b d Output State x=0 x=1 0 1 0 1 1 0 1 0

Present states a and b have the same output for the same input. x=0 : a c , b d if c and d equivalent a and b equivalent we say that ( a , b ) imply ( c , d )
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Asynchronous Sequential Logic

Implication Table :
Example : State table to be reduced Present State a b c d e f g Next State x=0 x=1 d b e a g f a d a d c b a e Output State x=0 x=1 0 0 0 0 0 1 1 0 1 0 0 0 1 0
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Asynchronous Sequential Logic

Implication table Present State a b c d e f g Next State Output State x=0 x=1 x=0 x=1 d b 0 0 e a 0 0 g f 0 1 a d 1 0 a d 1 0 c b 0 0 a e 1 0

b c d e f g

d, e

c, e a, b

c, d

Equivalent States (a, b) (d, e) (d, g) (e, g)

d, e d, e

(a, b) (d, e, g)
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Asynchronous Sequential Logic (a,b) (c) (d,e,g) (f) reduce to 4 states (a) (c) (d) (f) Reduced State Table

Present State a c d f

Next State x=0 x=1 d a d f a d c a

Output State x=0 x=1 0 0 0 1 1 0 0 0

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Asynchronous Sequential Logic

Merging of the Flow Table :

Asynchronous sequential circuit may sometimes be represented by incompletely specified state table. Such as :
00 a b c d e f DG 01 11 10 -,-

c,- a,0 b,-,-

a,- b,1 e,-,d,-

c,0 a,c,f,f,1 -,-,a,-

b,- d,0 b,- e,1 -,e,48

Asynchronous Sequential Logic

Two incompletely specified states can be combined are said to be compatible. The process that of finding a suitable group of compatibles :
1. Determine all compatible pairs by using the implication table. 2. Find Maximal compatibles using a merger diagram. 3. Find a minimal collection of compatibles that covers all the states and is closed.

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Asynchronous Sequential Logic

Determine all compatible pairs DG 01 11

00 a b c d e f

10 -,-

b c d e

c, f d, e d, e

c,- a,0 b,-,-

d, e c, f

a,- b,1 e,-,d,-

c,0 a,c,f,f,1 -,-,a,-

b,- d,0 b,- e,1 -,e,-

d, e c, f

f c, f a

compatible pairs (a, b) (a, c) (a, d) (b, e) (b, f) (c, d) (e, f)

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Asynchronous Sequential Logic

Maximal compatibles
A group of compatibles that contains all the possible combinations of compatible states. The maximal compatibles can be obtained from a merger diagram.
compatible pairs : (a, b) (a, c) (a, d) (b, e) (b, f) (c, d) (e, f) a b

Merger diagram :
f

e d

Maximal compatibles (a, b) (a, c, d) (b, e, f)

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Asynchronous Sequential Logic

An n-state compatible is represented in the merger diagram by an n-sided polygon with all its diagonals connected. Example : a h g f e d b c

Maximal compatibles (a, b, e, f) (b, c, h) (c, d) (g)

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Asynchronous Sequential Logic

Closed Covering Condition The condition that must be satisfied for row merging is that the set of chosen compatibles must cover all the states and must be closed. Closure condition : There are no implied states or if the implied states are included within the set. A closed set of compatibles that covers all the states is called a closed covering.
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Asynchronous Sequential Logic

Example: a f b

Maximal compatibles (a, b) (a, c, d) (b, e, f)

e d

Remove (a, b) c a set of two compatibles (a, c, d) (b, e, f)

(a, c, d) (b, e, f) cover all the states. covering condition satisfied. There are no implied states for (a, c) (a, d) (c, d) (b, e) (b, f) (e, f) closure condition satisfied.
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Asynchronous Sequential Logic

Example: a

b b, c c

d, e

e a, d

d b, c e

c d

Maximal Compatibles (a, b) (a, d) (b, c) (c, d, e)

Compatible pairs (a, b) (a, d) (b, c) (c, d) (c, e) (d, e)

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Asynchronous Sequential Logic

Choose the two compatibles : (a, b) (c, d, e) the set will cover all five states. The closure condition can be checked by means of a closure table :

Compatibles Implied states

(a, b)

(a, d) (b, c) (c, d, e) (a, d) (b, c)

(b, c) (b, c) (d, e)

The implied states for (a, b) are (b, c). But (b, c) is not included in the chosen set (a, b) (c, d, e) Not closed.

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Asynchronous Sequential Logic Choose the three compatibles : (a, b) (b, c) (c, d, e) the implied states (b, c) (d, e) and (a, d) are included in the set. Satisfy the closed covering condition. The original flow table can be reduced from 5 rows to 3 rows by merging a and d, b and c as well as c, d and e. Note : An alternative satisfactory choice of closed-covered compatibles would be (a, b) (b, c) (d, e).
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Asynchronous Sequential Logic

Race-free State Assignment

The primary objective in choosing a proper binary state assignment is the prevention of critical races. Critical races can be avoided by making a binary state assignment in such a way that only one variable changes at any given time when a state transition occurs in the flow table.

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Asynchronous Sequential Logic

Example : Three-row Flow-table

x 1x 2 00 a b c a a a 01 b b c 11 c b c 10 a c c a = 00 b = 01

c = 11

Flow table

Transition diagram

Assign binary value : a = 00, b = 01, c = 11 This assignment will cause a critical race during the transition form a to c. ( Because 2 changes in the binary state variables)
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Asynchronous Sequential Logic A race-free assignment : Add an extra row to the flow table.
x1x2 01 11 b b c c d b c -

00 a b c d a a d a

10 a c c a = 00 b = 01

d = 10 c = 11

Flow table

Transition diagram

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Asynchronous Sequential Logic

Example : Four-row Flow-table

00 a b c d b b c c 01 a d a d 11 d b b d 10 a a c c a b

d c

Flow table

Transition diagram

Avoid 2 changes in the binary state variables. Need three binary state variables.

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Asynchronous Sequential Logic A state assignment map suitable for any fourrow flow table. Original states : a , b , c , and d Extra states : e , f , and g
00 0 1 a e 01 b d 11 c f 10 g

a=000

b=001

e=100 g=010

Binary assignment
ad aed dc dfc ca cga

d=101

f=111

c=011

Transition diagram
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Asynchronous Sequential Logic State assignment to modified flow table

00 a b c d b b c c 01 a d a d 11 d b b d 10 a a c c 000 a 00 b b c c f 01 a d g a d b b d d 63

11 e

10 a a c c f

001 b 011 c 010 g 110 111 f 101 d 100 e

Flow table
ad aed dc dfc ca cga

Asynchronous Sequential Logic The method for making race-free state assignment by adding extra rows in the flow table, sometimes referred to as the shared-row method. Another method : multiple-row method each state in the original flow table is replaced by two or more combinations of state variables.

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Asynchronous Sequential Logic

Example : Multiple-Row Method

00 a b c d b b c c 01 a d a d 11 d b b d 10 a a c c

Flow table Avoid 2 changes in the binary state variables. Need three binary state variables.

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Asynchronous Sequential Logic Binary assignment

00 0 1 a1 c2

01 b1 d2

11 c1 a2

10 d1 b2

Each state is adjacent to three states of different letter designation. The change from one stable state to another will always cause a change of one binary state variable.
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Asynchronous Sequential Logic The expand table is formed by replacing each row of the original table with two rows.
00 0 1 a1 c2 00 a b c d b b c c 01 b1 d2 01 a d a d 11 d b b d 11 c1 a2 10 a a c c 010 d1 101 d2 10 d1 b2 000 a1 111 a2 001 b1 00 b1 b2 b1 b2 c1 c2 c1 c2 01 a1 a2 d2 d1 a2 a1 d1 d2 11 d1 d2 b1 b2 b1 b2 d1 d2 10 a1 a2 a1 a2 c1 c2 c1 c2
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110 b2 011 c1 100 c2

Flow table

Hazards

Asynchronous Sequential Logic

Hazard : Unwanted switching transients that may appear at the output of a circuit because different path exhibit different propagation delays. Hazards occurs :
1. In combinational circuit : Cause a temporary false output value. 2. In asynchronous circuit : May result in a trasition to a wrong stable state.
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Asynchronous Sequential Logic

Hazard in Combinational Circuits

Example:
x1 1111 11 1 10 0 0 0 0 01 1 1 1 1110 11 Y 0 00 1 1 1

x2 x3

1000 00 1111 11

Y = x1 x2 + x2 x3 x2 : 1 0 The output may momentarily go to 0.

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Asynchronous Sequential Logic Static 1-hazard : The output may momentarily go to 1 when it should remain 0. Static 0-hazard : The output may momentarily go to 0 when it should remain 1. Dynamic hazard : The output change three or more times when is should change from 1 to 0 or from 0 to 1.

1 0 Static 1-hazard

1 0 Static 0-hazard

1 0 Dynamic hazard
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00 0 1

01 1 1

11

10

Asynchronous Sequential Logic

Y = x1 x2 + x2 x3 x2 : 1 0 move the circuit from minterm 111 to minterm 101. Hazard exits because the change of input results in a different product term covering the two minterms. The remedy for eliminating a hazard : Covering any two minterms that may produce a hazard with a product term common to both.
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Asynchronous Sequential Logic

x1 0 1 00 x2 x3 01 11 1 1 1 1 10

Y = x1 x2 + x2 x3 + x1 x3
x1

x2 x3

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Asynchronous Sequential Logic

Hazard in Sequential Circuits

In synchronous sequential circuit, hazards are not of concern, since momentary erroneous signals are not generally troublesome. If a momentary incorrect signal is fed back in an asynchronous sequential circuit, it may cause the circuit to go to the wrong stable state.

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 Example:
x1

Asynchronous Sequential Logic

Y = x1 x2 +x2 y x2 y y 0 1 00 0 1 x1 x2 01 11 0 0 1 1 10 0 1

If in total state : y x1 x2 = 111 and x2 : 10 the next total state should be 110. However, because of the hazard, output Y may go to 0 momentarily the next total state will switch to the incorrect total state 010. This malfunction can be eliminated by adding an extra gate.

Transition table y 0 1 00 0 1 x1 x2 01 11 0 0 1 1 10 0 1

Map for Y
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 Essential Hazards

Cause by unequal delays along two or more paths that originate from the same input. To avoid essential hazards : Adjust the amount of delay in the affected path. Example: suppose the delay of inverter is longer than the other delays. 01 0 y 1 R1 01 y1 S1 01 0 y2 R2 0 10 y2 0 1 01 y 2 10 0 1 0 1 y1 0 1 y1 x 01 y2 S2 0 1 0 01 y1 y2 01 x 0 1

Asynchronous Sequential Logic

00 00 01 00 11 11 10 11

10 01 01 10
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Asynchronous Sequential Logic Implementation with SR Latches

To avoid static hazards in asynchronous sequential circuit is to implement the circuit with SR latches. Typical structure of latch implementation :

R Q

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Asynchronous Sequential Logic

Design Example
Design procedures :
1. State the design specifications. 2. Derive a primitive flow table. 3. Reduce the flow table by merging the row. 4. Make a race-free binary state assignment. 5. Obtain the transition table and output map. 6. Obtain the logic diagram using SR latches.

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Example :
1. State the design specifications.

Asynchronous Sequential Logic

Design a negative-edge-triggered T flip-flop.

2. Derive a primitive flow table.

Total State table Inputs Output T C Q 1 1 1 1 0 0 0 0 1 0 1 0 0 1 0 1 0 1 1 0 0 0 1 1

State a b c d e f g h

Comments Initial output is 0 After state a Initial output is 1 After state c After state d or f After state a or e After state b or h After state c or g
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Violate fundamental mode

Asynchronous Sequential Logic

primitive flow table. TC 01 11

00 a b c d e f g h

10

-,- f,0 g,- -,-,e,h,-,-

a,0 b,c,b,1

c,1 d,a,- d,0 -,d,-

e,0 f,e,f,0

a,- -,b,-

g,1 h,- -,g,-

h,1 c,- -,-

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Asynchronous Sequential Logic 3. Reduce the flow table by merging the row. b c d e f g h
a, c

Implication table
b, d

b, d b, d

e, g b, d

a, c

f, h f, h a, c

f, h e, g f, h a, c a, c

e, g e, g f, h b, d e, g e, g a, c f, h

b, d

g
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Asynchronous Sequential Logic The compatible pairs : (a , f) (b , g) (b , h) (c , h) (d , e) (d , f) (e , f) (g , h) Merger Diagram

a h g f e d b c

The maximum compatible set : (a , f) (b , g , h) (c , h) (d , e , f)

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Asynchronous Sequential Logic The minimal collection of compatibles is also the maximal compatible pairs. (a , f) (b , g) (b , h) (c , h) (d , e) (d , f) (e , f) (g , h) The Reduced flow table
TC 01 11 TC 01 11

00 a,f b,g,h c,h d,e,f

10 a b c d

00

10

e,- f,0

a,0 b,b,1

d,- a,0 a,0 b,b,1 b,1 c,b,1

g,1 h,1 c,-

g,1 h,1 c,1 d,e,0 f,0 a,- d,0

b,1 c,1 c,1 d,d,0 d,0 a,- d,0

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Asynchronous Sequential Logic 4. Make a race-free binary state assignment Transition diagram : a = 00 b = 01

d = 10

c = 11

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Asynchronous Sequential Logic 5. Obtain the transition table and output map
TC 01 11 00 01 11 10 00 11 11 00 TC 01 11 0 1 1 0 0 1 1 0

y1 y2 00 00 01 11 10 01 01

10 01 01 10 10

y1 y2 00 00 01 11 10 0 1 1 0

10 x 1 x 0

10 10

Transition table

Output Q = y2

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Asynchronous Sequential Logic 6. Obtain the logic diagram using SR latches

Q is equal to the state variable y2 Require two SR latches. Map for latch inputs TC 01 11 0 0 x x 0 1 x 0 TC 01 11 x x 0 0 x 0 0 1

y1 y2 00 00 01 11 10 1 0 0 x

10 0 0 x x

y1 y2 00 00 01 11 10 0 x 1 0

10 x x 0 0

S1 = y2 T C + y2 T C

R1 = y2 T C + y2 T C
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Asynchronous Sequential Logic

y1 y2 00 00 01 11 10 0 x x 0

TC 01 11 0 x x 0 0 x x 0

10 1 x 0 0

y1 y2 00 00 01 11 10 x 0 0 x

TC 01 11 x 0 0 x x 0 0 x

10 0 0 1 x

S2 = y1 T C

R2 = y1 T C

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 The logic diagram T C

Asynchronous Sequential Logic

Y1 Y1

Y2 Y2

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