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MPCPRG/D 10/95
Motorola Inc. 1995 Portions hereof International Business Machines Corp. 19911995. All rights reserved. This document contains information on a new product under development by Motorola and IBM. Motorola and IBM reserve the right to change or discontinue this product without notice. Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or implied copyright or patent licenses granted hereunder by Motorola or IBM to design, modify the design of, or fabricate circuits based on the information in this document. The PowerPC 60x microprocessors embody the intellectual property of Motorola and of IBM. However, neither Motorola nor IBM assumes any responsibility or liability as to any aspects of the performance, operation, or other attributes of the microprocessor as marketed by the other party or by any third party. Neither Motorola nor IBM is to be considered an agent or representative of the other, and neither has assumed, created, or granted hereby any right or authority to the other, or to any third party, to assume or create any express or implied obligations on its behalf. Information such as data sheets, as well as sales terms and conditions such as prices, schedules, and support, for the product may vary as between parties selling the product. Accordingly, customers wishing to learn more information about the products as marketed by a given party should contact that party. Both Motorola and IBM reserve the right to modify this manual and/or any of the products as described herein without further notice. NOTHING IN THIS MANUAL, NOR IN ANY OF THE ERRATA SHEETS, DATA SHEETS, AND OTHER SUPPORTING DOCUMENTATION, SHALL BE INTERPRETED AS THE CONVEYANCE BY MOTOROLA OR IBM OF AN EXPRESS WARRANTY OF ANY KIND OR IMPLIED WARRANTY, REPRESENTATION, OR GUARANTEE REGARDING THE MERCHANTABILITY OR FITNESS OF THE PRODUCTS FOR ANY PARTICULAR PURPOSE. Neither Motorola nor IBM assumes any liability or obligation for damages of any kind arising out of the application or use of these materials. Any warranty or other obligations as to the products described herein shall be undertaken solely by the marketing party to the customer, under a separate sale agreement between the marketing party and the customer. In the absence of such an agreement, no liability is assumed by Motorola, IBM, or the marketing party for any damages, actual or otherwise. Typical parameters can and do vary in different applications. All operating parameters, including Typicals, must be validated for each customer application by customers technical experts. Neither Motorola nor IBM convey any license under their respective intellectual property rights nor the rights of others. Neither Motorola nor IBM makes any claim, warranty, or representation, express or implied, that the products described in this manual are designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the product could create a situation where personal injury or death may occur. Should customer purchase or use the products for any such unintended or unauthorized application, customer shall indemnify and hold Motorola and IBM and their respective ofcers, employees, subsidiaries, afliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola or IBM was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Afrmative Action Employer.
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Introduction
The primary objective of this document is to provide a concise method by which system software and hardware developers and application programmers may more readily provide software that is compatible across the family of PowerPC processors and other devices. A more detailed account of the following topics or the PowerPC architecture in general, may be obtained from the PowerPC Microprocessor Family: The Programming Environments, referred to as The Programming Environments Manual. (The PowerPC Architecture: A Specication for a New Family of RISC Processors denes the architecture from the perspective of the three programming environments and remains the dening document for the PowerPC architecture.) This document is divided into four parts: Part 1, Register Summary, on page 4 provides a brief overview of the PowerPC register set, including a programming model and quick reference guides for both 32and 64-bit registers. Part 2, Memory Control Model, on page 28 provides a brief outline of the page table entry and segment table entry for both 32- and 64-bit implementations. Part 3, Exception Vectors, on page 40 provides a quick reference for exception types and the conditions that cause them. Part 4, PowerPC Instruction Set, on page 41 provides detailed information on the instruction eld summaryincluding syntax and notation conventions. Also included, is the entire PowerPC instruction set, sorted by mnemonic and opcode.
In this document, the term 60x is used to denote a 32-bit microprocessor from the PowerPC architecture family. 60x processors implement the PowerPC architecture as it is specied for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits, and oating-point data types of 32 and 64 bits (singleprecision and double-precision). Table 1 contains acronyms and abbreviations that are used in this document. Note that the meanings for some acronyms (such as SDR1 and XER) are historical, and the words for which an acronym stands may not be intuitively obvious.
GPR31
IBAT1U IBAT1L
Floating-Point Registers
FPR0 FPR1
SDR1 Register
FPR31 SDR1 SPR 25
2
Segment Registers 1
SR0 SR1
Condition Register
CR
SR15
XER Register
XER
SPRG Registers
SPRG0 SPRG1 SPR 272 SPR 273 SPR 274 SPR 275
Link Register
LR SPR 8
SPRG2 SPRG3
Count Register
CTR SPR 9
Miscellaneous Registers
Time Base Facility (Write-Only)
TBL SPR 284 SPR 285 TBU
1 2
3 These
These registers are in 32-bit implementations only. These registers are in 64-bit implementations only. registers are optional in the PowerPC architecture.
Table 3 provides a quick method by which to reference the SPR and TBR numbers and bit elds for all 32-bit PowerPC registers. Note that reserved bits are shaded.
Table 3. Quick Reference Guide32-Bit Registers
Number
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 18 16 19 20 21 22 23 24 25 26 27 28 29 30 31 Name
GPRn CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 (For the FPSCR bits, refer to 1.4, Floating-Point Status and Control Register (FPSCR), on page 9.) 0 0 0 0 0 0 0 0 0 0 0 0 0 POW 0 ILE EE PR FP ME FE0 SE BE FE1 0 IP IR DR 0 0 RI LE 0 0 0 0 VSID T Ks Kp N T Ks Kp BUID Controller-Specic Information Byte Count SPR 1 SO OV CA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPR 8 Branch Address SPR 9 CTR SPR 18 DSISR DAR SPR 19 DEC SPR 22 0 0 0 0 0 0 0 HTABORG HTABMASK SPR 25 SPR 26 SRR0 0 0 SRR1 SPR 27 SPRGn SPR 272 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPR 282 E RID TB(L) SPR 284 SPR 285 TBU SPR 287 Version Revision 0 0 0 0 SPR 528 Vs Vp BL BEPI SPR 529 0 0 0 0 0 0 0 0 0 0 BRPN WIMG 0 PP SPR 1013 DAB BT DW DR TBR 268 TB(L) TBR 269 TBU Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Notes: 1. For all SPR numbers refer to Figure 1 2. Write-Only 3. Read-Only
GPRn CR FPSCR MSR SRn[T = 0 ] SRn[T = 1 ] XER LR CTR DSISR DAR DEC SDR1 SRR0 SRR1 SPRGn 1 EAR TB(L) 2 TBU 2 PVR xBATnU 1 xBATnL 1 DABR TB(L) 2 TBU 2 Name30 31 29
Table 4 provides a quick method by which to reference the SPR and TBR numbers and bit elds for all 64-bit PowerPC registers. Note that reserved bits are shaded.
Table 4. Quick Reference Guide64-Bit Registers
Number
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51Name54 55 56 57 52 53
SPR 8 SPR 9 SPR 19 SPR 25 SPR 26 SPR 27 SPR 272 SPR 280 SPR 528 SPR 529 SPR 1013 TBR 268 TBR 269
FPRn For the MSR bits, refer to 1.8, Machine State Register (MSR), on page 16.) Branch Address CTR DAR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HTABSIZE HTABORG 0 0 SRR0 SRR1 SPRGn Physical Address of Segment Table 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BL VsVp BEPI 0 0 0 0 0 0 0 0 WIMG 0 PP 0 0 BRPN B D D DAB TW R TB(L) TBU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPRn FPRn MSR LR CTR DAR SDR1 SRR0 SRR1 SPRGn 1 0 0 ASR 0 xBATnU 1 xBATnL 1 DABR
All oating-point arithmetic instructions operate on data located in FPRs and, with the exception of compare instructions, place the result into an FPR. Information about the status of oating-point operations is placed into the FPSCR and in some cases, into the CR after the completion of instruction execution. The oating-point arithmetic instructions produce intermediate results that may be regarded as innitely precise. After normalization or denormalization, if the precision of the intermediate result cannot be represented in the destination format (single or double precision), it is rounded to the specied precision before being placed in the target FPR. The nal result is then placed into the FPR in the double-precision format.
FPR0 FPR1 ... ... FPR31 0 63
OV
324 2531
Byte Count
Reserved
19 20 21 22 23 24 25 26 27 28 29 30 31
The FPSCR contains bits to do the following: Record exceptions generated by floating-point operations Record the type of the result produced by a floating-point operation Control the rounding mode used by floating-point operations Enable or disable the reporting of exceptions (invoking the exception handler)
Bits 023 are status bits. Bits 2431 are control bits. Status bits in the FPSCR are updated at the completion of the instruction execution. Except for the oating-point enabled exception summary (FEX) and oating-point invalid operation exception summary (VX), the exception condition bits in the FPSCR (bits 012 and 2123) are sticky. Once set, sticky bits remain set until they are cleared by an mcrfs, mtfs, mtfsf, or mtfsb0 instruction. FEX and VX are the logical ORs of other FPSCR bits. Therefore, these two bits are not listed among the FPSCR bits directly affected by the various instructions.
FEX
VX
3 4 5 6
OX UX ZX XX
7 8 9 10 11 12 13 14
10
20 21 22 23 24 25 26 27 28 29
3031
RN
Table 7 illustrates the oating-point result ags used by PowerPC processors. The result ags correspond to FPSCR bits 1519.
11
The CR elds can be set in one of the following ways: Specified fields of the CR can be set by a move instruction (mtcrf) to the CR from a GPR. A specified field of the CR can be moved to another CR field with the mcrf instruction. A specified field of the XER can be copied to the CR by the mcrxr instruction. A specified field of the FPSCR can be copied to the CR by the mcrfs instruction. Condition register logical instructions can be used to perform logical operations on specified bits in the condition register. CR0 can be the implicit result of an integer instruction. CR1 can be the implicit result of a floating-point instruction. A specied CR eld can indicate the result of either an integer or oating-point compare instruction.
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The following tables, Table 8Table 10, provide bit setting information for CR0, CR1, and the CRn fields, respectively.
Table 8. Bit Settings for CR0 Field of CR
CR0 Bit 0 1 2 3 Description Negative (LT)This bit is set when the result is negative. Positive (GT)This bit is set when the result is positive (and not zero). Zero (EQ)This bit is set when the result is zero. Summary overow (SO)This is a copy of the nal state of XER[SO] at the completion of the instruction.
Note: For more information on the FPSCR refer to Section 1.4, Floating-Point Status and Control Register (FPSCR).
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Notes: 1. Here, the bit indicates the bit number in any one of the four-bit subelds, CR0CR7. 2. For a complete description of instruction syntax conventions, refer to Table 31.
Note that although the two least-signicant bits can accept any values written to them, they are ignored when the LR is used as an address. The link register can be accessed by the mtspr and mfspr instructions using SPR8. Fetching instructions along the target path (loaded by an mtspr instruction) is possible provided the link register is loaded sufciently ahead of the branch instruction. It is possible for a PowerPC microprocessor to fetch along a target path loaded by a branch and link instruction. Both conditional and unconditional branch instructions include the option of placing the effective address of the instruction following the branch instruction in the LR.
14 PowerPC Microprocessor Family: The Programmers Reference Guide
Fetching instructions along the target path is also possible provided the count register is loaded sufciently ahead of the branch instruction. The count register can be accessed by the mtspr and mfspr instructions by specifying SPR9. In branch conditional instructions, the BO eld species the conditions under which the branch is taken. The rst four bits of the BO eld specify how the branch is affected by or affects the CR and the CTR. The encoding for the BO eld is shown in Table 11.
Table 11. BO Operand Encodings
BO 0000y 0001y 001zy 0100y 0101y 011zy 1z00y 1z01y 1z1zz Description Decrement the CTR, then branch if the decremented CTR 0 and the condition is FALSE. Decrement the CTR, then branch if the decremented CTR = 0 and the condition is FALSE. Branch if the condition is FALSE. Decrement the CTR, then branch if the decremented CTR 0 and the condition is TRUE. Decrement the CTR, then branch if the decremented CTR = 0 and the condition is TRUE. Branch if the condition is TRUE. Decrement the CTR, then branch if the decremented CTR 0. Decrement the CTR, then branch if the decremented CTR = 0. Branch always.
The z indicates a bit that is ignored. The z bits should be cleared to zero, as they may be assigned a meaning in some future version of the PowerPC architecture. The y bit provides a hint about whether a conditional branch is likely to be taken and is used by some PowerPC implementations to improve performance. Other implementations may ignore the y bit.
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Table 12 shows the bit denitions for the MSR. Full function reserved bits are saved in SRR1 when an exception occurs; partial function reserved bits are not saved.
Table 12. MSR Bit Settings
Bit(s) Name 64 Bit 0 32 Bit SF Sixty-four bit mode 0 The 64-bit processor runs in 32-bit mode. 1 The 64-bit processor runs in 64-bit mode. Note that this is the default setting. Reserved. Full function. Reserved. Partial function. Reserved. Full function. Reserved. Partial function. Power management enable 0 Power management disabled (normal operation mode). 1 Power management enabled (reduced power mode). Note: Power management functions are implementation-dependent. If the function is not implemented, this bit is treated as reserved. ReservedImplementation-specic Exception little-endian mode. When an exception occurs, this bit is copied into MSR[LE] to select the endian mode for the context established by the exception. External interrupt enable 0 While the bit is cleared the processor delays recognition of external interrupts and decrementer exception conditions. 1 The processor is enabled to take an external interrupt or the decrementer exception. Description
0 14 59 1012 13
POW
46 47 48
14 15 16
ILE EE
16
50
18
FP
51
19
ME
52 53
20 21
FE0 SE
54
22
BE
55 56 57
23 24 25
FE1 IP
58
26
IR
59
27
DR
6061 62
2829 30
RI
63
31
LE
17
The oating-point exception mode bits (FE0FE1) are interpreted as shown in Table 13. Note that these bits can be logically ORed, so that if either is set the processor operates in precise mode.
Table 13. Floating-Point Exception Mode Bits
FE0 0 0 1 1 FE1 0 1 0 1 Mode Floating-point exceptions disabled Floating-point imprecise nonrecoverable Floating-point imprecise recoverable Floating-point precise mode
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The PVR consists of two 16-bit elds: Version (bits 015)A 16-bit number that uniquely determines a particular processor version and version of the PowerPC architecture. This number can be used to determine the version of a processor; it may not distinguish between different product models if more than one model uses the same processor. Revision (bits 1631)A 16-bit number that distinguishes between various releases of a particular version (that is, an engineering change level). The value of the revision portion of the PVR is implementation-specic. The processor revision level is changed for each revision of the device.
19
60 61 62 63
Figure 14 and Figure 15 show the format of the upper and lower BAT registers for 32-bit PowerPC processors.
Reserved BEPI 0 14 15 0000 18 19 BL Vs Vp 29 30 31
28 29 30 31
20
BL Vs Vp BRPN WIMG
61 6263
29 3031
PP
Table 16 lists the BAT area lengths encoded in the BL eld of the upper BAT registers.
Table 16. BAT Area Lengths
BAT Area Length 128 Kbytes 256 Kbytes 512 Kbytes 1 Mbyte 2 Mbytes 4 Mbytes 8 Mbytes 16 Mbytes 32 Mbytes BL Encoding 000 0000 0000 000 0000 0001 000 0000 0011 000 0000 0111 000 0000 1111 000 0001 1111 000 0011 1111 000 0111 1111 000 1111 1111
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1.11 SDR1
The SDR1 is a 64-bit register in 64-bit implementations and a 32-bit register in 32-bit implementations. Refer to Section 2.3.3, SDR1 Register Denitions, for a complete description of SDR1.
The effective address generated by a memory access instruction is placed in the DAR if the access causes an exception (for example, an alignment exception). If the exception occurs in a 64-bit implementation operating in 32-bit mode, the high-order 32 bits of the DAR are cleared.
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1.15 SPRG0SPRG3
SPRG0SPRG3 are 64-bit or 32-bit registers, depending on the type of PowerPC microprocessor. They are provided for general operating system use, such as performing a fast state save or for supporting multiprocessor implementations. The formats of SPRG0 through SPRG3 are shown in Figure 17.
SPRG0 SPRG1 SPRG2 SPRG3
0 0 63 63
SPRG1
SPRG2 SPRG3
1.16 DSISR
The 32-bit DSISR, shown in Figure 18, identies the cause of DSI and alignment exceptions.
DSISR 0 31
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status when an r instruction is executed. It also holds the EA for the instruction that follows the System Call (sc) instruction. The format of SRR0 is shown in Figure 19. For 32-bit implementations, the format of SRR0 follows the low-order bits (3263) of Figure 19.
Reserved SRR0 0 00 61 62 63
When an exception occurs, SRR0 is set to point to an instruction such that all prior instructions have completed execution and no subsequent instruction has begun execution. When r is executed, the contents of SRR0 are copied to the next instruction address (NIA)the 64- or 32-bit address of the next instruction to be executed. The instruction addressed by SRR0 may not have completed execution, depending on the exception type. SRR0 addresses either the instruction causing the exception or the instruction that immediately follows. The instruction addressed can be determined from the exception type and status bits. If the exception occurs in 32-bit mode of the 64-bit implementation, the high-order 32 bits of SRR0 are cleared and the high-order 32 bits of the NIA are cleared when returning to 32-bit mode. Note that in some implementations, every instruction fetch, when MSR[IR] = 1, and every instruction execution requiring address translation when MSR[DR] = 1, may modify SRR0.
On 64-bit implementations, when an exception occurs, bits 3336 and 4247 of SRR1 are loaded with exception-specic information and bits 032, 3741, and 4863 of MSR are placed into the corresponding bit positions of SRR1.
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For 32-bit implementations, when an exception occurs, bits 14 and 1015 of SRR1 are loaded with exception-specic information and bits 0, 59, and 1631 of MSR are placed into the corresponding bit positions of SRR1. Note that, in some implementations, every instruction fetch when MSR[IR] = 1, and every instruction execution requiring address translation when MSR[DR] = 1, may modify SRR1.
The TB increments until its value becomes 0xFFFF_FFFF_FFFF_FFFF (264 1). At the next increment its value becomes 0x0000_0000_0000_0000. Note that there is no explicit indication that this has occurred (that is, no exception is generated). The period of the time base depends on the driving frequency. The TB is implemented such that the following requirements are satised: 1. Loading a GPR from the time base has no effect on the accuracy of the time base. 2. Storing a GPR to the time base replaces the value in the time base with the value in the GPR. The PowerPC VEA does not specify a relationship between the frequency at which the time base is updated and other frequencies, such as the processor clock. The TB update frequency is not required to be constant; however, for the system software to maintain time of day and operate interval timers, one of two things is required: The system provides an implementation-dependent exception to software whenever the update frequency of the time base changes and a means to determine the current update frequency; or The system software controls the update frequency of the time base.
Note that if the operating system initializes the TB to some reasonable value and the update frequency of the TB is constant, the TB can be used as a source of values that increase at a constant rate, such as for time stamps in trace entries.
25
Even if the update frequency is not constant, values read from the TB are monotonically increasing (except when the TB wraps from 264 1 to 0). If a trace entry is recorded each time the update frequency changes, the sequence of TB values can be post-processed to become actual time values. For information on reading, writing, and computing time of day on the time base, refer to Chapter 2, PowerPC Register Set, The Programming Environments Manual.
For information on writing and reading the DEC, refer to Chapter 2, PowerPC Register Set, The Programming Environments Manual.
DAB 0
BT DW DR 60 61 62 63
26
A data address breakpoint match is detected for a load or store instruction if the three following conditions are met for any byte accessed: EA[060] = DABR[DAB] MSR[DR] = DABR[BT] The instruction is a store and DABR[DW] = 1, or the instruction is a load and DABR[DR] = 1.
In 32-bit mode of a 64-bit implementation, the high-order 32 bits of the EA are treated as zero for the purpose of detecting a match.
The high-order bits of the resource ID (RID) eld that correspond to bits of the RID beyond the width of the RID supported by a particular implementation are treated as reserved bits. The EAR register is provided to support the External Control In Word Indexed (eciwx) and External Control Out Word Indexed (ecowx) instructions. Access to the EAR is supervisorlevel, thus the operating system can determine which tasks are allowed to issue external access instructions and when they are allowed to do so. The bit settings for the EAR are described in Table 19.
27
The data access of eciwx and ecowx is performed as though the memory access mode bits (WIMG) were 0101. For example, if the external control facility is used to support a graphics adapter, the ecowx instruction could be used to send the translated physical address of a buffer containing graphics data to the graphics device. The eciwx instruction could be used to load status information from the graphics adapter.
Table 19. External Access Register (EAR) Bit Settings
Bit 0 E Name Description Enable bit 1 Enabled 0 Disabled If this bit is set, the eciwx and ecowx instructions can perform the specied external operation. If the bit is cleared, an eciwx or ecowx instruction causes a DSI exception. Reserved Resource ID
125 2631
RID
This register can also be accessed by using the mtspr and mfspr instructions.
The T bit in the segment descriptor selects between memory segments and direct-store segments, as shown in Table 20.
28
All accesses generated by the processor map to a segment descriptor. If MSR[IR] = 0 or MSR[DR] = 0 for an instruction or data access, respectively, then real addressing mode translation is performed. Otherwise, if T = 0 in the corresponding segment descriptor (and the address is not translated by the BAT mechanism), the access maps to memory space and page address translation is performed. After a memory segment is selected, the processor creates the virtual address for the segment and searches for the PTE that dictates the physical page number to be used for the access. Note that I/O devices can be easily mapped into memory space and used as memory-mapped I/O.
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The translation of effective addresses to physical addresses for 32-bit implementations is similar to that for 64-bit implementations, except that 32-bit implementations index into an array of 16 segment registers instead of segment tables in memory to locate the segment descriptor, and the address ranges are obviously different. Thus, the address translation is as follows: Bits 03 of the effective address comprise the segment register number used to select a segment descriptor, from which the virtual segment ID (VSID) is extracted. Bits 419 of the effective address correspond to the page number within the segment; these are concatenated with the VSID from the segment descriptor to form the virtual page number (VPN). The VPN is used to search for the PTE in either an on-chip TLB or the page table. The PTE then provides the physical page number (RPN). Bits 2031 of the effective address are the byte offset within the page; these are concatenated with the RPN eld of a PTE to form the physical address used to access memory.
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mechanism. Figure 25 shows the format of both double words that comprise a T = 0 segment descriptor (or STE) in a 64-bit implementation.
Reserved ESID 0 000000000000000000000 V 35 36 T Ks Kp N 000 63
55 56 57 58 59 60 61
VSID 0 51 52
00000000000 63
Table 21 lists the bit denitions for each double word in an STE.
Table 21. STE Bit Definitions for Page Address Translation64-Bit Implementations
Double Word 0 Bit 035 3655 56 57 58 59 60 6163 1 051 5263 Name ESID V T Ks Kp N VSID Description Effective segment ID Reserved Entry valid (V = 1) or invalid (V = 0) T = 0 selects this format Supervisor-state protection key User-state protection key No-execute protection bit Reserved Virtual segment ID Reserved
The Ks and Kp bits partially dene the access protection for the pages within the segment. The virtual segment ID eld is used as the high-order bits of the virtual page number (VPN). The segment descriptors are programmed by the operating system and placed into segment tables in memory, although some processors may additionally have on-chip segment lookaside buffers (SLBs). These SLBs store copies of recently-used STEs that can be accessed quickly, providing increased overall performance.
31
ASR is shown in Figure 26. The ASR contains bits 051 of the 64-bit physical base address of the segment table. Bits 5256 of the STEG address are derived from the hashing function, (and bits 5763 are zero at the beginning of a segment table search operation to point to the beginning of an STEG). Therefore, the beginning of the segment table lies on a 212 byte (4 Kbyte) boundary. Note that unless all accesses to be performed by the processor can be translated by the BAT mechanism when address translation is enabled (MSR[DR] or MSR[IR] = 1), the ASR must point to a valid segment table. If the processor does not support 64 bits of physical address, software should write zeros to those unsupported bits in the ASR. Otherwise, a machine check exception can occur. Additionally, values x0, 0x1000, and 0x2000 should not be used as segment table addresses as they correspond to areas of the exception vector table reserved for implementationspecic purposes.
Reserved
000000000000
51 52 63
Figure 27. Segment Register Format for Page Address Translation32-Bit Implementations
Table 22 provides the corresponding bit denitions of the segment register in 32-bit implementations.
32
Table 22. Segment Register Bit Definition for Page Address Translation32-Bit Implementations
Bit 0 1 2 3 47 831 T Ks Kp N VSID Name Description T = 0 selects this format Supervisor-state protection key User-state protection key No-execute protection bit Reserved Virtual segment ID
The Ks and Kp bits partially dene the access protection for the pages within the segment. The virtual segment ID eld is used as the high-order bits of the virtual page number (VPN). The segment register instructions are summarized in Table 23. These instructions are privileged in that they are executable only while operating in supervisor mode.
Table 23. Segment Register Instructions32-Bit Implementations Only
Instruction mtsr SR,rS mtsrin rS,rB mfsr rD,SR mfsrin rD,rB Description Move to Segment Register SR[SR] rS Move to Segment Register Indirect SR[rB[03]]rS Move from Segment Register rDSR[SR] Move from Segment Register Indirect rDSR[rB[03]]
33
Reserved 0000 63
55 56 57 58 59 60
63
Table 24 shows the bit denitions for the segment descriptors when the T bit is set for 64bit implementations.
Table 24. Segment Descriptor Bit Definitions for Direct-Store Segments64-Bit Implementations
Double Word 0 035 3655 56 57 58 59 6163 1 063 Bit Name ESID V T Ks Kp Description Effective segment ID Reserved Entry valid (V = 1) or invalid (V = 0) T = 0 selects this format Supervisor-state protection key User-state protection key Reserved Device specic data for I/O controller
In 32-bit implementations, the segment descriptors reside in one of 16 segment registers. Figure 29 shows the register format for the segment registers when the T bit is set for 32bit implementations.
T Ks Kp 0 1 2 3 BUID 11 12 Controller-Specific Information 31
34
Table 25 shows the bit denitions for the segment registers when the T bit is set for 32-bit implementations.
Table 25. Segment Register Bit Definitions for Direct-Store Segments
Bit 0 1 2 311 1231 T Ks Kp BUID Name Description T = 1 selects this format. Supervisor-state protection key User-state protection key Bus unit ID Device specic data for I/O controller
Conceptually, the page table in memory must be searched to translate the address of every reference.
35
the memory protection mechanism. Figure 30 shows the format of the two double words that comprise a PTE for 64-bit implementations.
Reserved 0 VSID RPN 0 51 52 API 000 51 52 R C 56 57 00000 WIMG 0 61 62 63 H V
PP
54 55 56 57
60 61 62 63
Table 26 lists the corresponding bit denitions for each double word in a PTE as dened above.
Table 26. PTE Bit Definitions64-Bit Implementations
Double Word 0 051 Bit Name VSID Description Virtual segment IDcorresponds to the high-order bits of the virtual page number (VPN) Abbreviated page index Reserved Hash function identier Entry valid (V = 1) or invalid (V = 0) Physical page number Reserved Referenced bit Changed bit Memory/cache access control bits Reserved Page protection bits
The PTE contains an abbreviated page index rather than the complete page index eld because at least 11 of the low-order bits of the page index are used in the hash function to select a PTE group (PTEG) address (PTEG addresses dene the location of a PTE). Therefore, these 11 lower-order bits are not repeated in the PTEs of that PTEG.
36
22 23 24 25
28 29 30 31
Table 27 lists the corresponding bit denitions for each word in a PTE as dened above.
Table 27. PTE Bit Definitions32-Bit Implementations
Word 0 0 124 25 2631 1 019 2022 23 24 2528 29 3031 Bit V VSID H API RPN R C WIMG PP Name Description Entry valid (V = 1) or invalid (V = 0) Virtual segment ID Hash function identier Abbreviated page index Physical page number Reserved Referenced bit Changed bit Memory/cache control bits Reserved Page protection bits
In this case, the PTE contains an abbreviated page index rather than the complete page index eld because at least ten of the low-order bits of the page index are used in the hash function to select a PTEG address (PTEG addresses dene the location of a PTE). Therefore, these ten lower-order bits are not repeated in the PTEs of that PTEG.
37
2.3.3.1 SDR1 Register Denition for 64-Bit Implementations The format of the SDR1 register for a 64-bit implementation is shown in Figure 32 and the bit settings are described in Table 28.
Reserved
HTABORG 0 45 46
0000000000000
HTABSIZE 63
58 59
Figure 32. SDR1 Register Format64-Bit Implementations Table 28. SDR1 Register Bit Settings64-Bit Implementations
Bits 045 4658 59-63 Name HTABORG HTABSIZE Description Physical base address of page table Reserved Encoded size of page table (used to generate mask)
The HTABORG eld in SDR1 contains the high-order 46 bits of the 64-bit physical address of the page table. Therefore, the beginning of the page table lies on a 218 byte (256 Kbyte) boundary at a minimum. If the processor does not support 64 bits of physical address, software should write zeroes to those unsupported bits in the HTABORG eld (as the implementation treats them as reserved). Otherwise, a machine check exception can occur. A page table can be any size 2 bytes where 18 n 46. The HTABSIZE eld in SDR1 contains an integer value that species how many bits from the output of the hashing function are used as the page table index. HTABSIZE is used to generate a mask of the form 0b00...011...1 (a string of (HTABSIZE 28) 0 bits followed by a string of 1 bits). As the table size increases, more bits are used from the output of the hashing function to index into the table. The 1 bits in the mask determine how many additional bits (beyond the minimum of 11) from the hash are used in the index; the HTABORG eld must have this same number of lower-order bits equal to 0. 2.3.3.2 SDR1 Register Denition for 32-Bit Implementations The format of SDR1 for 32-bit implementations is similar to that of 64-bit implementations except that the register size is 32 bits and the HTABMASK eld is programmed explicitly into SDR1. Additionally, the address ranges correspond to a 32-bit physical address and the range of page table sizes is smaller. Figure 33 shows the format of the SDR1 register for 32-bit implementations; the bit settings are described in Table 29.
n
38
Reserved
HTABORG 0 15 16
0000000 22 23
HTABMASK 31
Figure 33. SDR1 Register Format32-Bit Implementations Table 29. SDR1 Register Bit Settings32-Bit Implementations
Bits 015 1622 2331 Name HTABORG HTABMASK Description Physical base address of page table Reserved Mask for page table address
The HTABORG eld in SDR1 contains the high-order 16 bits of the 32-bit physical address of the page table. Therefore, the beginning of the page table lies on a 216 byte (64 Kbyte) boundary at a minimum. As with 64-bit implementations, if the processor does not support 32 bits of physical address, software should write zeroes to those unsupported bits in the HTABORG eld (as the implementation treats them as reserved). Otherwise, a machine check exception can occur. A page table can be any size 2 bytes where 16 n 25. The HTABMASK eld in SDR1 contains a mask value that determines how many bits from the output of the hashing function are used as the page table index. This mask must be of the form 0b00...011...1 (a string of 0 bits followed by a string of 1 bits). As the table size increases, more bits are used from the output of the hashing function to index into the table. The 1 bits in HTABMASK determine how many additional bits (beyond the minimum of 10) from the hash are used in the index; the HTABORG eld must have the same number of lower-order bits equal to 0 as the HTABMASK eld has lower-order bits equal to 1.
n
39
Machine check
00200
DSI
00300
ISI
00400
00500
00600
Program
00700
Floating-point unavailable
00800
40
00E00
00E1000FFF 0100002FFF
BD (1629)
BI (1115) BO (610)
41
FM (714) frA (1115) frB (1620) frC (2125) frD (610) frS (610) IMM (1619) L (10) LI (629) LK (31)
42
rD (610) rS (610) SH (1620) SIMM (1631) SR (1215) TO (610) UIMM (1631) XO (2129, 2130, 2230, 2630, 2729, 2730, or 3031)
Split eldsmb, me, sh, spr, and tbrare described in Table 32.
Table 32. Split-Field Notation and Conventions
Field mb (2126) me (2126) sh (1620) and sh (30) spr (1120) tbr (1120) Description Field used in rotate instructions to specify the rst 1 bit of a 64-bit mask (32 bits in 32-bit implementations). This eld is dened in 64-bit implementations only. Field used in rotate instructions to specify the last 1 bit of a 64-bit mask (32 bits in 32-bit implementations). This eld is dened in 64-bit implementations only. Fields used to specify a shift amount (64-bit implementations only). Field used to specify a special purpose register for the mtspr and mfspr instructions. Field used to specify either the time base lower (TBL) or time base upper (TBU).
43
This section lists the PowerPC architectures instruction set. Instructions are sorted by mnemonic and opcode. Note that split fields, that represent the concatenation of sequences from left to right, are shown in lowercase. Table 33 lists the instructions implemented in the PowerPC architecture in alphabetical order by mnemonic.
Key: Reserved bits
31 31 31 14 12 13 15 31 31 31 31 28 29 18 16 19 19 31 11 31 10 31 31 19
D D D D D D D D D S S S S
A A A A A A A A A A A A A
B B B
266 10 138
Rc Rc Rc
00000 00000 B B
OE OE
Rc Rc Rc Rc
LI BO BO BO crfD crfD crfD crfD S S crbD 0 L 0 L 0 L 0 L BI BI BI A A A A A A crbA 00000 00000 crbB B UIMM 58 26 257 00000 00000 B SIMM 32 BD 528 16 0
AA LK AA LK LK LK 0
Rc Rc 0
44
Name crandc creqv crnand crnor cror crorc crxor dcbf dcbi 1 dcbst dcbt dcbtst dcbz divdx 4 divdux 4 divwx divwux eciwx ecowx eieio eqvx extsbx extshx extswx 4 fabsx faddx faddsx fcfidx
4
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
19 19 19 19 19 19 19 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 63 63 59 63 63 63 63 63 63
crbD crbD crbD crbD crbD crbD crbD 00000 00000 00000 00000 00000 00000 D D D D D S 00000 S S S S D D D D crfD crfD D D D 00 00
crbA crbA crbA crbA crbA crbA crbA A A A A A A A A A A A A 00000 A A A A 00000 A A 00000 A A 00000 00000 00000
crbB crbB crbB crbB crbB crbB crbB B B B B B B B B B B B B 00000 B 00000 00000 00000 B B B B B B B B B 00000 00000 OE OE OE OE
129 289 225 33 449 417 193 86 470 54 278 246 1014 489 457 491 459 310 438 854 284 954 922 986 264 21 21 846 32 0 814 815 14
0 0 0 0 0 0 0 0 0 0 0 0 0 Rc Rc Rc Rc 0 0 0 Rc Rc Rc Rc Rc Rc Rc Rc 0 0 Rc Rc Rc
45
Name fctiwzx fdivx fdivsx fmaddx fmaddsx fmrx fmsubx fmsubsx fmulx fmulsx fnabsx fnegx fnmaddx fnmaddsx fnmsubx fnmsubsx fresx 5 frspx frsqrtex
5
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
63 63 59 63 59 63 63 59 63 59 63 63 63 59 63 59 59 63 63 63 63 59 63 59 31 19 34 35 31 31 58 31 58
D D D D D D D D D D D D D D D D D D D D D D D D 00000 00000 D D D D D D D
00000 A A A A 00000 A A A A 00000 00000 A A A A 00000 00000 00000 A 00000 00000 A A A 00000 A A A A A A A
B B B B B B B B 00000 00000 B B B B B B B B B B B B B B B 00000 d d B B ds B ds 00000 C 00000 00000 00000 00000 C C C C 00000 C C C C 00000 00000 C C
Rc Rc Rc Rc Rc Rc Rc Rc Rc Rc Rc Rc Rc Rc Rc Rc Rc Rc Rc Rc Rc Rc Rc Rc 0 0
fselx 5 fsqrtx 5 fsqrtsx 5 fsubx fsubsx icbi isync lbz lbzu lbzux lbzx ld 4 ldarx 4 ldu 4
119 87 0 84 1
0 0
46
Name ldux
4
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
31 31 50 51 31 31 48 49 31 31 42 43 31 31 31 40 41 31 31 46 31 31 58 31 31 31 31 32 33 31 31 19 63 crfD crfD
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D 00 00 crfS crfS
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 00 00
B B d d B B d d B B d d B B B d d B B d NB B ds B B B B d d B B 00000 00000
53 21
0 0
ldx 4 lfd lfdu lfdux lfdx lfs lfsu lfsux lfsx lha lhau lhaux lhax lhbrx lhz lhzu lhzux lhzx lmw 3 lswi 3 lswx 3 lwa 4 lwarx lwaux 4 lwax 4 lwbrx lwz lwzu lwzux lwzx mcrf mcrfs
631 599
0 0
567 535
0 0
0 0 0
311 279
0 0
0 0
0 0 0 0
55 23 0 64
0 0 0 0
47
Name mcrxr mfcr mffsx mfmsr 1 mfspr 2 mfsr 1,6 mfsrin 1,6 mftb mtcrf mtfsb0x mtfsb1x mtfsfx mtfsfix mtmsr 1 mtspr 2 mtsr 1,6 mtsrin 1,6 mulhdx 4 mulhdux4 mulhwx mulhwux mulldx 4 mulli mullwx nandx negx norx orx orcx ori oris rfi 1 rldclx 4
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
31 31 63 31 31 31 31 31 31 63 63 63 63 31 31 31 31 31 31 31 31 31 7 31 31 31 31 31 31 24 25 19 30 0
00
0 0 Rc 0 0 0 0 0 0 Rc Rc Rc Rc 0 0 0 0 Rc Rc Rc Rc Rc
00000 B tbr
00000
0 00000 00000
FM
CRM
00000 00000 0 B
IMM
crfD S S S S D D D D D D D S D S S S S S
00
00000
00000 A A A A A A A A A A A A A A 00000 A
Rc Rc Rc Rc Rc Rc
00000 S
50 8
0 Rc
48
Name rldcrx
4
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
30 30 30 30 30 20 21 23 17 31 31 31 31 31 31 31 31 31 31 38 39 31 31 62 31 62 31 31 54 55 31 31 31
B sh sh sh sh SH SH B
me mb mb me mb MB MB MB 00000000000000 2 0 1 3
Rc
sh Rc sh Rc sh Rc sh Rc
rldicx 4 rldiclx 4 rldicrx 4 rldimix 4 rlwimix rlwinmx rlwnmx sc slbia 1,4,5 slbie 1,4,5 sldx 4 slwx sradx 4 sradix 4 srawx srawix srdx 4 srwx stb stbu stbux stbx std 4 stdcx. 4 stdu 4 stdux 4 stdx
4
ME ME ME
Rc Rc Rc 1 0 0 0 Rc Rc Rc
sh Rc
00000 B B B B sh B SH B B d d B B ds B ds B B d d B B B
Rc Rc Rc Rc
0 0
0 0
0 0 0
49
Name stfs stfsu stfsux stfsx sth sthbrx sthu sthux sthx stmw 3 stswi 3 stswx
3
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
52 53 31 31 44 31 45 31 31 47 31 31 36 31 31 37 31 31 31 31 31 08 31 31 31 31 02 31 31 31 31 03 31
d d 695 663 d 918 d 439 407 d 725 661 d 662 150 d 183 151 40 8 136 SIMM 232 200 598 68 SIMM 370 306 566 4 SIMM 316 Rc 0 0 0 0 Rc Rc 0 0 0 0 Rc Rc Rc 0 1 0 0 0 0 0 0 0
stw stwbrx stwcx. stwu stwux stwx subfx subfcx subfex subfic subfmex subfzex sync td 4 tdi
4
50
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
26 27
S S
A A
UIMM UIMM
1 2
Supervisor-level instruction Supervisor- and user-level instruction and store string or multiple instruction 4 64-bit instruction 5 Optional instruction 6 32-bit instruction only
3 Load
Table 34 lists the instructions dened in the PowerPC architecture in numeric order by opcode.
Key: Reserved bits
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
000010 000011 000111 001000 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010011 010011 010011 010011 010011 010011
A A A A A A A A A A BI 00000 LI
SIMM SIMM SIMM SIMM UIMM SIMM SIMM SIMM SIMM SIMM BD 000000000000000 AA LK 1 0 AA LK 0000000000 0000010000 0000100001 0000110010 0010000001 0010010110 0011000001 0 LK 0 0 0 0 0
twi mulli subfic cmpli cmpi addic addic. addi addis bcx sc bx mcrf bclrx crnor rfi crandc isync crxor
crfD BO crbD
00
crfS BI crbA
00
51
Name crnand crand creqv crorc cror bcctrx rlwimix rlwinmx rlwnmx ori oris xori xoris andi. andis. rldiclx 4 rldicrx 4 rldicx 4 rldimix rldclx
4 4
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
010011 010011 010011 010011 010011 010011 010100 010101 010111 011000 011001 011010 011011 011100 011101 011110 011110 011110 011110 011110 011110 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111
0011100001 0100000001 0100100001 0110100001 0111000001 1000010000 MB MB MB UIMM UIMM UIMM UIMM UIMM UIMM ME ME ME
0 0 0 0 0 LK Rc Rc Rc
sh sh sh sh B B B B B B B B 00000 B B B B 00000 OE 0 OE 0
mb me mb mb mb me
sh Rc sh Rc sh Rc sh Rc
Rc Rc 0 0 Rc Rc Rc Rc 0 0 0 0 Rc Rc
rldcrx 4 cmp tw subfcx mulhdux 4 addcx mulhwux mfcr lwarx ldx 4 lwzx slwx cntlzwx
01001
0000000000 0000000100 0000001000 0000001001 0000001010 0000001011 0000010011 0000010100 0000010101 0000010111 0000011000 0000011010
52
Name sldx
4
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 crfD
S S 0 L D D 00000 D S S TO D D D D 00000 D D D S D D S S S S S S S D D S S S 0 0
A A A A A A A A A A A A 00000 A A A A A A A A
CRM
0000011011 0000011100 0000100000 0000101000 0000110101 0000110110 0000110111 0000111010 0000111100 0001000100 0001001001 0001001011 0001010011 0001010100 0001010110 0001010111 0001101000 0001110111 0001111100 0010001000 0010001010 0010010000 0010010010 0010010101 0010010110 0010010111 0010110101 0010110111 0011001000 0011001010 0011010010 0011010110 0011010111
Rc Rc 0 Rc 0 0 0 Rc Rc 0 Rc Rc 0 0 0 0 Rc 0 Rc Rc Rc 0 0 0 1 0 0 0 Rc Rc 0 1 0
andx cmpl subfx ldux 4 dcbst lwzux cntlzdx 4 andcx td 4 mulhdx 4 mulhwx mfmsr ldarx 4 dcbf lbzx negx lbzux norx subfex addex mtcrf mtmsr stdx 4 stwcx. stwx stdux 4 stwux subfzex addzex mtsr 1,6 stdcx. 4 stbx
00000 A A A A A A A
SR
A A
53
Name subfmex mulld 4 addmex mullwx mtsrin 1,6 dcbtst stbux addx dcbt lhzx eqvx tlbie 1,5 eciwx lhzux xorx mfspr 2 lwax 4 lhax tlbia
1,5
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111
00000 B 00000 B B B B B B B B B B B B
OE OE OE OE
Rc Rc Rc Rc 0 0 0 Rc 0 0 Rc 0 0 0 Rc 0 0 0 0 0 0 0 0 Rc
sh Rc
OE
B B 00000
mftb lwaux 4 lhaux sthx orcx sradix 4 slbie 1,4,5 ecowx sthux orx divdux 4 divwux mtspr 2 dcbi
B B B B sh B B B B B B OE OE
0101110101 0101110111 0110010111 0110011100 1100111011 0110110010 0110110110 0110110111 0110111100 0111001001 0111001011 0111010011
0 0 0 Rc Rc Rc 0 0
0111010110
54
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111 011111
0111011100 0111101001 0111101011 0111110010 1000000000 1000010101 1000010110 1000010111 1000011000 1000011011 1000110110 1000110111 1001010011 1001010101 1001010110 1001010111 1001110111 1010010011 1010010101 1010010110 1010010111 1010110111 1011010101 1011010111 1011110111 1100010110 1100011000 1100011010 1100111000 1101010110 1110010110 1110011010 1110111010
Rc Rc Rc 0 0 0 0 0 Rc Rc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rc Rc Rc 0 0 Rc Rc
lswi 3 sync lfdx lfdux mfsrin 1,6 stswx 3 stwbrx stfsx stfsux stswi 3 stfdx stfdux lhbrx srawx sradx 4 srawix eieio sthbrx extshx extsbx
55
Name icbi stfiwx 5 extsw 4 dcbz lwz lwzu lbz lbzu stw stwu stb stbu lhz lhzu lha lhau sth sthu lmw
3
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
011111 011111 011111 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111010 111010 111010 111011 111011
00000 S S 00000 D D D D S S S S D D D D S S D S D D D D S S S S D D D D D
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
B B 00000 B
0 0 Rc 0
stmw 3 lfs lfsu lfd lfdu stfs stfsu stfd stfdu ld 4 ldu 4 lwa 4 fdivsx fsubsx
00 01 10 10010 10100 Rc Rc
B B
00000 00000
56
Name faddsx fsqrtsx 5 fresx 5 fmulsx fmsubsx fmaddsx fnmsubsx fnmaddsx std 4 stdu 4 fcmpu frspx fctiwx fctiwzx fdivx fsubx faddx fsqrtx 5 fselx 5 fmulx frsqrtex 5 fmsubx fmaddx fnmsubx fnmaddx fcmpo mtfsb1x fnegx mcrfs mtfsb0x fmrx mtfsfix fnabsx
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
111011 111011 111011 111011 111011 111011 111011 111011 111110 111110 111111 111111 111111 111111 111111 111111 111111 111111 111111 111111 111111 111111 111111 111111 111111 111111 111111 111111 111111 111111 111111 111111 111111 crfD crfD crfD crfD
D D D D D D D D S S 00 D D D D D D D D D D D D D D 00
A 00000 00000 A A A A A A A A 00000 00000 00000 A A A 00000 A A 00000 A A A A A 00000 00000 00 crfS 00
B B B 00000 B B B B
Rc Rc Rc Rc Rc Rc Rc Rc 00 01 0 Rc
0000000000 0000001100 0000001110 0000001111 00000 00000 00000 00000 C C 00000 C C C C 10010 10100 10101 10110 10111 11001 11010 11100 11101 11110 11111
Rc Rc Rc Rc Rc Rc Rc Rc Rc Rc Rc Rc 0 Rc Rc 0 Rc Rc Rc Rc
crbD D
crbD D 00 D
57
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
D D
FM
B 00000 B B B B
Rc Rc Rc Rc Rc Rc
D D D
1 2
Supervisor-level instruction Supervisor- and user-level instruction and store string or multiple instruction 4 64-bit instruction 5 Optional instruction 6 32-bit instruction only
3 Load
58
Motorola Inc. 1995 Portions hereof International Business Machines Corp. 19911995. All rights reserved. This document contains information on a new product under development by Motorola and IBM. Motorola and IBM reserve the right to change or discontinue this product without notice. Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or implied copyright or patent licenses granted hereunder by Motorola or IBM to design, modify the design of, or fabricate circuits based on the information in this document. The PowerPC 60x microprocessors embody the intellectual property of Motorola and of IBM. However, neither Motorola nor IBM assumes any responsibility or liability as to any aspects of the performance, operation, or other attributes of the microprocessor as marketed by the other party or by any third party. Neither Motorola nor IBM is to be considered an agent or representative of the other, and neither has assumed, created, or granted hereby any right or authority to the other, or to any third party, to assume or create any express or implied obligations on its behalf. Information such as data sheets, as well as sales terms and conditions such as prices, schedules, and support, for the product may vary as between parties selling the product. Accordingly, customers wishing to learn more information about the products as marketed by a given party should contact that party. Both Motorola and IBM reserve the right to modify this manual and/or any of the products as described herein without further notice. NOTHING IN THIS MANUAL, NOR IN ANY OF THE ERRATA SHEETS, DATA SHEETS, AND OTHER SUPPORTING DOCUMENTATION, SHALL BE INTERPRETED AS THE CONVEYANCE BY MOTOROLA OR IBM OF AN EXPRESS WARRANTY OF ANY KIND OR IMPLIED WARRANTY, REPRESENTATION, OR GUARANTEE REGARDING THE MERCHANTABILITY OR FITNESS OF THE PRODUCTS FOR ANY PARTICULAR PURPOSE. Neither Motorola nor IBM assumes any liability or obligation for damages of any kind arising out of the application or use of these materials. Any warranty or other obligations as to the products described herein shall be undertaken solely by the marketing party to the customer, under a separate sale agreement between the marketing party and the customer. In the absence of such an agreement, no liability is assumed by Motorola, IBM, or the marketing party for any damages, actual or otherwise. Typical parameters can and do vary in different applications. All operating parameters, including Typicals, must be validated for each customer application by customers technical experts. Neither Motorola nor IBM convey any license under their respective intellectual property rights nor the rights of others. Neither Motorola nor IBM makes any claim, warranty, or representation, express or implied, that the products described in this manual are designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the product could create a situation where personal injury or death may occur. Should customer purchase or use the products for any such unintended or unauthorized application, customer shall indemnify and hold Motorola and IBM and their respective ofcers, employees, subsidiaries, afliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola or IBM was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Afrmative Action Employer.
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