Reg. No.

M.E. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2010 First Semester VLSI Design

VL 9212 VLSI DESIGN TECHNIQUES (Common to M.E. Applied Electronics) (Regulation 2009) Time : Three hours Answer ALL questions

PART A (10 2 = 20 Marks) 1. 2. 3. 4. 5. 6. 7. 8. 9.

Give two reasons as to why polysilicon is used as Gate material in VLSI. What is pinch off? What is its effect?

Mention the drawbacks of pass transistor logic. What is body effect? Show the same for PMOSFET. Placement and routing have to be optimal in VLSI design, why? What is DFT? What is its philosophy? Indicate any two ways to reduce power in a CMOS IC. Differentiate concurrent statements from sequential statements.

10.

List the operators used in Verilog.

Give Noise margin 0 and Noise margin 1 of a CMOS gate.

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Maximum : 100 Marks

Question Paper Code :

98077

PART B (5 16 = 80 Marks) 11. (a) (i) With the help of structure and transfer characteristic differentiate the working of an enhancement type NMOSFET from depletion type NMOSFET. (8)

(ii)

Write the expression for the threshold voltage of a NMOSFET. Briefly explain all the terms. (8) Or

(b)

(i) (ii)

Explain any two secondary effects of a MOSFET.

Illustrate the fabrication steps involved in a twintub CMOS IC. (10) Compare the design of a 4 : 1 MUX built using transmission gates with the one built using static CMOS gates. (8) Implement the following Boolean gates using static CMOS structures.

12.

(a)

(i) (ii)

Or (b) (i) (ii) 13. (a) (i) (ii)

Explain the working of a domino logic.

0
Or Or 2

2I/P AND gate, 2-I/P OR gate, 2-I/P ExOR gate and 2I/P ExNOR gate. (8)

What is meant by transmission gate? Design a 2 1 mux using transmission gate. (10)

What do you mean by transistor sizing? Clearly answer as to why is it done? (6)

(b)

(i) (ii)

Discuss the different scaling models that are prevalent in VLSI. Illustrate them with examples. (10) What are the limitations of scaling? Explain. (6)

14.

(a)

(i)

Starting from basics, design and explain a 4 bit high speed adder. (8) Explain the working of a 4 4 multiplier with examples. (8)

(ii)

Derive an expression for dynamic power dissipation of a CMOS IC. Comment on the same. (10)

0
(6) (6)

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(b)

(i) (ii)

What is Physical design in VLSI? Elaborate the same.

(8)

s-a-1 A B

C D E

s-a-0

Fig. 14 (b) 15. (a) (i)

Explain functions with suitable examples, with respect to Verilog. (8)

(b)

(i)

Write a Verilog Code for +ve edge triggered DFlip-Flop using data flow modeling. Show the waveforms also. (8) Explain the complete flow diagram of digital system design using Verilog (HDL). (8)

(ii)

4
3

Or

(ii)

Write a Verilog Code for 3 to 8 decoder using gate level primitives. (8)

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98077

0
Y

For the circuit shown in Fig. 14 (b), generate, test vectors to detect the sa1 and sa0 faults shown. Also indicate the other faults covered by the test vectors generated. (8)