TIBPAL22V10-10C HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS015 D3972, FEBRUARY 1992

Second-Generation PLD Architecture High-Performance Operation: fmax (External Feedback) . . . 71 MHz Propagation Delay . . . 10 ns Max Increased Logic Power Up to 22 Inputs and 10 Outputs Increased Product Terms Average of 12 Per Output Variable Product Term Distribution Allows More Complex Functions to Be Implemented Each Output Is User Programmable for Registered or Combinational Operation, Polarity, and Output Enable Control Power-Up Clear on Registered Outputs TTL-Level Preload for Improved Testability Extra Terms Provide Logical Synchronous Set and Asynchronous Reset Capability Fast Programming, High Programming Yield, and Unsurpassed Reliability Ensured Using Ti-W Fuses AC and DC Testing Done at the Factory Utilizing Special Designed-In Test Features Dependable Texas Instruments Quality and Reliability Package Options Include Plastic Dual-In-Line and Chip Carrier Packages
CLK/I I I I I I I I I I I GND

NT PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13

VCC I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I

FN PACKAGE (TOP VIEW)

I I I NC I I I

5 6 7 8 9 10

I I CLK/I NC VCC I/O/Q I/O/Q

4 3 2 1 28 27 26 25 24 23 22 21 20 11 19 12 13 14 15 16 17 18

I/O/Q I/O/Q I/O/Q NC I/O/Q I/O/Q I/O/Q

NC No internal connection Pin assignments in operating mode

description
The TIBPAL22V10-10C is a programmable array logic device featuring high speed and functional equivalency when compared to presently available devices. They are implemented with the familiar sum-of-products (AND-OR) logic structure featuring the new concept Programmable Output Logic Macrocell. These IMPACT-X circuits combine the latest Advanced Low-Power Schottky technology with proven titaniumtungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic. These devices contain up to 22 inputs and 10 outputs. They incorporate the unique capability of defining and programming the architecture of each output on an individual basis. Outputs may be registered or nonregistered and inverting or noninverting as shown in the output logic macrocell diagram. The ten potential outputs are enabled through the use of individual product terms. Further advantages can be seen in the introduction of variable product term distribution. This technique allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output. This variable allocation of terms allows far more complex functions to be implemented than in previously available devices.
This device is covered by U.S. Patent 4,410,987. IMPACT-X is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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I I GND NC I I/O/Q I/O/Q

Copyright 1992, Texas Instruments Incorporated

TIBPAL22V10-10C HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS015 D3972, FEBRUARY 1992

description (continued)
Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term. These functions are common to all registers. When the synchronous set product term is a logic 1, the output registers are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous reset product term is a logic 1, the output registers are loaded with a logic 0. The output logic level after set or reset depends on the polarity selected during programming. Output registers can be preloaded to any desired state during testing. Preloading permits full logical verification during product testing. With features such as programmable output logic macrocells and variable product term distribution, the TIBPAL22V10-10C offers quick design and development of custom LSI functions with complexities of 500 to 800 equivalent gates. Since each of the ten output pins may be individually configured as inputs on either a temporary or permanent basis, functions requiring up to 21 inputs and a single output or down to 12 inputs and 10 outputs are possible. A power-up clear function is supplied that forces all registered outputs to a predetermined state after power is applied to the device. Registered outputs selected as active-low power up with their outputs high. Registered outputs selected as active-high power up with their outputs low. A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns. Once blown, the verification circuitry is disabled and all other fuses will appear to be open. The TIBPAL22V10-10C is characterized for operation from 0C to 75C.

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SRPS015 D3972, FEBRUARY 1992

functional block diagram (positive logic)

C1 & 44 x 132 8 Set Reset 1 1S R Output Logic Macrocell

I/O/Q EN I/O/Q

10 CLK/I 22 EN I/O/Q 14 EN I/O/Q 16 EN I/O/Q 16 I 11 10 22 EN I/O/Q 14 EN I/O/Q 12 EN I/O/Q 10 EN I/O/Q 8 EN I/O/Q 10 10 denotes fused inputs EN 10

12

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logic diagram (positive logic)

CLK/I 1 Increment
0 4 8 12 16 20 24 28 32 36 40

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TIBPAL22V10-10C HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS

First Fuse Numbers

Asynchronous Reset (to all registers)

Macrocell

23

I/O/Q

396
P = 5808 R = 5809

440

Macrocell

22

I/O/Q

880

2
924

P = 5810 R = 5811

Macrocell

21

I/O/Q

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1452

3
1496

P = 5812 R = 5813

Macrocell

20

I/O/Q

2112

4
2156

P = 5814 R = 5815

Macrocell

19

I/O/Q

2860

P = 5816 R = 5817

2904

Macrocell

18

I/O/Q

TIBPAL22V10-10C HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS

3608

6
3652

P = 5818 R = 5819

Macrocell

17

I/O/Q

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4268

7
4312

P = 5820 R = 5821

Macrocell

16

I/O/Q

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5

4840

8
4884

P = 5822 R = 5823

Macrocell

15

I/O/Q

5324

9
5368

P = 5824 R = 5825

SRPS015 D3972, FEBRUARY 1992

Macrocell
5720

14

I/O/Q

I I

10
5764

P = 5826 R = 5827

Synchronous Set (to all registers) 13 I

11

Fuse number = First Fuse number + Increment Inside each MACROCELL the P fuse is the polarity fuse and the R fuse is the register fuse.

TIBPAL22V10-10C HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS015 D3972, FEBRUARY 1992

output logic macrocell diagram

Output Logic Macrocell MUX 2 AR R I=0 1D C1 SS From Clock Buffer MUX 1 1 G1 1S 3 0 1 1 0 S0 G 0 3

S1

AR = asynchronous reset SS = synchronous set

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SRPS015 D3972, FEBRUARY 1992

R 1D C1 1S S1 = 0 S0 = 0

R 1D C1 1S S1 = 0 S0 = 1

REGISTER FEEDBACK, REGISTERED, ACTIVE-LOW OUTPUT

REGISTER FEEDBACK, REGISTERED, ACTIVE-HIGH OUTPUT

S1 = 1 S0 = 0

S1 = 1 S0 = 1

I/O FEEDBACK, COMBINATIONAL, ACTIVE-LOW OUTPUT

I/O FEEDBACK, COMBINATIONAL, ACTIVE-HIGH OUTPUT

MACROCELL FEEDBACK AND OUTPUT FUNCTION TABLE FUSE SELECT S1 S0 0 0 1 1 0 1 0 1 FEEDBACK AND OUTPUT CONFIGURATION Register feedback Register feedback I/O feedback I/O feedback Registered Registered Combinational Combinational Active low Active high Active low Active high

0 = unblown fuse, 1 = blown fuse S1 and S0 are select-function fuses as shown in the output logic macrocell diagram.

Figure 1. Resultant Macrocell Feedback and Output Logic After Programming

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SRPS015 D3972, FEBRUARY 1992

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 V to VCC +0.5 V Voltage range applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC +0.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 75C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.

recommended operating conditions

MIN VCC VIH VIL IOH IOL tw Supply voltage High-level input voltage (see Note 2) Low-level input voltage (see Note 2) High-level output current Low-level output current Clock high or low Pulse duration Asynchronous reset high or low Input Feedback tsu Setup time before clock Synchronous preset (active) Synchronous preset (inactive) Asynchronous reset (inactive) th TA Hold time, input, set, or feedback after clock Operating free-air temperature 5 10 7 7 9 8 8 0 0 75 ns C ns ns 4.75 2 NOM 5 MAX 5.25 5.5 0.8 3.2 16 UNIT V V V mA mA

NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and includes all overshoots due to system and/or tester noise. Testing these parameters should not be attempted without suitable equipment.

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SRPS015 D3972, FEBRUARY 1992

electrical characteristics over recommended operating free-air temperature range

PARAMETER VIK VOH VOL IOZH IOZL II IIH IIL IOS ICC Ci I CLK CLK All others VCC = 4.75 V, VCC = 4.75 V, VCC = 4.75 V, VCC = 5.25 V, VCC = 5.25 V, VCC = 5.25 V, VCC = 5.25 V, VCC = 5.25 V, VCC = 5.25 V, VCC = 5.25 V, f = 1 MHz, TEST CONDITIONS II = 18 mA IOH = 3.2 mA IOL = 16 mA VO = 2.7 V VO = 0.4 V VI = 5.5 V VI = 2.7 V VI = 0.4 V VO = 0.5 V VI = GND, VI = 2 V 30 Outputs open 6 6 MIN 2.4 0.35 0.5 0.1 0.1 1 25 0.25 0.1 130 210 TYP MAX 1.2 UNIT V V V mA mA mA A mA mA mA pF

Co f = 1 MHz, VO = 2 V 8 pF All typical values are at VCC = 5 V, TA = 25C. I/O leakage is the worst case of IOZL and IIL or IOZH and IIH, respectively. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to avoid test problems caused by test equipment ground degradation.

switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER fmax tpd tpd tpd tpd# ten tdis fmax (without feedback) = FROM (INPUT) TO (OUTPUT) TEST CONDITION MIN 100 80 71 R1 = 300 , R2 = 300 , See Figure 6 1 1 10 15 7 5.5 11 9 ns ns ns ns ns ns Q Q Feedback I/O, Q I/O, Q 1 MHz MAX UNIT

Without feedback With internal feedback (counter configuration) With external feedback I, I/O I, I/O (reset) CLK CLK I, I/O I, I/O t w(low) I/O

fmax (with internal feedback) = fmax (with external feedback) =

) tw(high) 1 t su ) t (CLK to feedback) pd

t su

1 (CLK to Q) pd # This parameter is calculated from the measured fmax with internal feedback in the counter configuration. t

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SRPS015 D3972, FEBRUARY 1992

preload procedure for registered outputs (see Notes 3 and 4)

The output registers can be preloaded to any desired state during device testing. This permits any state to be tested without having to step through the entire state-machine sequence. Each register is preloaded individually by following the steps given below: Step 1. Step 2. Step 3. Step 4. With VCC at 5 V and pin 1 at VIL, raise pin 13 to VIHH. Apply either VIL or VIH to the output corresponding to the register to be preloaded. Pulse pin 1, clocking in preload data. Remove output voltage, then lower pin 13 to VIL. Preload can be verified by observing the voltage level at the output pin.
VIHH Pin 13 tsu td Pin 1 tw VIH VIL VIH Registered I/O Input VIL Output VOL VOH td VIL

Figure 2. Preload Waveforms

NOTES: 3. Pin numbers shown are for the NT package only. If chip-carrier socket adapter is not used, pin numbers must be changed accordingly. 4. td = tsu = tw = 100 ns to 1000 ns. VIHH = 10.25 V to 10.75 V.

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power-up reset
Following power up, all registers are reset to zero. The output level depends on the polarity selected during programming. This feature provides extra flexibility to the system designer and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is important that the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable input and feedback setup times are met.
VCC 4V tpd (600 ns typ, 1000 ns MAX) Active High Registered Output VOH State Unknown 1.5 V VOL Active Low Registered Output VOH State Unknown 1.5 V VOL tsu VIH CLK 1.5 V tw This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data. This is the setup time for input or feedback. 1.5 V VIL 5V

Figure 3. Power-Up Reset Waveforms

programming information
Texas Instruments programmable logic devices can be programmed using widely available software and inexpensive device programmers. Complete programming specifications, algorithms, and the latest information on hardware, software, and firmware are available upon request. Information on programmers capable of programming Texas Instruments programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI distributor, or by calling Texas Instruments at (214) 997-5666.

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THERMAL INFORMATION thermal management of the TIBPAL22V10-10C

Thermal management of the TIBPAL22V10-10CNT and TIBPAL22V10-10CFN is necessary when operating at certain conditions of frequency, output loading, and outputs switching simultaneously. The device and system application will determine the appropriate level of management. Determining the level of thermal management is based on factors such as power dissipation (PD), ambient temperature (TA), and transverse airflow (FPM). Figures 4 (a) and 4 (b) show the relationship between ambient temperature and transverse airflow at given power dissipation levels. The required transverse airflow can be determined at a particular ambient temperature and device power dissipation level in order to ensure the device specifications. Figure 5 illustrates how power dissipation varies as a function of frequency and the number of outputs switching simultaneously. It should be noted that all outputs are fully loaded (CL = 50 pF). Since the condition of eight fully loaded outputs represents the worst-case condition, each application must be evaluated accordingly.
MINIMUM TRANSVERSE AIR FLOW vs AMBIENT TEMPERATURE
600 600

MINIMUM TRANSVERSE AIR FLOW vs AMBIENT TEMPERATURE

Minimum Transverse Air Flow ft/min

500

Minimum Transverse Air Flow ft/min

500

400

400

300 PD = 1.6 W PD = 1.4 W PD = 1.2 W PD = 1 W

300 PD = 1.6 W PD = 1.4 W PD = 1.2 W PD = 1 W

200

200

100

100

0 0 10 20 30 40 50 60 70 80 TA Ambient Temperature C (a) TIBPAL22V10-10CNT

0 0 10 20 30 40 50 60 70 80 TA Ambient Temperature C (b) TIBPAL22V10-10CFN

Figure 4

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THERMAL INFORMATION
POWER DISSIPATION vs FREQUENCY
2000 VCC = 5 V TA = 25 C CL = 50 pF 10 Outputs Switching 1600

P Power Dissipation mW D

1800

1400

1200

1000 1 Output Switching 800 1 2 4 10 20 40 100 200 f Frequency MHz

Figure 5

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SRPS015 D3972, FEBRUARY 1992

PARAMETER MEASUREMENT INFORMATION

5V

S1 R1 From Output Under Test CL (see Note A) R2 Test Point

LOAD CIRCUIT FOR 3-STATE OUTPUTS Timing Input tsu Data Input 1.5 V 3V 1.5 V 0 th 3V 1.5 V 0 (see Note B) VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Input tpd In-Phase Output tpd Out-of-Phase Output (see Note D) 1.5 V 1.5 V 1.5 V 1.5 V 0 tpd VOH 1.5 V VOL tpd VOH 1.5 V VOL Output Control (low-level enabling) ten 1.5 V 1.5 V 0 (see Note B) tdis Low-Level Pulse 3V 1.5 V 1.5 V 0 (see Note B) tw High-Level Pulse 3V 1.5 V 1.5 V 0

VOLTAGE WAVEFORMS PULSE DURATIONS

3V

2.7 V
Waveform 1 S1 Closed (see Note C) ten Waveform 2 S1 Open (see Note C) 1.5 V VOL tdis VOH 1.5 V

VOL + 0.5 V

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

0V

VOH 0.5 V

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis. B. All input pulses have the following characteristics: PRR 1 MHz, tr = tf = 2 ns, duty cycle = 50%. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. When measuring propagation delay times of 3-state outputs, switch S1 is closed. E. Equivalent loads may be used for testing.

Figure 6. Load Circuit and Voltage Waveforms

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TYPICAL CHARACTERISTICS
SUPPLY CURRENT vs FREE - AIR TEMPERATURE
220 7 6 Propagation Delay Time ns I CC Supply Current mA 210 VCC = 5.25 V 200 VCC = 5 V 5 tPLH (CLK to Q) 4 tPHL (CLK to Q) 3 2 1 tPLH (I, I/O to O, I/O) tPHL (I, I/O to O, I/O)

PROPAGATION DELAY TIME vs SUPPLY VOLTAGE

190 VCC = 4.75 V

TA = 25 C CL = 50 pF R1 = 300 R2 = 300 10 Outputs Switching 5 VCC Supply Voltage V 5.25

180 0 25 50 TA Free - Air Temperature C 75

0 4.75

Figure 7

Figure 8

PROPAGATION DELAY TIME vs FREE - AIR TEMPERATURE

7 6 Propagation Delay Time ns 5 4 tPHL (CLK to Q) 3 2 1 VCC = 5 V CL = 50 pF R1 = 300 R2 = 300 10 Output Switching 0 25 50 TA Free - Air Temperature C 75 pd Propagation Delay Time ns tPLH (I, I/O to O, I/O) tPHL (I, I/O to O, I/O) tPLH (CLK to Q) 16 14 12 10 8

PROPAGATION DELAY TIME vs LOAD CAPACITANCE

VCC = 5 V TA = 25 C R1 = 300 R2 = 300 1 Output Switching

tpd (I, I/O to O, I/O) 6 tpd (CLK to Q) 4 2 0 0 100 500 200 300 400 CL Load Capacitance pF 600

Figure 9

Figure 10

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TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME vs NUMBER OF OUTPUTS SWITCHING
7 1200 VCC = 5 V P Power Dissipation mW D 6 Propagation Delay Time ns

POWER DISSIPATION vs FREQUENCY 10 - BIT COUNTER MODE

1150

1100 TA = 0 C

3 VCC = 5 V TA = 25 C CL = 50 pF R1 = 300 R2 = 300 1 2 = tPLH (I, I/O to O, I/O) = tPHL (I, I/O to O, I/O) = tPLH (CLK to Q) = tPHL (CLK to Q) 7 10

1050 TA = 80 C TA = 25 C

1 6 7 6 3 4 5 Number of Outputs Switching

1000 1 2 4 10 20 40 100 f Frequency MHz

Figure 11

Figure 12

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SRPS015

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