8

zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz

I/O Circuit
Package

8-2

VLSI /

8.1

I/O Circuit
Schematic entry Layout
I/O Circuit I/O
IC
[33]IC
m IC mm
Bonding wire Bonding
wire m
IC

8-1 Dual In line Package (DIP)

Die Bonding Pad Bonding
Wire Bonding Finger Lead Frame
Bonding Pad

Die

(Alumina)

Bonding finger

Lead Frame

Alumna base
8-1

DIP

I/O Circuit Package

8-3

8-2 8-1 Die I/O Circuit ( 150 mm * 150mm ) Pad

ESD protection Latch Up

I/O Pad

I/O

8-2

I/O Pad Bonding wire, Lead frame

8-4

VLSI /

8.2

I/O Circuit Pad I/O Pad

I/O Pad

8.2.1

1.

Output PAD

2.

Input PAD

3.

Bidirection PAD

4.

Power Pad ( VDD VSS PAD )

Output PAD
PAD :
1.

Capacitive Loading (
Capacitive Loading pf , Ref[33] )

2.

3.

CMOS TTL
8-1 (CCL)
(TSMC) 0.8m Standard cell
library DC characteristics

4.

Tri-State Output Enable(OE)

Pad Off-Chip

( Pad, Package wire, Off-chip load ) On-Chip

PAD

I/O Circuit Package

8-5

( Inverter chain
Cascaded inverter ) Inverter
Inverter
Inverter Inverter chain
2.7 (

e ) Ref[13,14,33]
8-1

Symbol
VIL

VIH

VT

VOH

VOL

IOZ

CCL TSMC 0.8m DC

Parameter

MIN

TYP

MAX

Voltage in low

Unit
V

TTL

0.8

CMOS

1.5

V
V

Voltage in low
TTL

2.0

CMOS

3.5

Switching Threshold

TTL

1.5

CMOS

2.5

V
V

Voltage in low
TTL

CMOS

Voltage in low

TTL

CMOS

3-State Output Leak-

-10

10

age current

Output Pad (Ref[33]) : 1) TriState, 2) Bidirectional, 3) Low-VDD (3.3V) to high VDD (5V) output buffer, 4) Low swing output buffer
8-3 Tri-State output buffer Schematic, OE=1
Pad in OE=0 Pad
High impedance ( PMOS NMOS Turn off )

8-6

VLSI /

OE
P
Pad
N
in

8-3

8.2.2

Tri-state output buffer

Input PAD
Input Pad
IC

PCB

IC
VLSI 5V
( 3.3V/3V/2.5V )

vinyl ( ) floorsynthetic ( ) carpet

( ) (Relative humidity: RH)
10kV (Ref[33])
(Ref[32])
KW
(ESD, ElectroStatic Discharge) MOS

Ref[13] gate oxide 0.1 m

I/O Circuit Package

8-7

100V , >100V, silicon dioxide BreakdownMOS

ESD
8-4 Input Pad Schematic
R
Diffusion (Ref[33]) Polysilicon (Ref[32])
VDD GND ESD
VDD (Clamping)
GND Clamping

Input Buffer
R
Pad

8-4

8.2.3

ESD Input circuit

Bidirectional PAD
Bidirectional Pad Data Bus Data
Read Write

8-8

VLSI /

PAD PAD
8-5

OE

Pad

in

Buffer

Data in

8-5

8.2.4

Bidirectional Pad

VDD VSS PAD

VDD VSS Pad Power Pad, PAD
(
)
1 I/O PAD ESD 1.5K V
2 I/O PAD Latch up current 200mA

8.3

I/O Circuit Package

8-9

CIC I/O PAD

CIC I/O PAD
CIC PAD library Size
CIW
Design Manager set search path I/O PAD library
path library browser (
~ )

8.3.1

I/O cells

8.3.1.1

power pad
cic_pwr( ) cell core VDD VSS pad

To external ckt.
( I/O Pad
V DD /V SS

Power pad )

8-10

VLSI /

cic_gnd ( ) cell internalcore external circuit

I/O VSS pad
To external ckt.
( I/O Pad
V DD )

To external ckt.
( I/O Pad
V SS )

To internal ckt.

cic_VSS cell external circuit (I/O) VSS pad

To external ckt.

I/O Circuit Package

8-11

cic_VDD cell core external circuitI/O VDD

pad

To external ckt.

To external ckt.

To internal ckt.

8-12

VLSI /

8.3.1.2

I/O pad
cic_in input pad ESD protection

To external ckt.

in

Vss
ESD protection

I/O Circuit Package

8-13

cic_aout input pad driving Output pad

To external ckt.

VDD

out

Vss
ESD protection

8-14

VLSI /

cic_outA cic_outB cic_outC cic_outD

output pad
CIC
output pad

cic_outA

IOH (Vout = 4.5) = 16.5mA

IOL (Vout = 0.18) = -8.6mA

NG

cic_outB

IOH (Vout = 4.5) = 14.5mA

IOL (Vout = 0.18) = -7.5mA

PG

cic_outC

IOH (Vout = 4.5) = 12.5mA

IOL (Vout = 0.18) = -6.5mA

cic_outD

IOH (Vout = 4.5) = 10.5mA

IOL (Vout = 0.18) = -5.5mA

I/O Circuit Package

8-15

cic_biAcic_biBcic_biC cic_biDbi-direction I/O pad

PAD
PAD

cic_biA

IOH (Vout = 4.5) = 16.5mA

IOL (Vout = 0.18) = -8.6mA
NG

PG

cic_biB

IOH (Vout = 4.5) = 14.5mA

IOL (Vout = 0.18) = -7.5mA

in_out

cic_biC

IOH (Vout = 4.5) = 12.5mA

IOL (Vout = 0.18) = -6.5mA

cic_biD

IOH (Vout = 4.5) = 10.5mA

IOL (Vout = 0.18) = -5.5mA

8-16

VLSI /

cic_outA

cic_biA

8.3.1.3

I/O Circuit Package

8-17

cic_corner PAD

Vdd

Vdd

Vss
cic_dummy PAD PAD

Vss

8-18

VLSI /

8.3.2 predriver cells

pre8 cic_outX cic_biX X A
BCD

PG

NG

I/O Circuit Package

8-19

pre8h pre8 cic_outX cic_biX

pre8 w
noise

8-20

VLSI /

8.3.3 input TTL buffer cell

ttlcic_in or cic_aout input buffer

I/O Circuit Package

8-21

I/O PAD input TTL buffer cell

ttl

cic_in

cic_aout

ttl

8-22

VLSI /

I/O PAD predriver cell

external

pre8h

cic_outA

pre8

cic_biA

I/O Circuit Package

8-23

CIC I/O pad

Library cell ( edu ) 28 pindigital circuit pad-ring
input padcic_in cic_aout ttl
celloutput padcic_outA pre8 celltestkey
cell ,

testkey

VSS

vdd
VSS

cic_vdd
cic_in
cic_out
pre8

cic_gnd

ttl
cic_aout

8-24

VLSI /

ttl cell I/O Pad ttl cell

Mask

ttl

cic_in

I/O Circuit Package

8-25

TTL cell I/O Pad pre8 cell

Mask

cic_outA
pre8

8-26

VLSI /

Layout PAD layout

view

mouse

PAD

Edit

Properties PAD cell-name

digital circuit design output buffer output pad

predriver output current driving capability
noise margininput ESD protection
chip TTL high-low level chip CMOS high-low level

analog circuit design edu cell

ttl pre8 cell input output
cic_aout cell ESD protection
analog circuit design output
predriver cellinput TTL cellinput output
cic_aout cell

I/O Circuit Package

cic_vdd

cic_aout
cic_vss

8-27

8-28

VLSI /

8.4

I/O PAD
I/O PAD IC Power
consumptionSignal flow PCB Layout
I/O Pad

1.

Power I/O Pad : VSS

PAD 64mA Current sink I/O Pad
( 8-6)
VSS Pad 2 8 4mA I/O Pad
( 8-7) Layout Current

VSS

16*4mA
16*4mA
VSS

8-6

I/O pad : V SS 64mA ( )

I/O Circuit Package

8-29

8*4mA

VSS
8*4mA
8*4mA

8*4mA

VSS
8-7

2.

I/O pad : V SS 64mA ( )

Clock Pin I/O Pad

Clock Synchronous circuit
8-8 Clock Pin
Output Pin ( High Drive I/O Pin )

Core Circuit

VSS

VSS

CLK
8-8

Clock I/O pad

8-30

VLSI /

Ground Bounce
VSS Clock Pin
Noise margin 8-9 8-9
Clock Pin VSS Pin VSS Pin
Clock Pin Shielding Clock Pin
8-10 Clock Pin
VSS Pin Output Pad
8-10 8-6
I/O Pad
I/O Pad
Trade-Off

Core Circuit
VSS

VSS

VSS
CLK

8-9

Clock I/O pad ( 1 )

I/O Circuit Package

8-31

Core Circuit
VSS

VSS
8*4mA
8-10

3.

CLK

Clock I/O pad ( 2 )

Gate array I/O pad assignment Pin

V DD VSS : 1 )
PCB layout2 ) Pin assignment

4.

Semi-custom

Gate array

Standard cell I/O pad Lead frame I/O

pin I/O pad
8-11 Semi-custom
( Gate Array ) Master chip
Package Master chip Gate count
Package Pin count
Low/High pin count High/Low
gate count IC Low/High gate count
Low/High pin count IC

8-32

VLSI /

Core Circuit

8-11

5.

I/O Pad I/O pin

Pin I/O pad

I/O Pin I/O pad
Ground bounce

6.

I/O pin I/O pad

I/O buffer internal
buffer

7.

Output buffer
Current spike I/O pin
(V=-L di/dt) (Ground
Bounce) I/O buffer
(Slew rate control)
Current spike ( Undershoot/Overshoot )
Switching speed

I/O Circuit Package

8-33

8-12 I/O buffer

Bounce Slew rate control Buffer
Ground Bounce (Ref [33])
5V
INPUT
0V
5V
OUTPU
T

Slew rate control

I/O buffer

I/O buffer
0V

8-12

I/O buffer Slew rate buffer

8-34

VLSI /

8.5

NAND2 I/O PAD layout view

VDD
VDD
B

Output
VSS

VSS
Output

VSS

NAND

VSS

VSS
VSS

I/O Circuit Package

8-35

Layout

cic_in

ttl

cic_in
A

Vdd
B
Output

Vss
cic_outA

pre8

NAND layout

8-36

VLSI /

8.6

(Package)
CIC S/B
DIP (Dual in-Line Package) , CLCC (Ceramic Lead Chip Carrier) , PGA (Pin Grid Array) , CQFP (Ceramic Quad Flat Pack)
28 Pin LD S/B
CIC PGA

1.

8-1318 LD S/B (DIP)

2.

8-1424 LD S/B

3.

8-1528 LD S/B

4.

8-1632 LD S/B

5.

8-1740 LD S/B

6.

8-1868 LD PGA

7.

8-1968 LD CLCC

8.

8-2080 LD CQFP

9.

8-2184 LD PGA

10.

8-2284 LD CLCC

11.

8-23100 LD CQFP

12.

8-24120 LD CQFP

13.

8-25144 LD CQFP

14.

8-26160 LD CQFP

15.

8-27208 LD CQFP

16.

128 CQFP ( )

17.

256 CQFP ( )

I/O Circuit Package

Package Type: 18LD S/B

Die Cavity: 7360 * 3680 m2

8-13

18 LD S/B (DIP)

8-37

8-38

VLSI /

8-14

24 LD S/B

8-15

28 LD S/B

I/O Circuit Package

8-39

8-40

VLSI /

8-16

32 LD S/B

8-17

40 LD S/B

I/O Circuit Package

8-41

8-42

VLSI /

8-18

68 LD PGA

8-19

I/O Circuit Package

68 LD CLCC

8-43

8-44

VLSI /

8-20

80 LD CQFP

8-21

84 LD PGA

I/O Circuit Package

8-45

8-46

VLSI /

8-22

84 LD CLCC

8-23

I/O Circuit Package

100 LD CQFP

8-47

8-48

VLSI /

8-24

120 LD CQFP

8-25

I/O Circuit Package

144 LD CQFP

8-49

8-50

VLSI /

8-26

160 LD CQFP

8-27

I/O Circuit Package

208 LD CQFP

8-51

8-52

VLSI /