REGISTRATION FORM Call for Participation

National Workshop
On

VLSI DESIGN TOOLS

28 February-1st March, 2009 Electronics Engineering Department SVNIT, Surat
1. Name

National Workshop
On

VLSI DESIGN TOOLS

28 February-1st March, 2009 Under Special Manpower Development Programme (SMDP-II) Sponsored by Ministry of Communication & Information Technology Coordinator Mr. J. N. Sarvaiya Co-coordinators Mr. Anand Darji Ms. Rasika Dhavse
A

Dr / Mr / Ms 2. Qualification 3. Designation 4. Department 5. Experience in VLSI Field 6. Institutional Address

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7. E-mail Address 8. Mobile No. 9. Accommodation required

:YES / NO : _________________________ _________________________ _________________________ : _________________________ : _________________________ : YES / NO

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TI TUT E O F
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N S . V. AT IO

NO LO G Y

I hereby enclose DD no. , dated , of Rs.500/- drawn in favor of Director, SVNIT, Surat, payable at State Bank of India, Surat. Place: Date:

S U R AT

Signature

Name and Signature of Head of the Department with SEAL

ELECTRONICS ENGINEERING DEPARTMENT S. V. NATIONAL INSTITUTE OF TECHNOLOGY Ichchhanath, Surat-395 007, GUJARAT Phone: 0261- 2201551 & 2201552 Website: http://www.svnit.ac.in

ABOUT THE INSTITUTE Sardar Vallabhbhai National Institute of Technology (SVNIT), Surat is one of the twenty National Institutes of Technology in India set up with the objective to provide high quality technical education to meet the needs of the Nation in the present competitive world. At present, the Institute is offering 7 UG and 15 PG programmes in various disciplines of Technology as well as three 5 Year Integrated M. Sc. programmes. The Institute also offers Ph.D. programmes in all disciplines of engineering and applied sciences. SVNIT, Surat is located on the Mumbai-Delhi (NH- 8) and is connected to the rest of the country by rail. It is in the outskirts of Surat city in an area known as Ichchhanath, at a distance of about 10 kms from the Surat Railway Station. ABOUT THE DEPARTMENT The Electronics Engineering Department was started in 1982 and received its independent status in 1988. The Department is offering M.Tech. (Communication Systems), M. Tech. (Research) and Ph.D. programmes. The Department has received a 5 years project from Ministry of Communication and Information Technology, Govt. of India on Special Manpower Development Program for VLSI Design and Related Software (SMDP II). The main objective of this program is to train special manpower in the field of VLSI through the establishment of VLSI design laboratories. VLSI Design laboratory is equipped with latest chip design suits like Xilinx, Synopsys, Cadence, Mentor Graphics, Co-Ware, Microwind, SPICE and MAGIC. For more details about VLSI Design laboratory, please visit Url: http:// www.svnit.ac.in/VLSI ABOUT THE WORKSHOP The workshop is intended for faculty members and PG students to enhance their skills of transforming design concepts to chip through various free and commercial VLSI Design software tools. The workshop covers following topics IC Design Flow Free CAD Tools like SPICE, MAGIC RTL to GDS Flow with Cadence and Synopsys Hardware Description Language (HDL) Xilinx ISE, ModelSIM, Embedded Design Kit (EDK) Demonstrations of VLSI design tools and Practical Sessions ELIGIBILITY Faculty members and PG students from AICTE approved institutions aspiring to work in the field of VLSI design, are eligible to participate.

PATRON Dr. P. D. Porey, Director, SVNIT, Surat ADVISORY COMMITTEE Prof. B. R. Taunk, Head, ECED Prof. (Mrs.) N. Y. Desai, Coordinator, SMDP-II Dr. A.N. Chandorkar, IIT Bombay Mr. Anand Darji, Co-coordinator, SMDP-II Mr. Z. M. Patel Mr. P. J. Engineer ACCOMMODATION

ORGANIZING COMMITTEE Dr . Suprava Patnaik Mr. A. H. Lalluwadia Ms. U. D. Dalal Mr. N. B. Kanirkar Mr. P. N. Patel Ms. Shilpi Gupta Mr. Abhilash Mandloi Ms. J. N. Patel Mr. Golak Santra

The accommodation will be provided in the staff quarters/hostels to the outstation participants, if request is made well in advance. REGISTRATION The registration fees is Rs. 500/- for all participants. The registration fees is to be paid through a Demand Draft drawn in favor of Director, SVNIT, Surat, payable at SBI, Surat. The Registration Fees should reach the coordinator on or before 15th February, 2009 with the attached registration form. NO TA/DA WILL BE PAID TO THE PARTICIPANTS BY SVNIT, SURAT.
* LAST DATE OF RECEIVING REGISTRATION FORM : 15 February, 2009 * NOTIFICATION OF CONFIRMATION (Through e-mail): 17th February, 2009
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CONTACT PERSONS Mr. J. N. Sarvaiya : 0261-2201734 Ms. Rasika Dhavse : 0261-2201737 Filled Registration Form is to be sent to: The Coordinator, National workshop on VLSI Design tools, Electronics Engineering Department, S.V. National Institute of Technology, Ichchhanath, Surat-395 007. Gujarat, India Registration through E-mail is acceptable at vlsi09@eced.svnit.ac.in