MANIPAL INSTITUTE OF TECHNOLOGY

(A constituent college of Manipal University, Manipal)

Manipal Karnataka 576 104

DEPARTMENT OF COMPUTER SCIENCE AND ENGG.

COURSE PLAN Department Subject Semester & branch Name of the faculty No of contact hours/week : CSE : SWITCHING THEORY & LOGIC DESIGN (CSE-205) : III SEM (CSE) : Hemalatha S : 4 Hrs Assignment portion Assignment no. 1 2 3 Test no. 1 2 Submitted by: Hemalatha s Topics LECTURE N0. 1 TO 14 LECTURE NO. 15 TO 29 LECTURE NO. 30 TO 42 Test portion Topics LECTURE N0. 1 TO 20 LECTURE NO. 21 TO 42

(Signature of the faculty) Date: Approved by:

(Signature of HOD) Date:

MIT/GEN/F-05/RO

Lecture no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

Topic to be covered Introduction, Variables and Functions, Inversion, Truth Tables Logic Gates and Networks, Boolean Algebra Introduction to VHDL, introduction to MaxPLUS II design software, Writing simple VHDL code Examples on boolean algebra and VHDL code(T) Synthesis using AND, OR and NOT logic gates Minterms, SOP, maxterms, POS, Examples on SOP and POS Karnaugh Maps, Two-variable map, Three-variable map Four-variable map, Five-variable map, Examples(T) Strategy for Minimization - terminology Minimization procedure Minimization of Product-of-Sum forms Incompletely specified functions, Multiple output circuits(T) NAND and NOR Logic networks, Multilevel NAND and NOR circuits, Functional Decomposition Analysis of Multilevel circuits, Introduction to structural style of programming in VHDL- usage of components Positional Number Representation Addition of unsigned numbers, decomposed Full-Adder(T) Ripple-carry adder, Design example Signed numbers, negative numbers, addition and subtraction Adder and subtractor unit, Radix-complement schemes, arithmetic overflow, performance issues(T) Design of arithmetic circuits using VHDL Fast adders Carry Lookahead Adder

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Technology Considerartions Representation of numbers in VHDL code, Arithmetic assignment statements. BCD representation(T) Multiplexers, Synthesis of logic functions using muxs VHDL code for mux and circuits using muxs Mux synthesis using Shannons expansion Decoder, Encoder, circuits using decoders(T) VHDL code for decoders, encoders and circuits using decoders Code converters Arithmetic comparison circuits VHDL code for code converter and comparators, More examples (T) Flip-Flops Triggering of Flip-Flop Analysis of clocked sequential circuits(T) State reduction and Assignment Flip-Flop excitation tables Design procedure Design procedure (Contd.) Design of counters, Examples(T) Registers Shift registers FFs and Registers in VHDL code usage of sequential statements

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Ripple Counters(T) Synchronous counters Counters in VHDL code Overview of semiconductor diode, BJT, MOSFET, TTL-standards High speed, low-power schotky, CMOS logic-NAND, NOR(T)

MIT/GEN/F-05/RO