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P.MANJUNATH REDDY S/o Chandrasekhar Reddy, H.no. 1-40, Kurugunta (P) (V), Anantapur (M) (D), A.P.515001.

Email: p.manjunathreddy007@gmail.com Contact No: 9177776126 ASPIRING ELECTRONICS ENGINEER Seeking a position in Electronics or VLSI Designing with a growth oriented organization across the industry. PROFILE

Trained at P.G Diploma in VLSI from DOEACC Center, Calicut. Highly dependable, adaptive, confident individual with analytical bent of mind can surely contribute to growth of an organization. Result oriented professional with strong analytical and interpersonal skills and a quick learner with high levels of adaptability and ability to take initiative. Good communication skills, verbal as well as written coupled with exceptional presentation skills. An effective team player with exceptional planning and execution skills coupled with a systematic approach and quick adaptability. Work Experience Company Duration Designation : : : NV Logic Technologies Pvt. Ltd. April 2011 to till date. Project Trainee.

COMPLITED PROJECT VERIFICATION OF UART: Developed Model for UART and the stimuli was driven through Bus Functional Model (BFM) to the parallel input ports of the UART. The serial output port of UART is connected to serial input port of model and vice-versa. The parallel input and output ports of the model are connected to the memory block. Verification of UART RTL design was done by task-based test bench using Verilog HDL. The read and write operations of memory block are performed through the UART and the RTL design has been verified. Tool used HDL used : Modelsim : Verilog

CURRENT PROJECT: IMAGE ROTATION Client Role Tools Description : Pioneer Embedded Technologies Pvt Ltd.. : Verification Engineer. : Quartus7.2, MODELSIM ALTERA 6.5e, Cadence NC. : In This module read Avalon master reads image from external memory and write into internal RAM's.write Avalon master reads the stored data and write into another memory through Avalon protocol .finally the read image is flipped and rotated .

PROJECT UNDER TAKEN DURING P.G.DIPLOMA. Title Technology Description FPGA IMPLEMENTATION of Encryption Algorithm using VHDL VHDL, Xilinx 9.2i ISE tool & Spartan-3E FPGA board is Used Encryption Algorithm targeted for small embedded applications. It was initially designed for software implementations in controllers, smart cards, or processors. In this letter, we investigate its performances in recent field programmable gate array (FPGA) devices

TECHNICAL SKILLS Programming Languages Simulation Tools Hardware Exposure Operating System C, Verilog, VHDL. Modelsim, Xilinx ise. FPGA Spartan 3E, Microprocessor 8085. Linex,Windows.

ACADEMIC CREDENTIALS B.Tech. Electronics & Communication 2010 Vivekananda Institute of Engineering & Technology, J.N.T.U, Hyderabad, (A.P); 54.6%. Class XII (I.P.E) 2006 Nalanda Jr College (A.P); 67.00%. Class X 2001 Little Flower High School (A. P); 73.00%.

PERSONAL DETAILS Date of Birth: Aug 13th, 1986 Hobbies: Playing Cricket, Listening to music. Declaration I am confident of my ability to work in a team. I hereby declare that the above information and particulars are true to the best of my knowledge and belief. Place: Date: (P.MANJUNATH REDDY)