VHDL-BASED DIGITAL CIRCUIT SYNTHESIS: A CASE STUDY

Fsibio Luiz Viana, Furio Damiani Department of Semiconductors,Instruments and Photonics Faculty of Electrical and Computing Engineering University of Campinas AV.Albert Einstein, 400, 13081-970 Campinas, SP, Brazil { FabioV, Furio) @dsif.fee.unicamp.br
Abstract - Present day computer-aided design of VLSI circuits calls for specifying the design at a sufficiently high level of abstraction. This approach allows the designers to describe systems in terms of a set of interacting components, which facilitates the reuse of subsystems in a complex design and reduces the design cycle. This paper describes a case study of the Description-and-Synthesis methodology for digital circuit design. Distinct digital addition algorithms were coded in VHDL and automatically synthesized using two different commercial Electronic Design Automation (EDA) environments. The resulting circuits were simulated and the overall results are shown and discussed.

I. INTRODUCTION Todays highly competitive electronics market and increasing complexity ICs, due to manufacture technology evolution, fostered a high degree of automation in the design methodologies, using computer-aided design tools in EDA environments [6]. The combined forces of shrinking design cycles and ever-more-complex circuits have favored the use of higher levels of abstraction, with hardware description languages (HDLs) [ 1,7] and methods for automatic generation (synthesis) of circuits [3,6]. Digital circuit design methodologies are transformation sequences applied to circuit specification (and/or description). Their purpose is to generate validated descriptions, eventually used for the manufacture process [5,6,7,17]. There are two approaches to design: top-down and bottom-up. In top-down design, transformation sequences start from a higher level of abstraction to arrive to a lower one. In bottom-up design, transformation sequences start from a lower level of abstraction to arrive to a higher one. Usually, circuit design uses a combination of both. Top-down approach is used initially, refining the starting circuit description to a detailed level, where the primitive circuit components (cells) for the physical circuit implementation are known. The cells are retrieved from an existing library. These cells were designed with a bottom-up approach.

Until recently, digital circuit designs used the Capture-and-simulation methodology, that starts from an initial specification, involving a group of requirements. An initial block diagram is generated, containing functional structures, that are refined to a logical circuit. This logical circuit is captured by schematic capture tools for functionality verification of timing and fault occurrence 171. Due to circuit complexity increase and new circuit manufacture technologies, the Description-and-synthesis methodology is having better acceptance than the Capture-and-simulation [6]. This methodology reduces development time, allowing the manipulation of more complex structures and portability. The designer works with the high level solution of the problem, without the need of IC manufacture technology details knowledge ~71. 11. DESIGN SPECIFICATION AND SYNTHESIS Digital circuit design can be classified in three domains: structural, physical and behavioral [3,6,7]. Each domain can be further divided in abstraction levels: architecture, RTL (Register Transfer Level), logical and device. Each abstraction level in the structural domain is characterized by the primitive elements used for circuit representation. In the physical domain by the geometric cells. And in the behavioral domain by the formalisms used in functional representation [3,6]. In architecture level descriptions, large circuits can be set up without the need to specify details of the underlying hardware. In RTL level, basic digital circuit components are described in operational mode. In logical level, logical gate interconnections represent the circuit. And in device level, circuit behavior is described with the maximum of details. Fig. 1 shows a diagram with the primitive elements for each abstraction level in each domain. The diagram also depicts the transformations involved in logic synthesis. The synthesis is an automatic process. It uses algorithms that execute transformations between digital circuit specification levels, arriving at a physical implementation of the circuit. Each transformation introduces structural or geometric details, maintaining the circuit functionality [3,5,7,14].

0-7803-5766-3/00/!%1 b m n n n nn

IFFF

. .+. .
Physical Domain

Fig. 1. Digital circuit design representation. The first commercial synthesis tools worked at the lowest abstraction level. Eventually, they have incorporated logical level tools, both structural and behavioral, thus reaching higher abstraction levels. This interest is justified for the following reasons [4,7]: Shorter design cycle, due to design automation. As most of circuit cost is associated to the development phase, automation reduces costs. Fewer errors, through the use of simulation or internal verification rules. Exploration of design alternatives. The synthesis process allows variations in the design, maintaining specifications. The designer can investigate parameters as speed, area, energy consumption. Design process documentation. Being automated, the synthesis tool stores information on changes in the initial descriptions and the ensuing results. Evolution of the IC technologies. Technology evolution has pushed the synthesis tools development. In logic synthesis, functional units can be described by Boolean equations and then synthesized in two phases. In the first phase, called logic minimization, the number of and, or and other operators in the Boolean equations are factored (minimized) to satisfy time and cost constraints. In the second phase, called technology mapping, these minimized Boolean equations are implemented (mapped) using the logic gates from the given gate library in a selected technology [2,7,14]. The control units (sequential logic) can be defined by finite state machines (FSM)and synthesized in two phases. In the first phase, called state minimization, the number of states is minimized and a binary encoding is attributed to each state. In the second phase, the equations obtained are submitted to the logic minimization and the technology mapping [7,14]. In high-level synthesis (HLS), the complex circuit behavioral description is transformed to a structural

representation by the application of allocation, scheduling and binding procediures [3,5,6,7]. The allocation procedure determines the number of components and resources, at ithe register level, that will be used in the implementation. Specifically, it executes the following functions: It determines the number of functional units, the operations executed by each unit, the number of pipeline stages, the operation delays, as well as the size of each unit. It determines the number of storage units (for example, registers and memories), the read and write access time for each unit, as well as their size. It determines the number, size, protocol and delay for each system bus, as well as the connection options of the functional and storage units. The scheduling procedure partitions and orders the behavioral descriptions in time intervals, or control steps. During each step, usuallly a clock cycle, data are transferred from a register to another and, if necessary, transformed by functional units during the transfer. The scheduling procedure determines all the ope-rations that must be executed at each control step. The binding procedure assigns variables to storage units and operations to functional units, as well as it specifies the intercommunication busses. 111. VHDL MODELING AND SYNTHESIS The choice of an HDL involves the analysis of its characteristics: the hardware platform independence, the schematic capture tools integration, the simulation, the logical synthesis, the models diversity, the standardization and the accessible cost [13. The VHDL language is a standard in the integrated circuits modeling area, being supported by different hardware platforms for the compilation, debugging, synthesis and simulation [9,10,13]. A digital circuit can be modeled in VHDL in three description styles: structural, data-flow and behavioral [ 12,13,17]. Structural descriptions present a larger detail, and are hierarchical arrangements of components and their interconnections. In the data-flow descriptions, the digital circuit control and data flows are represented. The relationship between the input and the output is determined by instructions and concurrent signal assignments. Behavioral descriptions have less detail. They are used for digital circuit verification and functional simulation of its operations. Output to input relationship is usually specified by VHDL, processes. In the case of synthesis, it is not easy to identify which VHDL description style will give better results. Although not optimized, structural models already have circuit form. This form reduces optimization tools efficiency. Behavioral models are more flexible, however undesirable hard ware structures can be

generated, depending on the commands used and of their position in the description [17]. The tools to synthesize VHDL descriptions perform optimizations seeking for area andor timing goals. Area optimization minimizes IC area. Timing optimization seeks to fulfill operation frequency specifications [11,13,15]. Thus, it is necessary to set design constraints for synthesis tools. They set the optimization goals for a chosen manufacture technology. The constraints set the minimum and maximum bounds or acceptable value ranges. An example is minimum and maximum delay time for the signals. IV. ADDER CIRCUITS VHDL IMPLEMENTATION AND SYNTHESIS - A CASE The knowledge of cost and delay functions of the fundamental building blocks enables designers to optimize costs and propagation delays of the larger units built from them, A fundamental building block of an arithmetic logic unit (ALU) is the binary adder. Therefore, the Dwcriptian-and-synthesis methodology was applied in the implementation of fixedpoint adders. Some VHDL description styles for addition algorithms were modeled. These descriptions were synthesized, with area optimization, using the same constraints, in two commercial EDA environments. Considering a possible design space exploration, ripple-carry and carry-lookahead adders were modeled in VHDL. The 8 bit fixed point arithmetic sum was performed using two complement representation of the arguments [8,16]. the two EDA environments, both In architecture types can be found as macrocells, stored in a cell library. These macrocells were used for comparison purposes. Ripple-carry adders are structures composed by full adders. The quantity of full adders is dependent on the number of bits used. Ripple-carry adders perform addition by summing the nth order bit of the arguments, generating a partial sum result and a carry. The cany is summed together with the (n+Z)th order bit of the arguments. This process is repeated until the addition of Ripple-carry adders all the bits is completed [8,16,17]. modeled were [ 1 1 7: H rcl model: 8 bit ripple-carry adder with behavioral description. rc2 model: 8 bit ripple-carry adder with structural description. Data-flow description of full adders. rc3 model: 8 bit ripple-carry adder with structural description. Structural description of full adders. Carry-lookahead adders accelerate the addition operation using the carry properties. Complementary

logic structures are implemented to eliminate the interdependence between carry signals and their occurrence order. These structures produce the propagate and generate signals [8,16,17]. Carrylookahead adders modeled were [ 1 1 7: la1 model: 8 bit carry-lookahead adder with structural description. Unit-lookahead-adders instantiations (4 bit carry-lookahead adders). la2 model: 8 bit carry-lookahead adder with structural description. Unit-lookahead-adderss instantiations (4 bit cany-lookahead adders, that manipulate the group propagation and group generation additional signals). The synthesis results were compared using area and timing reports. Validation and performance were evaluated using simulations, with timing information from the manufacture technology. The design followed the sequence below: The adder circuits were described in VHDL, using standard package [9]; the IEEE-1164 The VHDL descriptions were compiled and simulated to verify the functionality (validation); The VHDL compiled descriptions were synthesized at the gate-level, using an independent technology (generic); These representations were optimized for area and mapped to the logical gates library of a manufacture technology (AMs CMOS 1 2pm); . Simulation of the optimized circuits was used to verify their performance and functionality. Area optimization does redundant logic elimination, thus reducing the number of gates used. This step maps the circuit in the manufacture technology, using its specific macrocell library. The macrocell library is supplied by the manufacturing foundry and contains cells with optimized layout [11,13,15]. Area reports supply information on used cells. It also gives an area estimate. The area unit in our case was mils2 (1 mil = 25,4 pm). Timing reports give circuit delay times in function of a clock (virtual or specific). The synthesis tools perform static timing analysis [11,13,15]. output The signal determination depends on the input signal time delay and on the time delays of the gates in the critical path. All synthesis were carried with the same optimization constraints. For area constraints, no restrictions were made. Thus, area optimizations were executed in different effort levels: low, medium and high. The effort level is the demand optimization degree of the circuit area reduction.

V. RESULTS

Values obtained from the area and timing reports are st"arized in Table 1 and Table 2. The values are normalized in function of the smallest Value obtained for each implementation. Fig. 2 and Fig. 4 show the schematics for the rcl model and macrocell synthesis, respectively. Fig. 3 and

Fig. 5 show the simulation waveforms for the rcl model and macrocell models. Table 3 shows the output stabilization time values. Input changes every 20 ns, and the pattern sequence (pa(7:O) and pb(7:0) values), s]nownin Fig. 3 and Fig. 5 , are the same for all models.

Imdementation

Effort level
low medium, high low, medium, high low, medium, high low, medium, high
~~~ ~~ ~

VendorA

Vend,orB

rcl model rc2 model rc3 model la1 model la2 model macrocell

101 100 100 100

100
~~ ~ ~~

158
156

173

low medium, high low, medium, high

105
100

100

::q
159

177

133

rcl model

79 (met) 107 (violated)

66 (met:)

rc3 model la1 model la2 model macrocell

low. medium. hieh

low, medium, high

low
~ ~ ~ ~~

medium, high low, medium, high

115 (violated)

101 (violated)

94 (met)

80 (met)

Table 2: Timing values. Values are normalized in function of the required time for all implementations. Met means that the output correct values generation happened before required time. Violated means that in certain situations, depending to the input signal values, the output correct values generation cannot happen before required time. Required time for all models was 15 ns = 100 %.

".

Fig. 2. Synthesized rclmodel schematic.

OlOlOfl +XlIllM11
.+

x10101010

54.00

x1w00000+

Xillllllf

+X101011fll

xooowooo

0.00
~ ~~

18.00

36.00

72.00
TimehS)

90.00

108.00

126.00

144

Fig. 3. Synthesized rcl model simulation waveforms.

Fig. 4. Synthesized macrocell schematic.

/pa (7 : 0)

/& (7: 01
ISLnnR :01
I

0.00

18.00

36.00

54.00

72.00
TimehS)

90.00

108.00

126.00

Fig. 5. Synthesized macrocell simulation waveforms.

Table 3: Output stabilization times. As can be seen in Fig. 3 and Fig. 5, for each 20 ns period the adder operands change and so the output stabilization time varies.

VI. CONCLUSIONS In this paper, the basic notions of the methodology and of the automated synthesis process involved were discussed. The Description-and-synthesis methodology has many advantages: it is efficient, it allows an initial validation of the design and it grants the exploration of design alternatives. The synthesis results were reported and their analysis show that for a given implementation and manufacture technology, area and timing differences were always observed, depending on the synthesis software used. The difference is due to the mapping tool of the synthesis software. It can be seen that the vendor B synthesis algorithms are tuned to timing optimization, whereas vendor A synthesis algorithms are tuned to area optimization. Designs synthesized with vendor B software showed about 50% area increase. Because of the aforementioned algorithms tuning, the vendor B designs showed about 15% static timing improvement. The adder circuit design synthesis, performed on the different VHDL descriptions, provides decision parameters for complex designs. That will allow to evaluate the quality of the proposed specification and guide the synthesis towards optimal circuits. These parameters are the circuit description abstraction level, synthesis and simulation tools efficiency, and design cycle time. Finally, Description-and-synthesis methodology ensues the design reuse, through the establishment of components library and facilitates the design migration between different implementation technologies, without the need for a complete change of design steps.

* This work was supported by grants from Brazilian agency CNPq.

REFERENCES
BRAGE, Jens P. Language Models for Design f Automation, Technical report, Department o Computer Science, Technical University o f Denmark, July 1993. BRAYTON, Robert K., HACHTEL, Gary D., SANGIOVANNI-VINCENTELLI, Albert0 Mulf tilevel Logic Synthesis, Proceedings o the IEEE, v.78, n.2, p.264-300, February 1990. CAMPOSANO, Raul High-Level Synthesis. In: I1 Brazilian Microeletronics School, p.93- 128, Gramado-RS, Brazil, March 1992. CAMPOSANO, Raul, ROSENSTIEL, Wolfgang Synthesizing Circuits From Behavioral

Descriptions, IEEE Transactions on ComputerAided Design, v.8, n.2, p.171-180, February 1989. [5] EDWARDS, Stephen, et al. Design of Embedded Systems: Formal Models, Validation, and Synthesis, Proceedings of the IEEE, v.85, n.3, p.366-390, March 1997. [6] GAJSKI, Daniel D., et al. System Design Methodologies: Aiming at the lOOh Design Cycle, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.4, n.1, p.70-82, March 1996. [7] GAJSKI, Daniel D., VAIIID, Frank, NARAYAN, f Sanjiv, GONG, Jie Specification and Design o Embedded Systems, Prentice Hall Inc., 1994. 181 HWANG, Kai Computer Arithmetic: Principles, Architecture, and Design.,John Wiley & Sons Inc., 1979. [9] IEEE Standard Multivalue Logic System for VHDL Model Interoperability. IEEE Standard 1164-1993. The Institute o Electrical and Elecf tronics Engineers Inc., 1993. [lo] IEEE Standard VHDL Language Reference Manual, IEEE Standard 1076-1987. The Institute o f Electrical and Electronks Engineers Inc., 1987. [ 111 MENTOR GRAPHICS CORPORATION. Introduction to Autologic and Design Synthesis. Mentor Graphics Corporation, 1994. [12] NAGASAMY, V., BER.RY, N., DANGELO, C. Specification, Planning and Synthesis, IEEE Design & Test o Computers, v.9, n.2, p.58-68, f June 1992. [ 131 PERRY, Douglas L. VHIIL, 2nd ed., McGraw-Hill Inc., 1994. [I41 RUDELL, Richard Tutorial: Design of a Logic f Synthesis System, In: Proceedings o 33rd Design Automation Conference, Las Vegas, Nevada, USA, June 1996. [15] SYNOPSYS INC. CHIP Synthesis and Simulation. Synopsys Inc., 19961. [ 161 TAUB, Herbert Digital Circuits and Microprocessors, McGraw-Hill Inc., 1982. [17] VIANA, Fi5bio L. A Study on the ArithmeticDigital Circuit Design Using VHDL Description Synthesis. Master Thesis - Faculty of Electrical and Computing Engineering, University of Campinas, 1997 (in Portuguese).