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Am29F800B
8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s Single power supply operation 5.0 Volt-only operation for read, erase, and program operations Minimizes system level requirements s Manufactured on 0.35 m process technology Compatible with 0.5 m Am29F800 device s High performance Access times as fast as 55 ns s Low power consumption (typical values at 5 MHz) 1 A standby mode current 20 mA read current (byte mode) 28 mA read current (word mode) 30 mA program/erase current s Flexible sector architecture One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbyte sectors (byte mode) One 8 Kword, two 4 Kword, one 16 Kword, and fifteen 32 Kword sectors (word mode) Supports full chip erase Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors s Top or bottom boot block configurations available s Embedded Algorithms Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors Embedded Program algorithm automatically writes and verifies data at specified addresses s Minimum 1,000,000 program/erase cycles per sector guaranteed s Package option 48-pin TSOP 44-pin SO s Compatibility with JEDEC standards Pinout and software compatible with singlepower-supply Flash Superior inadvertent write protection s Data# Polling and toggle bits Provides a software method of detecting program or erase operation completion s Ready/Busy# pin (RY/BY#) Provides a hardware method of detecting program or erase cycle completion s Erase Suspend/Erase Resume Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation s Hardware reset pin (RESET#) Hardware method to reset the device to reading array data
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29F800B is an 8 Mbit, 5.0 volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 44-pin SO and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15DQ0; the byte-wide (x8) data appears on DQ7 DQ0. This device is designed to be programmed insystem with the standard system 5.0 volt VCC supply. A 12.0 V VPP is not required for write or erase operations. The device can also be programmed in standard EPROM programmers. This device is manufactured using AMDs 0.35 m process technology, and offers all the features and benefits of the Am29F800, which was manufactured using 0.5 m process technology. The standard device offers access times of 55, 70, 90, 120, and 150 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithman internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithman internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. AMDs Flash technology combines years of Flash memory manufacturing experience to produce the h i g h e s t l eve l s o f q u a l i t y, r e l i a b i l i t y a n d c o s t effectiveness. The device electrically erases all bits within a sector simultaneously via F o w l e r -N o r d h e i m t u n n e l i n g . T h e d a t a i s programmed using hot electron injection.
Am29F800B
P R E L I M I N A R Y
BLOCK DIAGRAM
RY/BY# VCC VSS RESET# Erase Voltage Generator Input/Output Buffers Sector Switches DQ0DQ15 (A-1)
WE# BYTE#
PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE# OE#
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0A18
21504C-1
Am29F800B
P R E L I M I N A R Y
CONNECTION DIAGRAMS
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48-Pin TSOPStandard Pinout
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48-Pin TSOPReverse Pinout
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1
21504C-2
Am29F800B
P R E L I M I N A R Y
CONNECTION DIAGRAMS
SO
RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE# VSS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 RESET# WE# A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC
21504C-3
PIN CONFIGURATION
A0A18 = 19 addresses DQ0DQ14 = 15 data inputs/outputs DQ15/A-1 BYTE# CE# OE# WE# RESET# RY/BY# VCC = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) = Selects 8-bit or 16-bit mode = Chip enable = Output enable = Write enable = Hardware reset pin, active low = Ready/Busy# output = +5.0 V single power supply (see Product Selector Guide for device speed ratings and voltage supply tolerances) = Device ground = Pin not connected internally
LOGIC SYMBOL
19 A0A18 DQ0DQ15 (A-1) CE# OE# WE# RESET# BYTE# RY/BY# 16 or 8
21504C-4
VSS NC
Am29F800B
P R E L I M I N A R Y
Am29F800B
-70
OPTIONAL PROCESSING Blank = Standard Processing B = Burn-in (Contact an AMD representative for more information) TEMPERATURE RANGE C = Commercial (0C to +70C) I = Industrial (40C to +85C) E = Extended (55C to +125C) PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) F = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048) S = 44-Pin Small Outline Package (SO 044) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top Sector B = Bottom Sector
DEVICE NUMBER/DESCRIPTION Am29F800B 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory 5.0 Volt-only Read, Program, and Erase
Valid Combinations Valid Combinations Am29F800BT-55, Am29F800BB-55 Am29F800BT-70, Am29F800BB-70 Am29F800BT-90, Am29F800BB-90 Am29F800BT-120, Am29F800BB-120 Am29F800BT-150, Am29F800BB-150 EC, EI, EE, FC, FI, FE, SC, SI, SE EC, EI, FC, FI, SC, SI Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Am29F800B
P R E L I M I N A R Y
Table 1.
Operation Read Write CMOS Standby TTL Standby Output Disable Hardware Reset Temporary Sector Unprotect (See Note)
OE# L H X X H X X
WE# H L X X H X X
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 0.5 V, X = Dont Care, DIN = Data In, DOUT = Data Out, AIN = Address In Note: See the sections on Sector Protection and Temporary Sector Unprotect for more information.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins DQ15DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic 1, the device is in word configuration, DQ15DQ0 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
sert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See Reading Array Data for more information. Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the timing waveforms. ICC1 in the DC Characteristics table represents the active current specification for reading array data.
Am29F800B
P R E L I M I N A R Y After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. In the DC Characteristics tables, ICC3 represents the standby current specification.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when CE# and RESET# pins are both held at VCC 0.5 V. (Note that this is a more restricted voltage range than VIH.) The device enters the TTL standby mode when CE# and RESET# pins are both held at VIH. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section, RESET#: Hardware Reset Pin. If the device is deselected during erasure or programming, the device draws active current until the operation is completed.
Am29F800B
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18
A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1
A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1
A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1
A14 X X X X X X X X X X X X X X X 0 1 1 1
A13 X X X X X X X X X X X X X X X X 0 0 1
A12 X X X X X X X X X X X X X X X X 0 1 X
Note: Address range is A18:A-1 in byte mode and A18:A0 in word mode. See Word/Byte Configuration section for more information.
Am29F800B
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18
A18 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A17 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A16 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A15 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A14 0 0 0 1 X X X X X X X X X X X X X X X
A13 0 1 1 X X X X X X X X X X X X X X X X
A12 X 0 1 X X X X X X X X X X X X X X X X
Note: Address range is A18:A-1 in byte mode and A18:A0 in word mode. See Word/Byte Configuration section for more information.
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are dont care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require VID. See Command Definitions for details on using the autoselect mode.
10
Am29F800B
Description
Mode
CE# L
OE# L L
WE# H H
A9 VID
A6 L
A1 L
A0 L
Manufacturer ID: AMD Device ID: Am29F800B (Top Boot Block) Device ID: Am29F800B (Bottom Boot Block) Word
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Dont care.
Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (VID) on address pin A9 and the control pins. Details on this method are provided in a supplement, publication number 20374. Contact an AMD representative to obtain a copy of the appropriate document. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMDs ExpressFlash Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode for details.
START
RESET# = VIH
21504C-5
Notes: 1. All protected sectors unprotected. 2. All previously protected sectors are protected once again.
Figure 1.
Am29F800B
11
P R E L I M I N A R Y
proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse Glitch Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the AC Characteristics section. ters, and Read Operation Timings diagram shows the timing diagram.
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are dont care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).
Am29F800B
P R E L I M I N A R Y
the operation and set DQ5 to 1, or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still 0. Only erase operations can convert a 0 to a 1.
START
Verify Data?
No
Yes No
Increment Address
Last Address?
Note: See the appropriate Command Definitions table for program command sequence.
Figure 2.
Program Operation
Am29F800B
P R E L I M I N A R Y reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See Write Operation Status for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 3 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in AC Characteristics for parameters, and to the Chip/Sector Erase Operation Timings for timing waveforms. are ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to Write Operation Status for information on these status bits. Figure 3 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the AC Characteristics section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms.
Am29F800B
P R E L I M I N A R Y The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence for more information. The system must write the Erase Resume command (address bits are dont care) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing.
No
START
Data = FFh?
1. See the appropriate Command Definitions table for erase command sequence. 2. See DQ3: Sector Erase Timer for more information.
Figure 3.
Erase Operation
Am29F800B
15
P R E L I M I N A R Y Table 5.
Command Sequence (Note 1) Read (Note 6) Reset (Note 7) Manufacturer ID Word Byte Word Byte Word Byte Word Sector Protect Verify (Note 9) Byte Program Chip Erase Sector Erase Erase Suspend (Note 10) Erase Resume (Note 11) Word Byte Word Byte Word Byte 4 6 6 1 1 4 AAA 555 AAA 555 AAA 555 AAA XXX XXX AA AA AA B0 30
Cycles
First Addr RA XXX 555 AAA 555 AAA 555 AAA 555 Data
Third Addr
1 1 4 4 4
01 22D6 D6 2258 58 XX00 XX01 00 01 PD AA AA 2AA 555 2AA 555 55 55 555 AAA SA 10 30
Autoselect (Note 8)
Device ID, Top Boot Block Device ID, Bottom Boot Block
X01
X02
(SA) X02
Legend: X = Dont care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A17A12 uniquely select any sector.
Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except when reading array or autoselect data, all bus cycles are write operations. 4. Data bits DQ15DQ8 are dont cares for unlock and command cycles. 5. Address bits A17A11 are dont cares for unlock and command cycles, unless SA or PA required. 6. No unlock or command cycles required when reading array data. 7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data).
8. The fourth cycle of the autoselect command sequence is a read cycle. 9. The data is 00h for an unprotected sector and 01h for a protected sector. See Autoselect Command Sequence for more information. 10. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 11. The Erase Resume command is valid only during the Erase Suspend mode.
16
Am29F800B
P R E L I M I N A R Y
START
DQ7 = Data?
Yes
No No
DQ5 = 1?
DQ7 = Data?
Yes
No FAIL PASS
Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.
21504C-8
Figure 4.
Am29F800B
17
P R E L I M I N A R Y
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 6 shows the outputs for RY/BY#. The timing diagrams for read, reset, program, and erase shows the relationship of RY/BY# to other signals.
The Write Operation Status table shows the outputs for Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit algorithm, and to the Toggle Bit Timings figure in the AC Characteristics section for the timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II.
18
Am29F800B
P R E L I M I N A R Y The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 5).
START
Read DQ7DQ0
Read DQ7DQ0
(Note 1)
No
No
DQ5 = 1?
Yes
(Notes 1, 2)
No
Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete
Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. See text.
21504C-9
Figure 5.
Am29F800B
19
P R E L I M I N A R Y Table 6.
Operation Standard Mode Erase Suspend Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector Reading within Non-Erase Suspended Sector Erase-Suspend-Program
Notes: 1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 2. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See DQ5: Exceeded Timing Limits for more information.
20
Am29F800B
P R E L I M I N A R Y
20 ns
Figure 6.
21504C-11
Figure 7.
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) . . . . . . . . . . . 0C to +70C Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . 40C to +85C Extended (E) Devices Ambient Temperature (TA) . . . . . . . . 55C to +125C VCC Supply Voltages VCC for 5% devices . . . . . . . . . . .+4.75 V to +5.25 V VCC for 10% devices . . . . . . . . . . . .+4.5 V to +5.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
Am29F800B
21
P R E L I M I N A R Y
ICC1
19 36
50 60
mA mA
0.4
mA V V V V V
4.2
Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. ICC active while Embedded Erase or Embedded Program is in progress. 3. Not 100% tested.
22
Am29F800B
P R E L I M I N A R Y
40
mA
28
50
mA
VCC Active Write Current (Notes 1 and 2) VCC Standby Current Input Low Voltage Input High Voltage Voltage for Autoselect and Temporary Sector Unprotect Output Low Voltage Output High Voltage
30 0.3
mA A V V V V V V V
Notes: 1. ICC active while Embedded Erase or Embedded Program is in progress. 2. Not 100% tested.
Am29F800B
23
P R E L I M I N A R Y
TEST CONDITIONS
Table 7.
5.0 V Test Condition Device Under Test CL 6.2 k Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels 5 0.03.0 1.5 1.5 20 0.452.4 0.8, 2.0 0.8, 2.0 ns V V V 2.7 k Output Load Output Load Capacitance, CL (including jig capacitance) 30 -55 All others 1 TTL gate 100 pF Unit
Test Specifications
Figure 8.
Test Setup
KS000010-PAL
24
Am29F800B
P R E L I M I N A R Y
tAXQX
tOH
Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1)
Min
ns
Notes: 1. Not 100% tested. 2. See Figure 8 and Table 7 for test specifications.
tRC Addresses CE# tOE tOEH WE# HIGH Z Outputs RESET# RY/BY# Output Valid tCE tOH HIGH Z tDF Addresses Stable tACC
OE#
0V
21504C-13
Figure 9.
Am29F800B
25
P R E L I M I N A R Y
RY/BY#
RESET# tRP
21504C-14
Figure 10.
RESET# Timings
26
Am29F800B
P R E L I M I N A R Y
CE#
OE#
DQ15/A-1
DQ0DQ14
DQ15/A-1
21504C-15
Figure 11.
CE#
BYTE#
tSET (tAS)
tHOLD (tAH)
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
21504C-16
Figure 12.
P R E L I M I N A R Y
Notes: 1. Not 100% tested. 2. See the Erase and Programming Performance section for more information.
28
Am29F800B
P R E L I M I N A R Y
AC CHARACTERISTICS
Program Command Sequence (last two cycles) tAS tWC Addresses 555h PA tAH CE# tGHWL OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# tVCS VCC Status DOUT tRB tWPH tWHWH1 Read Status Data (last two cycles)
PA
PA
tCH
A0h
Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode.
21504C-17
Figure 13.
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P R E L I M I N A R Y
AC CHARACTERISTICS
Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA
555h for chip erase
VA tAH
VA
CE# tGHWL OE# tWP WE# tCS tDS tDH Data 55h 30h
10 for Chip Erase In Progress Complete
tCH
tWPH
tWHWH2
tRB
Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status). 2. Illustration shows device in word mode.
21504C-13
Figure 14.
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P R E L I M I N A R Y
AC CHARACTERISTICS
tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ7
High Z
VA
VA
tOE tDF
Complement
Complement
True
Valid Data
High Z
Status Data
Status Data
True
Valid Data
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
21504C-18
Figure 15.
tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ6/DQ2 tBUSY RY/BY#
High Z
VA
VA
VA
tOE tDF
Valid Data
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.
21504C-19
Figure 16.
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P R E L I M I N A R Y
AC CHARACTERISTICS
Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete
DQ6
DQ2
Note: The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the erase-suspended sector.
21504C-20
Figure 17.
12 V
21504C-21
Figure 18.
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P R E L I M I N A R Y
Notes: 1. Not 100% tested. 2. See the Erase and Programming Performance section for more information.
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P R E L I M I N A R Y
AC CHARACTERISTICS
555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase
Data# Polling PA
Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH
A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase
tAS tAH
tWHWH1 or 2
tBUSY
DQ7#
DOUT
RESET#
RY/BY#
Notes: 1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data. 2. Figure indicates the last two bus cycles of the command sequence, with the device in word mode.
21504C-22
Figure 19.
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P R E L I M I N A R Y
Notes: 1. Typical program and erase times assume the following conditions: 25C, 5.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90C, VCC = 4.5 V (4.75 V for -55), 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5 for further information on command definitions. 6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) Input voltage with respect to VSS on all I/O pins VCC Current Min 1.0 V 1.0 V 100 mA Max 12.5 V VCC + 1.0 V +100 mA
Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time.
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz.
DATA RETENTION
Parameter Minimum Pattern Data Retention Time 125C 20 Years Test Conditions 150C Min 10 Unit Years
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P R E L I M I N A R Y
13.10 13.50
15.70 16.30
22
2.80 MAX.
0.60 1.00
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P R E L I M I N A R Y
PHYSICAL DIMENSIONS (continued) TS 04848-Pin Standard Thin Small Outline Package (measured in millimeters)
0.95 1.05 Pin 1 I.D.
1 48
11.90 12.10
0.50 BSC
24 25
0.05 0.15
11.90 12.10
0.50 BSC
24 25
0.05 0.15
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P R E L I M I N A R Y
Erase and Programming Performance Corrected word and chip programming times.
Revision C
Global Formatted for consistency with other 5.0 volt-only data sheets.
Revision C+1
Distinctive Characteristics Changed typical program/erase current to 30 mA to match the CMOS DC Characteristics table. Changed minimum endurance to 1 million write cycles per sector guaranteed. AC Characteristics
Erase/Program Operations: Corrected the notes reference for tWHWH1 and tWHWH2. These parameters are 100% tested. Changed tDS and tCP specifications for 55 ns device. Changed tWHWH1 word mode specification to 12 s. Alternate CE# Controlled Erase/Program Operations: Corrected the notes reference for tWHWH1 and tWHWH2. These parameters are 100% tested. Changed tDS and tCP specifications for 55 ns device. Changed tWHWH1 word mode specification to 12 s.
Temporary Sector Unprotect Table Added note reference for tVIDR. This parameter is not 100% tested. Erase and Programming Performance In Notes 1 and 6, changed the endurance specification to 1 million cycles.
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Trademarks
Copyright 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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