Serial ATA

Seminar SATA II
Thorsten Scholz
thorsten.scholz@ibs-networks.de

Serial ATA
Seminar SATA II
2008 Ingenieurbro T. Scholz, www.IBS-Networks.de, all rights reserved No part or whole of this document may be reproduced, transmitted, transcribed, stored in a retrieval system or translated into any language without prior permission of Ingenieurbro Scholz. This document is provided "as is", without warranty of any kind, neither expressed nor implied, including but not limited to a particular purpose. Ingenieurbro Scholz may make improvements and/or changes in this document without notice at any time. 2

Contents
General Overview El t i l Interface Electrical I t f Data Communication Application Layer SATA Link Expansion SATA Integrated Circuits

Serial ATA
General Overview
Standards Topology Terms and Definitions

SATA Overview
Responsibilities espo s b t es
Serial ATA International Organization (SATA-IO)
www.sata-io.org Dell, HP, Hitachi, Intel, Seagate, Western Digital,

Connectors: SFF, www.sffcommittee.com (P)ATA Standards

InterNational Committee for Information Technology Standards, T13 Group www.incits.org i it www.t13.org

SATA Overview
Parallel ATA aa e
ATA = Advanced Technology Attachment Parallel ATA (PATA)
40/80 Pin cable 16 Bit bus width Up to 66 MHz p max. Data Rate of 133 MB/s 2 Connections per Controller (Master & Slave) in bus connection

SATA Overview
Se a Serial ATA
Register-compatible with Parallel ATA Command set from PATA-6 used LVD S g V Signaling g Data rates of 1,5 Gbps and 3,0 Gbps Line coding for fault-tolerance and signal integrity Point-to-Point connections (no Master/Slave) 7-Pin Interface M use S May Spread S t d Spectrum Cl ki t reduce EMI Clocking to d
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SATA Overview
Co pat b ty Compatibility
SATA is Software compatible to Parallel ATA Identical Register Interface
OS
Application Application

OS Parallel ATA Adapter

M
Application

Application

Driver

Driver

Serial ATA HBA

S
Application

Application

Parallel P ll l ATA

Serial S i l ATA
10

SATA Overview
Se a Serial ATA Link Speed
Data rates of 1,5 Gbps and 3,0 Gbps 20% used for line code Link layer speed o 150/300 MB/s ye of 50/300 /s Separate Transmit and Receive Pairs Full-Duplex-operation BUT: only one frame active at a given time Only Handshake/Error Control in backward direction

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SATA Overview
Terms a d Definitions e s and e t o s
Gen1 Gen2 GenX Defines SATA Interface with transmission rate of 1,5 Gbps Defines SATA Interface with transmission rate of 3,0 Gbps Gb Defines SATA Interface with any transmission rate

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Serial ATA
Electrical Interface
Usage Models Cables and Connectors Analog Frontend (AFE)

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Electrical Interface
Usage Models ode s
Internal connection Host to Device Short Backplane to Device Long Backplane to Device o g c p e o ev ce Internal Cabled Disk Arrays System to System Interconnects Serial Attached SCSI (SAS)

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Electrical Interface
Reference Points e e e ce o ts
Layer Association: Physical Interface (PHY) Divided into two Generations: 1 (1,5 Gbps) and 2 (3 Gbps) Reference/Compliance Points described by Electrical Specification: e e e ce/Co p ce o s desc bed ec c Spec c o :
Gen1i: Gen1m:
Gen1x:

Internal host to device applications Short backplane and external single-lane cabling applications single lane Extended length for long backplane and external multi-lane applications pp

Same association for Generation 2 specifications (Gen2i, )

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Electrical Interface
Internal Power Cab e te a o e Cable
Pin Contact Description 3,3 Volt 3,3 V lt 3 3 Volt 3,3 Volt Pre-Charge GND GND GND 5 Volt Pre-Charge 5 Volt 5 Volt GND DAS/DSS GND 12 Volt Pre Charge Pre-Charge 12 Volt 12 Volt 35

Cable consists of
3,3 Volt power and pre-charge 5 Volt power and pre-charge 12 Volt power and pre-charge Ground (GND) Device Activity Signal (DAS) or Disable Staggered Spinup (DDS)

P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14

5 AWG 18 wires (1 mm)

3 wires for voltage 2 wires for GND

P15

Electrical Interface
Cab e ect ca Specification Cable Electrical Spec cat o
Description Connector Impedance Cable Impedance Pair Matching Impedance g p Common Mode Impedance Maximum Insertion Loss (10-4500 MHz) Maximum Crosstalk (Single Lane) Maximum Crosstalk (Multilane) Maximum Rise Time Maximum Intersymbol Interference M i I t b lI t f Maximum Intra-Pair Skew Gen1i/Gen2i 100 Ohms 15% 100 Ohms 10% 5 Ohms 20 40 Ohms 6 dB 26 dB 30 dB 25 ps (20/80) 50 ps 10 ps Gen1m/Gen2m 100 Ohms 15% 100 Ohms 10% 5 Ohms 20 40 Ohms 8 dB 26 dB 30 dB 150 ps (20/80) 50 ps 20 ps Gen1x/Gen2x 100 Ohms 10% 100 Ohms 5% 5 Ohms 25 40 Ohms 16 dB 30 dB 150 ps (20/80) 60 ps 20 ps

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Electrical Interface
Voltage levels o tage e e s
Input and Output voltage levels dependant on usage model
Description (all values in mV) Output Voltage Input Voltage Output Voltage Input Voltage Gen1 Gen_i Gen_m Gen_x 400-1600 275-1600 400-1600 240-750 275-1600 500 (400-600) 400 (325-600) 400 (240-600)

Gen2

400-700 275-750

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Electrical Interface
Hot-Plug ot ug
Surprise Hot-Plug capable
Insertion or Removal under power GenXx, GenXm and GenXi in Short Backplane applications AC coupling

OS-Aware Hot-Plug capable g p

Insertion or Removal with unpowered or powered backplane Data connector is in defined state

The removal of a rotating device should be prevented by the system designer!

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Electrical Interface
Impedance Ca b at o peda ce Calibration
Host and Device may employ on-chip impedance matching Host launches a step-waveform
Impedance measurement using TDR techniques Adjusts impedance settings as necessary

Device assumes calibrated far end far-end

Uses this calibration as reference for its own calibration

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Electrical Interface
Interface Power States te ace o e
PHYRDY
Phy logic and PLL are on and active Interface is synchronized and capable of transmitting and receiving data

Partial
Phy logic in reduced p y g power state Signal lines are at common mode voltage (neutral) Transition latency to PHYRDY no longer than 10 s

Slumber
Phy logic in reduced power state Transition latency to PHYRDY no longer than 10 ms
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Electrical Interface
Elasticity Buffer ast c ty u e
Serial ATA allows clock tracking as well as non-tracking implementations For non-tracking implementations an Elasticity Buffer is required Phy layer supports unlimited frame size, Elasticity Buffer is finite Phy layer solution needed Maximum frequency difference is up to 0,5% for an SSC device talking to a non-SSC device non SSC Phy layer inserts two ALIGN primitives every 254 DWORDS Elasticity Buffer of 64 Bits (2 DWords) is sufficient
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Serial ATA
Data Communication
Task Overview Encoding/Decoding Primitives and Frames Data Flow Frame Information Structure

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Data Communication
Link Layer: Tasks aye as s
Framing CRC Generation and Check Flow Co o and Handshaking ow Control d ds g Encoding and Decoding Scramble / Descrambling for EMI purposes

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Data Communication
Link Layer: Encoding aye cod g
Character to be transmitted consists of 8 Data Bits and Control indicator Control indicator bit is D for data and K for control information Total of 8+1 Bit to be encoded to 10 Bit (8B/10B code) Unencoded Bits are named A to H Control indicator named Z H, Each character is given a name by Zxx.y with
Z is the value of the control indicator
Bit 7 H 6 G y 5 F 4 E 3 D 2 C xx 1 B 0 A Ctrl Z Z

xx is the decimal value of bits A to E y is the decimal value of bits F to H

Unencoded Notation N t ti

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Data Communication
Link Layer: Notation aye otat o
Notation of 0xBC Control 0b10111100 K K28.5 N t ti of 0x4A Data Notation f 0 4A D t 0b01001010 D D10 2 D10.2 Only 2 control characters exist: K28.3 and K28.5 If not stated otherwise Control variable Z is always D
Bit Unencoded Notation N t ti 7 H 6 G y 5 F 4 E 3 D 2 C xx 1 B 0 A Ctrl Z Z

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Data Communication
Link Layer: Encoding Sc e e aye cod g Scheme
Widmer and Franaszek 8B/10B Code Two-stage coding: 5B/6B and 3B/4B 5B/6B has 5 bits input p us running d sp y 5 /6 s b s pu plus u g disparity 3B/4B has 3 bits input plus running disparity Running disparity is
Negative Positive Same if output bits contain more zeroes than ones if output bits are 111000 or 1100 bi if output bits contain more ones than zeroes if output bits are 000111 or 0011 if output bits have equal number of ones and zeroes
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Data Communication
Link Layer: Encoding Sc e e aye cod g Scheme
Code guarantees to generate always opposite disparity or neutral Aim of Code
DC free output Clock containment of output

Output notation in small letters

EDCBA HGF encoded to abcdei encoded t fghj d d to f hj

Final coded word is abcdeifghj a is transmitted first

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Data Communication
Link Layer: Code Table 5 /6 aye ab e 5B/6B
rd indicates whether incoming disparity is changed (-rd) or not (rd)

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Data Communication
Link Layer: Code Table 3 / aye ab e 3B/4B
rd indicates whether incoming disparity is changed (-rd) or not (rd) Special case for input Dxx.7: Coding depends on previous 2 bits

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Data Communication
Link Layer: Code Table Control Codes aye ab e Co t o
Existence of 2 Control characters K28.3 and K28.5 Any control characters inverts the running disparity
rd is always -rd

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Data Communication
Link Layer: Encoding aye cod g
Encoding of Data Byte: 0x9A, last rd should be negative (rd-) Binary representation 0x9A __ __ __ __ __ __ __ __ Character notation C ce o o Binary 5B/6B output Binary 3B/4B output Resulting 8B/10B output D___.__ . __ __ __ __ __ __, rd __ __ __ __ __, rd __ __ __ __ __ __ __ __ __ __ __, rd __

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Data Communication
Link Layer: Encoding/LUT aye cod g/ U
Encoding Examples
Incoming rd-, 0x4A D10.2 Incoming rd+, 0xEB D11.7 Incoming rd-, 0x00 D0.0 Incoming rd+, 0xF8 D24.7 010101 0101 rd- (neutral encoding) 110100 1000 rd- (P7 replacement) 100111 0100 rd 001100 1110 rd+

Three previous tables may be combined to one lookup table

256 plus 2 entries

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Data Communication
Primitive Format t e o at
All Primitives begin with a Control character K28.3 or K28.5 Followed by 3 non-control characters to complete DWord 8B/10B Encoding applies 8 / 0 cod g pp es ALIGNP (D27.3 D10.2 D10.2 K28.5) is special primitive
C Command: Phy l d Ph layer re-adjusts internal operations dj i l i Only primitive that uses the K28.5 Control character Has neutral disparity, can be injected without changing rd May be consumed by Phy layer or dropped by Link layer

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Data Communication
Primitives: Frame Example t es a e a pe
Frame transmission from host to device
Host X_RDY X RDY X_RDY SOF Data Data Data EOF WTRM WTRM WTRM WTRM SYNC SYNC Device R_RDY R RDY R_RDY R_RDY R_RDY R_IP R_IP R_IP R_IP R_IP R_OK R_OK R_OK R OK R_OK 94 Host has decoded R_OK and sends Idle R OK Device has received EOF and computes CRC CRC OK device sends R_OK Device has decoded SOF and sends R_IP Host has decoded R_RDY and starts frame Description Device decodes X RDY and answers R RDY X_RDY R_RDY

Data Communication
Primitives: Flow Co t o Example t es o Control a p e
Frame transmission from host to device
Host SOF Data Data Data HOLD HOLD HOLD Data Data EOF WTRM WTRM WTRM Device R_RDY R RDY R_RDY R_IP R_IP R_IP R_IP HOLDA HOLDA HOLDA R_IP R_IP R_OK R OK R_OK 95 Device has received EOF and computes CRC CRC OK device sends R OK R_OK Device has decoded HOLD and sends HOLDA Host resumes data transfer Host send buffer empty sending HOLD Device has decoded SOF and sends R_IP Description Host has decoded R_RDY and starts frame R RDY

Data Communication
Primitives: Co t ue Example t es Continue a p e
Frame transmission from host to device
Host X_RDY X RDY X_RDY SOF Data Data Data EOF WTRM WTRM CONT any SYNC SYNC Device R_RDY R RDY R_RDY CONT any R_IP R_IP CONT any any R_OK R_OK CONT any 96 Host has decoded R_OK and sends Idle R OK Device has received EOF and computes CRC CRC OK device sends R_OK Device has decoded SOF and sends R_IP Host has decoded R_RDY and starts frame Description Device decodes X RDY and answers R RDY X_RDY R_RDY

Data Communication
Primitives: Co ect o Init t es Connection t
Initialization of Communication Not temp. correct
Host
COMRESET Idle COMWAKE Idle D10.2 ALIGN

Device
Idle COMINIT Idle COMWAKE ALIGN ALIGN

Description Host issues COMRESET (informative) Device issues COMINIT (informative) Host issues COMWAKE (informative) Device issues COMWAKE (informative) Host tries to lock on devices ALIGN Host locked on ALIGN sends ALIGN now Device locked on Host-ALIGN, sending SYNC

T Temporally correct ll t

ALIGN ALIGN ALIGN ALIGN ALIGN

SYNC SYNC SYNC SYNC SYNC SYNC SYNC

Host detected 1st SYNC from Device

Host detected 3rd SYNC from Device Host wants to transmit data

X_RDY X RDY X_RDY

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Data Communication
Primitives: Co s o t es Collision
Frame transmission from host to device
Host SYNC X_RDY X_RDY X_RDY R_RDY R_RDY R_RDY R_RDY R_IP R_IP R_IP R_IP R IP R_OK Device SYNC SYNC X_RDY X_RDY X_RDY X_RDY SOF Data Data EOF WTRM WTRM WTRM 97 Device detected R_RDY, sends data Description Idle Host signals transmission Device signals transmission Device detects hosts transmission Host detects device transmission

Data Communication
ATA Registers a d S g a s eg ste s and Signals
Serial ATA is compatible with ATA Software ATA emulation needed Host thinks o w os s of writing to ATA registers g o eg s e s
No direct access possible in SATA SATA holds copy of devices register block Named Shadow Register Block W iti to this block triggers Register Transfer to Device Writing t thi bl k t i R it T f t D i

Signal INTRQ is reflected by a bit in a register

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Data Communication
ATA Signals Sg as
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Signal Name /RESET GND DD7 DD8 DD6 DD9 DD5 DD10 DD4 DD11 DD3 DD12 DD2 DD13 DD1 DD14 DD0 DD15 GND KEY Description Reset Ground Data 7 Data 8 Data 6 Data 9 Data 5 Data 10 Data 4 Data 11 Data D t 3 Data 12 Data 2 Data 13 Data 1 Data 14 Data 0 Data 15 Ground Key (Pin missing) Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Signal Name DMARQ GND /DIOW GND /DIOR GND IORDY SPSYNC:CSE L /DMACK GND INTRQ /IOCS16 DA1 PDIAG DA0 DA2 /IDE_CS0 /IDE_CS1 /ACTIVE GND Description DMA Request Ground Write Strobe Ground Read Strobe Ground I/O Ready (obsolete) Spindle Sync or Cable Select DMA Acknowledge Ground G d Interrupt Request IO Chip Select 16 Address 1 80 pin 80-pin cable detect detect. Address 0 Address 2 Chip Select Chip Select Led driver Ground

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Data Communication
FIS: Register Host Device g
Transfers contents of Shadow Register Block to device FIS Type 0x27, Length of 5 DWords (20 Bytes)
PM Port C Device port address (e.g. Port Multiplier) Command, set if command register addressed, not set if control r.

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Data Communication
FIS: Register Host Device g
Command, Features, LBA Low/Mid/High, Device, Control and Sector Count correspond to the appropriate registers in the Shadow Register Block LBA Low/Mid/High (exp), Features (exp) and Sector Count (exp) correspond to the appropriate expanded fields in the Shadow Register Block All reserved field should be cleared on write and ignored on read

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Data Communication
FIS: Register Device Host g
FIS Type of 0x34 Used by device to indicate command completion
I is Interrupt Bit and reflects the interrupt line of the device Status and Error contain the appropriate values of the Shadow Register Block

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Data Communication
FIS: Data ( d ect o a ) S ata (Bidirectional)
Transportation of payload data Data read or written to number of sectors, no register transfers Generated by Host or Device Ge e ed os o ev ce Generally one element of sequence of transactions leading to data transfer In DMA operation multiple Data FIS may follow With PIO mode number of bytes transferred shall be equal to bytes indicated in Transfer Count field Recipient is not expected to buffer data for CRC checking
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Data Communication
FIS: O e e S Overview
FIS Register Set Device Bits Se ev ce s DMA Setup DMA Activate PIO Setup Data BIST A ti t Activate X X X H->D D->H X X X X X X X X Type 0x27 / 0x34 0 0xA1 0x41 0x39 0x5F 0x46 0x58 0 58
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Data Communication
Protocol: Device Power-On otoco e ce o e O
Hardware reset detected by Phy (Power-on or COMRESET) State: Device Hardware Reset (DHR) After COMRESET is negated hardware is initialized and powe o e CO S s eg ed dw e s ed d power-on self-test is executed
POST successful: Device sends Register FIS with g Sector Count = 1, LBA = 1, Device = 0, Error = 1, Status 0x00 - 0x70 POST failure: Device sends Register FIS with Sector Count = 1, LBA = 1, Device = 0, Error = any but 1, Status 0x00 - 0x70

Device transitions to Device Idle (DI) state

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Data Communication
Protocol: Device Software Reset otoco e ce So t a e eset
State: Device Software Reset (DSR) Software reset by Register FIS (SRST-Bit set in control register) C C-Bit must be set to zero to address control register us se o e o o add ess co o eg s e Software reset by Register FIS (SRST-Bit cleared) Device initializes and executed diagnostics (same as DHR) Result is transferred to Host via Register FIS Transition to Device Idle (DI)

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Data Communication
Example: Software Reset a p e So t a e eset
Host H t
Transmit C=0, SRST=1 Transmit C=0, SRST=0 Register FIS g Register FIS

Device D i
Process command Process command Initialization and Self-Test

Update Shadow Register Block

Register FIS g

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Data Communication
Protocol: Device Idle otoco e ce d e
Device waits for FIS, state is Device Idle (DI) While idle device or Host send SYNC primitives FIS reception: S ecep o :
Register FIS, C-Bit cleared, SRST set Register FIS C-Bit cleared, SRST cleared FIS, C Bit cleared Register FIS, C-Bit set DMA Setup FIS S t Unexpected FIS DSR (Reset) DI (Idle) DI2 (CheckCmd) DI (Idle) (Idl ) DI (Idle)

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Data Communication
Protocol: Device Idle C ec Co otoco e ce d e Check Command a d
Device received Register FIS State is Device Idle 2:Check_command (DI2:Check_command) Determine required command protocol ee e equ ed co d p o oco
Non-data command PIO data-in data in PIO data-out READ DMA WRITE DMA DEVICE RESET DND0: Non-data DPIOI0: PIO_in PIO in DPIOO0: PIO_out DDMAI0 DMA_in DDMAI0: DMA i DDMAO0: DMA_out DDR0: Device_reset
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Data Communication
Protocol: PIO In otoco O
0. Successfully parsed PIO In command 1. Prepare a data block for transfer 2. Transmit PIO Setup FIS to Host . s O Se up S o os 3. Transmit Data FIS
If more data than 8192 B d h Bytes (2048 DW d ) requested proceed to 1 DWords) d d 1.

4. Transition to Device Idle (DI)

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Data Communication
Example: PIO Read from Device a pe O ead o e ce
Host
Initialization of Shadow Control Registers Transfer Shadow Control Registers Update Status Register Update Status Register with E_Status Update Status Register Update Status Register with E_Status Register FIS R i PIO Setup FIS Data FIS

Device

Process command

PIO Setup FIS Data FIS

R l final status is not transferred Real fi l t t i tt f d

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Data Communication
ATAPI PIO In O
1. Host sends PACKET command via Register FIS 2. After device is ready to receive ATAPI command packet PIO Setup FIS is transmitted to Host 3. Host writes command to Shadow Data Register and sends Data FIS containing the command to device 4. Device processes command packet and starts delivering data
Data transfer announced with PIO Setup FIS to Host (Multiple) Data FIS follow

5. Device t 5 D i transmits Register FIS at end of transfer it R i t t d ft f

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Data Communication
Example: ATAPI PIO Read from Device a pe O ead o e ce
Host
PACKET command Register FIS PIO Setup FIS Send command packet Data D t FIS Process command Send data announcement Send data Send register update

Device
Request command packet

PIO Setup FIS Receive data Update Shadow Registers Data FIS Register FIS

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Data Communication
PIO vs. DMA Transfers O s a ses
DMA
Data from/for Data FIS is handled by Host DMA controller

PIO
Data is written to (serial) FIFO that is attached to Shadow Data Register Host reads Shadow Data Register to get/set data g g A FIFO overflow or underflow is prevented by SATA Flow Control Host register access time defined by PIO mode setting

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Serial ATA
Application Layer
Host Adapter Register Interface Parallel ATA Emulation Native Command Queuing HDD Activity Indication

152

Application Layer
Feature: Native Co eatu e at e Command Queuing a d Queu g
Allows commands to be accepted even if one or more previously accepted commands are not completed All commands send must carry a NCQ tag NCQ tag is identifier for command slot in queue Queue size is defined in IDENTIFY DEVICE Word 75 Status of queue is returned to Host in Set Device Bits FIS
Set Device Bits FIS is send to Host after each successful command completion

U Unsuccessful command completion is indicated by Register FIS or f l d l i i i di db R i Set Device Bits FIS (both with ERR-Bit set) to Host 180

Application Layer
Feature: NCQ Commands eatu e CQ Co a ds
NCQ consists of two commands to read and write data First-party DMA (FPDMA) READ FPDMA QUEUED 0 60 / W QU U 0x60 WRITE FPDMA QU U QUEUED 0 6 0x61
FUA: Prio:
Register Features Sector Count LBA Low LBA Mid LBA High Device D i Command

Forced Unit Access (Data must be on media) Command Priority: 0 = Normal, 1 = High Normal
15 14 13 12 11 10 Prio Reserved 9 8 7 6 5 4 3 2 1 0 Sector Count NCQ Tag na LBA LBA LBA FUA 1 R/0 0 Reserved R d 60h/61h
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Application Layer
Feature: NCQ Command Sending eatu e CQ Co a d Se d g
NCQ Commands are transferred via Register FIS to device BSY Bit and DRQ Bit is not set Register FIS is used to inform Host o co eg s e S s o o os of command acceptance d ccep ce NCQ and normal commands are not allowed to mix If this is tried all unexecuted commands in queue are marked failed Host implements 32 Bit SActive Register and sets the appropriate Bit position to 1 if a NCQ command is send with this tag Host may issue as many commands as there are empty slots in y y py SActive
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Application Layer
Feature: NCQ Data Delivery eatu e CQ ata e e y
Device issues DMA Setup FIS when data is ready to be transferred Originating commands tag is used as buffer identifier Host controller must find appropriate context for this identifier os co o e us d pp op e co e o s de e

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Application Layer
Feature: NCQ Data Delivery eatu e CQ ata e e y
Only one DMA Setup FIS will be send
If transfer spans multiple Data FIS additional DMA Setup FIS not needed

For Host to device transfers the DMA Activate FIS may be omitted if Auto-Activate feature is used in DMA Setup FIS Transferring of data depends on two feature settings g p g
Non-zero buffer offsets in DMA Setup FIS Guaranteed in order data delivery in-order

If non-zero buffer offsets are not supported or not enabled a command is not allowed to be splitted Data transfer must be satisfied to completion after Setup FIS
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Application Layer
Feature: NCQ Data Delivery eatu e CQ ata e e y
Non-zero buffer offsets enabled / in-order delivery enabled
Data transfer may be interrupted after a specific DMA Setup FIS Interleaving of commands is not allowed Data transfer may be continued with additional DMA Setup FIS

Non-zero buffer offsets enabled / in-order delivery disabled y

Data transfer may be interrupted after a specific DMA Setup FIS Interleaving of commands is allowed Data transfer may be continued with additional DMA Setup FIS

185

Application Layer
Feature: NCQ Success Notification eatu e CQ ot cat o
After last Data FIS of a command device sends Set Device Bits FIS
Set Device Bits FIS includes SActive Register in Reserved field Bits set in the SActive fields indicate successful completion of command All bit position set shall be cleared in Hosts SActive Register as completed Host

may send command with Tags having value of zero in SActive y g g

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Application Layer
Feature: NCQ Error Notification eatu e CQ o ot cat o
Command raises error condition on reception/processing
Device sends Register FIS with ERR-Bit set

Command executed in queue raises error

Device sends Set Device Bits FIS with ERR-Bit set Bit for failed command (and completed commands if any) also set ( p y)

Stops all command processing until Host action Further commands to the device are aborted with ERR-Bit set h d h d i b d ih i Host shall issue a READ LOG EXT command to determine exact error condition
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Application Layer
Example: NCQ FPDMA Read a p e CQ ead
Host
READ FPDMA QUEUED Register FIS Queuing of command Register FIS Additional commands with different tags Prepare for reception DMA Setup FIS O se Offset = 0 Data FIS Data FIS Data FIS Data ready, execution of command

Device

Non-zero buffer offsets In-order

Data FIS Update SActive Set Device Bits FIS

Command finished update SActive 191

Application Layer
Example: NCQ FPDMA Read a p e CQ ead
Host
READ FPDMA QUEUED Register FIS Queuing of command Register FIS Additional commands with different tags Prepare for reception DMA Setup FIS Offset = 0 Data FIS Data FIS Additional commands to Device Prepare for reception DMA Setup FIS S t Offset = 16384 Data FIS Data FIS Update SActive Set Device Bits FIS Data ready, further execution of command Data ready, execution of command Data not ready

Device

Non-zero buffer offsets In-order

Command finished update SActive 192

Application Layer
Example: NCQ FPDMA Read a p e CQ ead
Host
2 FPDMA READ Both > 8192 Bytes CMD 1 CMD 2 DMA Setup FIS Offset = 8192 Data FIS DMA Setup FIS Offset = 0 Data FIS DMA Setup FIS Offset = 0 Data FIS DMA Setup FIS Offset = 8192 Data FIS

Device

Non-zero buffer offsets In-order

Queuing of commands

Cmd 2 Bytes 8192 to X

Cmd 1 Bytes 0 to 8191

Cmd 2 Bytes 0 to 8191

Cmd 1 Bytes 8192 to X

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Application Layer
HDD Activity Indication ct ty d cat o
May be vendor-specific or Parallel ATA emulated by Host Emulation:
If BSY or SActive set then Else LED = On LED = Off

LED is valid for both Master-only and Master-Slave SATA Hosts y If Master-Slave mode LED should be always on ATAPI devices shall not generate LED indication

Multiple SATA channels LED indications should be connected by wired-OR

201

Application Layer
HDD Activity Indication ct ty d cat o
Activity signal shall be
Active low Open collector/drain

SATA controllers may include activity aggregated indication pin and/or pin for each channel

202

Serial ATA
SATA Link Expansion
Port Multiplier Port Selector

203

Serial ATA
SATA Integrated Circuits
Port Multiplier PATA Bridge Host controller

232

SATA Integrated Circuits

Port Multiplier S 3 6 o t u t p e SiI 3726
Silicon Image 3726 Port Multiplier 1:5 SATA II Port Multiplier Programmable Tx Voltage og be Vo ge 8 kByte FIFO buffer per device 32 GPIO Pins controlled by SATA (GSCR[130]-Register) Power Mode request support Integrated SATA to I2C Bridge

Picture Source: SiI 3726 Prodct Brief, SiI 3726CB364, 2004 Silicon Image, Inc.

233

SATA Integrated Circuits

S 3726 oc SiI 3 6 Block Diagram ag a

Picture Source: SiI 3726 Prodct Brief, SiI 3726CB364, 2004 Silicon Image, Inc.

234

SATA Integrated Circuits

PATA-SATA Bridge SiI 3811 S dge S 38
Silicon Image 3811 Parallel ATA to SATA Bridge Supports SSC Receive Power Management owe ge e Ultra/ATA 133 Parallel Interface Serial ATA 1,5 Gbps Interface 48 Bit LBA addressing (16 Bit Registers) Application: Mainboard or Device

Picture Source: SiI 3811 Prodct Brief, SiI PB-58 rev1 8/06, 2004 Silicon Image, Inc.

235

SATA Integrated Circuits

S 3811 oc SiI 38 Block Diagram ag a

Picture Source: SiI 3811 Prodct Brief, SiI PB-58 rev1 8/06, 2004 Silicon Image, Inc.

236

Serial ATA
Thanks for your Attention

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