Solution to Mid-semester Examination Autumn Semester 2006 EE309:Microprocessors

Soln. to Q1: We want to use a 2KB ROM and a 4KB RAM in an 8085 system. The ROM should respond to the address range 0000H to 07FFH. The RAM should cover the address range 0800H to 17FFH. Design the logic (using only NAND, NOR and INVERTER gates) to generate the negative true chip select signals for the ROM and the RAM. The ROM covers the binary address range: A15-A12 0000 0000 A11-A8 0000 0111 A7-A4 0000 1111 A3-A0 0000 1111

From to

This implies that all combinations of A10 through A0 reside in the ROM. So the 11 bits (A10-A0) should be connected to the address pins of the ROM, to be decoded inside the ROM. All the higher bits (15 through A11) should be 0. Therefore, the negative true chip select is (A15+A14+A13+A12+A11). 1 mark One way to generate this logic is as shown below:

A15 A14 A13 A12 A11

CS

1 mark The RAM covers the binary range: A15-A12 0000 0001 A11-A8 1000 0111 A7-A4 0000 1111 A3-A0 0000 1111

From to

Thus, the top 3 bits (A15-A13) are always 0; the bottom 11 bits (A10-A0) go through all their combinations while Bits A12 and A11 acquire values which are 01 and 10. The logic for A12 and A11 can be written by inspection, or derived from this Karnaugh map: A11 A12 0 1 0 0 1 1 1 0 as (A11 A12 + A11 A12).

Thus we want the output to be 0 when A15 = A14 = A13 = 0 AND (A11 A12 + A11 A12) = 1. Therefore the decode function is: (A15 + A14 + A13) (A11 A12 + A11 A12) 2 marks

One way to implement this function is:

A15 A14 A13 A12

CS

A11
1 mark Soln. to Q2: For all parts of this question, assume the following initial contents for registers and for memory locations 2710H to 2715H. All numbers are in hex. Register content Address Data PC 2700 2710 0B SP 27FF 2711 27 H 27 2712 64 L 10 2713 36 B 27 2714 F8 C 12 2715 27

Assume that all ags and memory locations 27F0 to 27FF are 0 initially. Describe what happens when the following code fragments are run. Execution begins from the location 2700 and ends when we reach a HLT instruction. Description must be in the order of execution of instructions. After the execution of each instruction, give the values of any registers, memory locations or ags which have changed. i) Code Label Instruction 2A1027 STRT: LHLD 2710H CD0827 CALL DVRT 29 DAD H 76 HLT E9 DVRT: PCHL EB XCHG C9 RET 221427 SHLD 2714H C9 RET 76 HLT PC SP HL BC Top Of Stack LHLD 2710 2703 27FF 270B 2712 XX00 CALL DVRT 2708 27FD 270B 2712 2706 PCHL 270B 27FD 270B 2712 2706 SHLD 2714 270E 27FD 270B 2712 2706 RET 2706 27FF 270B 2712 XX00 DAD H 2707 27FF 4E16 2712 XX00 HLT Addr 2700 2703 2706 2707 2708 2709 270A 270B 270E 270F Instruction

Addr 2700 2703 2708 270B 270E 2706 2707

Memory Addr:2710to2715 0B 27 64 36 F8 27 0B 27 64 36 F8 27 0B 27 64 36 F8 27 0B 27 64 36 0B 27 0B 27 64 36 0B 27 0B 27 64 36 0B 27

1. The instruction at 2700 (LHLD 2710) loads L and H with the contents of locations 2710 and 2711 respectively. As a result, HL now contains 270B. PC is updated to 2703. 2. The next instruction (at 2703) is a CALL instruction. Reading the 3 bytes of this instruction updates PC to 2706. This value is pushed on the stack. For this, SP is pre-decremented to 27FE and the high byte of PC (=27) is written to this address. The SP is pre-decremented again to 27FD and the low byte of PC (06) is written to this address. Thus

3. 4.

5.

6. 7. ii)

SP now contains 27FD. Finally, the address of label DVRT (2708) is copied to PC. The next instruction (at 2708) is PCHL. The value of HL (=270B) is copied into PC. The next instruction is therefore fetched from 270B. This is SHLD 2714. So the value of L (=0B) is written at 2714 and that of H (=27) is written at 2715. PC is updated to 270E. The instruction at 270E is RET. The value at the address pointed to by SP (27FD) is read and copied to PC (low), which now becomes 06. SP is incremented (to 27FE). The value at this address is read and copied to PC (High) which becomes 27 and SP is incremented (to 27FF). The next instruction is fetched from 2706 = which is DAD H. This doubles the value of HL to 4E16 and PC becomes 2707. The instruction at 2707 is HLT, which halts the program. -4 Addr 2700 2701 2702 2703 2705 2706 Code C5 E3 0A C636 27 76 PC 2701 2702 2703 2705 2706 2706 Label STRT: Instruction PUSH B XTHL LDAX B ADI 36H DAA HLT HL 2710 2712 2712 2712 2712 2712 BC 2712 2712 2712 2712 2712 2712 Top Of Stack 2712 2710 2710 2710 2710 2710 A X X 64 9A 00 00 Memory Addr:2710to2715 0B 27 64 36 F8 27 0B 27 64 36 F8 27 0B 27 64 36 F8 27 0B 27 64 36 F8 27 0B 27 64 36 F8 27 0B 27 64 36 F8 27

Addr 2700 2701 2702 2703 2705 2706

Instruction PUSH B XTHL LDAX B ADI 36 DAA HLT

SP 27FD 27FD 27FD 27FD 27FD 27FD

1. The program fetches the instruction at 2700 (PUSH B) and autoincrements PC to 2701. SP is pre-decremented to 27FE, and the value of B (=27) is written to this address. The SP is pre-decremented again to 27FD and the value of C (=12) is written to this address. 2. The instruction at 2701 is XTHL. This exchanges the values of HL and the Top of stack. Thus HL becomes 2712 and the top of stack becomes 2710. (i.e. The location 27FD contains 10 and 27FE contains 27). PC is incremented to 2702. 3. The next instruction (at 2702) is LDAX B. This loads A with the contents of the memory location whose address is specied by BC. BC contains 2712 and at this location we nd 64H. so A gets loaded with 64H. PC is incremented to 2703. 4. The instruction at 2703 is ADI 36H. This addition makes A = 64H + 36H = 9AH and clears carry as well as AC. PC is incremented to 2705. 5. The instruction at 2705 is DAA. The lower nibble contains A, which is > 9. Therefore 6 is added, which makes the lower nibble 0, sets AC and adds 1 to the upper nibble, making it A. The upper nibble is now A (> 9). Therefore 6 is added to it, which makes it 0 and sets carry. Thus, A=00 and carry as well as aux carry are set. PC is incremented to 2706. 6. The HLT instruction at 2706 halts the program -2

Soln. to Q3: An 8255A chip is I-O mapped and has the base address 80H. i) Write the initialization code required to put port A in mode 1 (input), port B in mode 1 (output) and port C in input mode. Using BSR mode, enable port A to cause interrupts. The CSR address is 80+3 = 83H, Port A address is 80H. The CSR should be loaded with: b7 1 1 b6-b5 Amode 01 b4 Adir 1 b3 CUdir 1 b2 Bmode 1 b1 Bdir 0 b0 CLdir = BDH 1

Port A (in mode 1: input) uses line 4 of Port C for ST B, which is the input handshake line. Therefore Port C line 4 should be set in BSR mode to enable interrupts. b7 0 0 b6-4 XXX 000 b3-1 line 100 b0 Val. =09 1

This leads to the following initialization code: Addr. 2700 2702 2704 2706 Code 3EBD D383 3E09 D383 Label Init: Instr. MVI OUT MVI OUT Comment ; Cong byte ; Write to CSR ; BSR to set PC line 4 ; Write to CSR -2 ii) Assume that the interrupt output of 8255A for port A is connected to the RST 7.5 pin of 8085. Write the required assembly code such that interrupts on RST 7.5 will be recognized by the 8085. To enable interrupts on RST 7.5, we need to do two things: RST 7.5 should be unmasked in the interrupt register and the global interrupts should be enabled. Ideally, we should leave the other interrupt settings unchanged while enabling interrupts on RST 7.5. This can be done by doing a RIM rst, adjusting the bits as needed and then doing a SIM. The RIM and SIM formats are:: bit7 SID SOD bit6 I7.5 SDE bit5 I6.5 XXX bit4 bit3 RIM I5.5 IE SIM R7.5 MSE bit2 M7.5 M7.5 bit1 M6.5 M6.5 bit0 M5.5 M5.5

A, 0BDH 83H A, 09 83H

After doing RIM, we need to make bits 7 and 6 = 0 (to disable serial IO), bit 4 = 1 (to clear the RST7.5 FF, in case it had been left set by some previous interrupt), bit 3 = 1 (to enable Mask set) and bit 2 = 0 (to unmask RST 7.5). This can be done by ANDing the RIM output with 00111011 (=3BH) and ORing it with 00011000 (=18H). So the required code is: Addr. 2708 2709 270B 270D 270E Code 20 E63B F618 30 FB Label Init: Instr. RIM ANI ORI SIM EI Comment ;Read interrupt settings ;Force b7,b6,b2 to 0 ;Force b4,b3 to 1 ;write new settings ; Enable interrupts globally

3BH 18H

-2 iii) Write the assembly code to service the RST 7.5 interrupt, such that a byte is read and stored at location 2714H every time an interrupt is caused by 8255 port A. (An interrupt service routine must ensure that all registers and ags are unchanged on return). We assume that a jump 2000 instruction is placed at 003C Addr. 2000 2001 2003 2006 2007 2008 Code F5 DB80 329A0A FB F1 C9 Label handler: Instr. PUSH IN STA EI POP RET Comment ; Save A and Flags ; Read Port A ; Store value at 2714 ; Re-enable interrupts ; Restore A and Flags -3 iv) Show the timing diagram of data transfer from the outside world through port A of 8255 to 8085 using interrupts.

PSW 80H 2714 PSW

Data (Port A) STB IBF INTE=1

INTR

RD
The external world places data on Port A and latches it in by a negative growing pulse on ST B. This causes the IBF output from 8255 to go high. When the ST B signal return high (data writing is complete) and IBF is high, and if INTEA is high, the INTRA line goes high. This causes an interrupt in the 8085. When the interrupt service routine runs, it reads port A. The low going RD signal causes INTRA line to return low. When the read cycle of 8085 completes, RD returns high, and this causes the IBF signal to return low. (This invites the external world to strobe the next data byte in). -3

Soln. to Q4: An 8085 processor uses a crystal of 2.0 MHz. Assume that the memory uses 2 wait states. Calculate the time required for the following program to run: Time taken by the HLT instruction is not to be included Addr 2700 2703 2706 2707 2708 2709 270A 270D Code 112301 CD0727 76 1B 7B B2 C20727 C9 Label Instruction LXI D, 0123H CALL Delay HLT DCX D MOV A, E ORA D JNZ Delay RET

Delay:

1. LXI involves 3 visits to memory (1 for opcode, 2 for value). This takes (3+2)*3 + 1 = 16 clock cycles. 2. CALL involves 5 visits to memory. (1 for opcode, 2 for reading the destination address and 2 for pushing PC on stack). Since a PUSH is involved, 2 extra cycles will be taken. This takes (3+2)*5 + 1 + 2 = 28 cycles. 3. The Delay loop is executed 0123H = 291 times. In the loop, (a) (b) (c) (d) DCX takes (3+2)*1 +1 +2 = 8 clock cycles. MOV A,E takes (3+2)*1 +1 = 6 clock cycles. ORA D takes (3+2)*1 + 1 = 6 clock cycles. JNZ takes (3+2)*3 + 1 = 16 clock cycles, except in the last iteration, where the jump is not to be taken. In this case, the second byte of destination address is not read, so there is one less visit to the memory, and 5 cycles are saved.

So the loop takes 291*(8+6+6+16) - 5 =10471 clock cycles. 4. RET involves 3 visits to the memory (1 for op code and 2 for popping the return address from the stack). This takes (3+2)*3+1 = 16 clock cycles. 5. Time for HLT is not to be included. Thus, in all, the execution takes 16+28+10471+16 = 10531 clock cycles. Each clock cycle takes 1 s, since the internal clock frequency is 1 MHz. (The crystal clock of 2 MHz is divided by 2 internally). Therefore the execution takes 10.531 ms in all. 5 marks Soln. to Q5: Explain (with illustrative examples), the operation of the following instructions: i) RST n This is equivalent to CALL 8n. Unlike a call, this is a single byte instruction. This is convenient for INTR type interrupts. The (updated) PC is pushed on the stack, and the value 8*n is copied to PC. For example, if the monitor code of a system begins from 1000H, we can place the instruction JMP 1000 at the location 0038. Then, a test program can terminate by RST 7, which will perform a call to location 8*7 = 56 = 0038H. At this location, the jump instruction will be executed taking us to the monitor code. ii) XTHL This single byte instruction exchanges the contents of HL with data stored at (SP +1) and SP respectively. For example, suppose the value of SP is 27FDH, HL contains 2710 and the memory locations 27FD and 27FE contain 12 and 34 respectively.

Then after the execution of XTHL, L will contain 12, H will contain 34, location 27FD will contains 10 and location 27FE will contain 27. The Stack pointer will remain unchanged at 27FD. iii) XCHG This exchanges HL with DE. If H contains 12, L contains 34, D contains 56 and E contains 78, then after the execution of XCHG, H will have 56, L will have 78, D will have 12 and E will have 34. iv) SIM SIM sets the interrupt mask and outputs serial data if enabled. the 8 bits in the accumulator are interpreted as: b7 SOD b6 SDE b5 XXX SIM b4 b3 R7.5 MSE b2 M7.5 b1 M6.5 b0 M5.5

If bit6 is 1, bit 7 is placed on the SOD pin. If bit4 is 1, the RST7.5 ip op is cleared. if bit 3 is 1 then the contents of bit2, 1 and 0 are copied to mask bits of RST7.5, RST6.5 and RST 5.5 respectively. 4 marks