0 C 0 X 1 Zzwyfc 4 WW 2 Up 4 CTDXWW 12 Yy

TL071, TL071A, TL071B, TL072 TL072A, TL072B, TL074, TL074A, TL074B LOW NOISE JFET INPUT OPERATIONAL AMPLIFIERS
SLOS080I SEPTEMBER 1978 REVISED APRIL 2004
D Low Power Consumption D Wide Common-Mode and Differential

Voltage Ranges
D Low Noise D D D D D
Vn = 18 nV/Hz Typ at f = 1 kHz High Input Impedance . . . JFET Input Stage Internal Frequency Compensation Latch-Up-Free Operation High Slew Rate . . . 13 V/s Typ Common-Mode Input Voltage Range Includes VCC+
D Low Input Bias and Offset Currents D Output Short-Circuit Protection D Low Total Harmonic Distortion
. . . 0.003% Typ
description/ordering information
The JFET-input operational amplifiers in the TL07x series are similar to the TL08x series, with low input bias and offset currents and fast slew rate. The low harmonic distortion and low noise make the TL07x series ideally suited for high-fidelity and audio preamplifier applications. Each amplifier features JFET inputs (for high input impedance) coupled with bipolar output stages integrated on a single monolithic chip. The C-suffix devices are characterized for operation from 0C to 70C. The I-suffix devices are characterized for operation from 40C to 85C. The M-suffix devices are characterized for operation over the full military temperature range of 55C to 125C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
ORDERING INFORMATION
TA VIOmax AT 25C PDIP (P) PDIP (N) PACKAGE Tube of 50 Tube of 50 Tube of 25 Tube of 75 Reel of 2500 Tube of 75 SOIC (D) 10 mV SOP (NS) SOP (PS) Reel of 2500 Tube of 50 Reel of 2500 Reel of 2000 Reel of 2000 Reel of 2000 Reel of 2000 TSSOP (PW) Tube of 90 Reel of 2000 Tube of 50 PDIP (P) PDIP (N) 0C to 70C Tube of 50 Tube of 25 Tube of 75 Reel of 2500 6 mV Tube of 75 SOIC (D) Reel of 2500 Tube of 50 Reel of 2500 SOP (PS) SOP (NS) PDIP (P) PDIP (N) Reel of 2000 Reel of 2000 Tube of 50 Tube of 50 Tube of 25 Tube of 75 Reel of 2500 3 mV SOIC (D) Tube of 75 Reel of 2500 Tube of 50 Reel of 2500 ORDERABLE PART NUMBER TL071CP TL072CP TL074CN TL071CD TL071CDR TL072CD TL072CDR TL074CD TL074CDR TL074CNSR TL071CPSR TL072CPSR TL072CPWR TL074CPW TL074CPWR TL071ACP TL072CP TL074ACN TL071ACD TL071ACDR TL072ACD TL072ACDR TL074ACD TL074ACDR TL072ACPSR TL074ACNSR TL071BCP TL072BCP TL074BCN TL071BCD TL071BCDR TL072BCD TL072BCDR TL074BCD TL074BCDR TL074BC 072BC 071BC TL074AC T072A TL074A TL071BCP TL072BCP TL074BCN 072AC 071AC T074 TL071ACP TL072CP TL074ACN TL074C TL074 TL071 T072 T072 TL072C TL071C TOP-SIDE MARKING TL071CP TL072CP TL074CN
SOP (NS) Reel of 2000 TL074BCNSR TL074B Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
DALLAS, TEXAS 75265
description/ordering information (continued)

ORDERING INFORMATION
TA VIOmax AT 25C PDIP (P) PDIP (N) PACKAGE Tube of 50 Tube of 50 Tube of 25 Tube of 75 40 C 85 C 40C to 85C 6 mV SOIC (D) Reel of 2500 Tube of 75 Reel of 2500 Tube of 50 Reel of 2500 CDIP (JG) 6 mV 55C to 125C 9 mV CFP (U) LCCC (FK) CDIP (J) CFP (W) LCCC (FK) Tube of 50 Tube of 150 Tube of 55 Tube of 25 Tube of 25 Tube of 55 ORDERABLE PART NUMBER TL071IP TL072IP TL074IN TL071ID TL071IDR TL072ID TL072IDR TL074ID TL074IDR TL072MJGB TL072MUB TL072MFKB TL074MJB TL074MWB TL074MFKB TL074I TL072MJGB TL072MUB TL072MFKB TL074MJB TL074MWB TL072I TL071I TOP-SIDE MARKING TL071IP TL072IP TL074IN
TL074MFKB Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
DALLAS, TEXAS 75265
TL071, TL071A, TL071B D, P, OR PS PACKAGE (TOP VIEW) TL072, TL072A, TL072B D, JG, P, PS, OR PW PACKAGE (TOP VIEW) TL074A, TL074B D, J, N, NS, OR PW PACKAGE TL074 . . . D, J, N, NS, PW, OR W PACKAGE (TOP VIEW)
OFFSET N1 IN IN+ VCC
1 2 3 4
8 7 6 5
NC VCC+ OUT OFFSET N2
1OUT 1IN 1IN+ VCC
1 2 3 4
8 7 6 5
VCC+ 2OUT 2IN 2IN+
TL072 U PACKAGE (TOP VIEW)
1OUT 1IN 1IN+ VCC+ 2IN+ 2IN 2OUT
1 2 3 4 5 6 7
14 13 12 11 10 9 8
4OUT 4IN 4IN+ VCC 3IN+ 3IN 3OUT
NC 1OUT 1IN 1IN+ VCC

TL071 FK PACKAGE (TOP VIEW)
1 2 3 4 5
10 9 8 7 6
NC VCC+ 2OUT 2IN 2IN+

NC OFFSET N1 NC NC NC
NC 1OUT NC V CC+ NC
NC V CC NC 2IN+ NC
NC No internal connection
symbols
TL071 OFFSET N1 IN+ IN OFFSET N2 + OUT IN IN+ TL072 (each amplifier) TL074 (each amplifier) + OUT
NC V CC NC OFFSET N2 NC
DALLAS, TEXAS 75265
2IN 2OUT NC 3OUT 3IN
NC IN NC IN+ NC
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
NC VCC+ NC OUT NC
NC 1IN NC 1IN+ NC
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
NC 2OUT NC 2IN NC
1IN+ NC VCC+ NC 2IN+
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
1IN 1OUT NC 4OUT 4IN 4IN+ NC VCC NC 3IN+
schematic (each amplifier)

VCC+
IN+ IN 64
128 OUT 64
C1 18 pF
VCC
OFFSET N1
TL071 Only
All component values shown are nominal. COMPONENT COUNT COMPONENT TYPE TL071 TL072 22 28 4 2 2 2 TL074 44 56 6 4 4 4
Resistors 11 Transistors 14 JFET 2 Diodes 1 Capacitors 1 epi-FET 1 Includes bias and trim circuitry

OFFSET N2
1080
1080
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (see Note 1): VCC+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V Input voltage, VI (see Notes 1 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Duration of output short circuit (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited Package thermal impedance, JA (see Notes 5 and 6): D package (8 pin) . . . . . . . . . . . . . . . . . . . . . . 97C/W D package (14 pin) . . . . . . . . . . . . . . . . . . . . . 86C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85C/W PS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 95C/W PW package (8 pin) . . . . . . . . . . . . . . . . . . . 149C/W PW package (14 pin) . . . . . . . . . . . . . . . . . . 113C/W U package . . . . . . . . . . . . . . . . . . . . . . . . . . . 185C/W Package thermal impedance, JC (see Notes 7 and 8): FK package . . . . . . . . . . . . . . . . . . . . . . . . . 5.61C/W J package . . . . . . . . . . . . . . . . . . . . . . . . . 15.05C/W JG package . . . . . . . . . . . . . . . . . . . . . . . . . 14.5C/W W package . . . . . . . . . . . . . . . . . . . . . . . . 14.65C/W Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: J, JG, or W package . . . . . . . . . . . . 300C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC. 2. Differential voltages are at IN+, with respect to IN. 3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less. 4. The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the dissipation rating is not exceeded. 5. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) TA)/JA. Operating at the absolute maximum TJ of 150C can affect reliability. 6. The package thermal impedance is calculated in accordance with JESD 51-7. 7. Maximum power dissipation is a function of TJ(max), JC, and TC. The maximum allowable power dissipation at any allowable case temperature is PD = (TJ(max) TC)/JC. Operating at the absolute maximum TJ of 150C can affect reliability. 8. The package thermal impedance is calculated in accordance with MIL-STD-883.
DALLAS, TEXAS 75265
electrical characteristics, VCC = 15 V (unless otherwise noted)

TEST CONDITIONS MIN 25C Full range 13 18 5 10 65 7 11 12 12 10 25 15 3 1012 70 70 100 100 75 80 25 3 1012 100 100 75 80 200 50 200 10 12 13.5 12 13.5 12 to 15 11 11 12 12 10 50 25 3 1012 100 100 75 80 200 12 to 15 7 12 to 15 13.5 200 65 200 65 2 2 200 7 11 12 12 10 50 25 3 1012 100 100 MHz dB dB 200 V/mV Full range 25C 25C VIC = VICRmin, RS = 50 VO = 0, 25C 25C VCC = 9 V to 15 V, RS = 50 VO = 0, VO = 0, AVD = 100 No load 25C 25C 12 to 15 13.5 V 65 100 5 100 5 100 18 18 7.5 5 18 5 100 2 200 20 Full range 25C VO = 0 Full range 25C VO = 0 Full range 25 C 25C RL = 10 k RL 10 k RL 2 k 25C VO = 10 V, RL 2 k Full range 25C 3 10 3 6 2 3 3 VO = 0, VO = 0, RS = 50 RS = 50 TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX 6 8 mV TA TL071C TL072C TL074C TL071AC TL072AC TL074AC TL071BC TL072BC TL074BC TL071I TL072I TL074I UNIT
PARAMETER
VIO
Input offset voltage
V IO
Temperature coefficient of input offset voltage
V/C pA nA pA nA V
IIO
Input offset current
IIB
Input bias current
VICR
Common-mode input voltage range
VOM
Maximum peak output voltage swing
AVD
Large-signal differential voltage amplification
B1
Unity-gain bandwidth
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
ri
Input resistance
CMRR
kSVR
Common-mode rejection ratio Supply-voltage rejection ratio (VCC /VIO)
ICC
Supply current (each amplifier)
1.4 120
2.5
1.4 120
2.5
1.4 120
2.5
1.4 120
2.5
mA dB
VO1/ VO2
Crosstalk attenuation
All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is TA = 0C to 70C for TL07_C,TL07_AC, TL07_BC and is TA = 40C to 85C for TL07_I. Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 4. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as possible.
electrical characteristics, VCC = 15 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN VIO V IO IIO IIB Input offset voltage Temperature coefficient of input offset voltage Input offset current Input bias current Common-mode input voltage range RL = 10 k RL 10 k RL 2 k VO = 10 V, TA = 25C TA = 25C VIC = VICRmin, RS = 50 VO = 0, VCC = 9 V to 15 V, RS = 50 VO = 0, VO = 0, No load 25C 25C 25C 80 80 RL 2 k VO = 0, VO = 0, VO = 0 VO = 0 11 12 12 10 35 15 3 1012 86 86 1.4 2.5 80 80 200 12 to 15 13.5 RS = 50 RS = 50 25C Full range Full range 25C Full range 25C 65 18 5 100 20 200 50 25C 25C Full range 25C 11 12 12 10 35 15 3 1012 86 86 1.4 2.5 200 V/mV MHz dB dB mA 12 to 15 13.5 V 65 TL071M TL072M TYP 3 MAX 6 9 18 5 100 20 200 50 MIN TL074M TYP 3 MAX 9 15 mV V/C pA nA pA nA V UNIT
VICR
VOM
Maximum peak output voltage swing Large-signal differential voltage amplification Unity-gain bandwidth Input resistance Common-mode rejection ratio Supply-voltage rejection ratio (VCC/VIO) Supply current (each amplifier)
AVD B1 ri CMRR kSVR ICC
VO1/VO2 Crosstalk attenuation AVD = 100 25C 120 120 dB Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 4. Pulse techniques must be used that will maintain the junction temperature as close to the ambient temperature as possible. All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is TA = 55C to 125C.
DALLAS, TEXAS 75265
operating characteristics, VCC = 15 V, TA = 25C

TL07xM PARAMETER SR tr Vn In THD Slew rate at unity gain Rise-time overshoot factor Equivalent input noise voltage Equivalent input noise current Total harmonic distortion TEST CONDITIONS VI = 10 V, CL = 100 pF, VI = 20 mV, CL = 100 pF, RS = 20 RS = 20 , VIrms = 6 V, RL 2 k, f = 1 kHz RL = 2 k, See Figure 1 RL = 2 k, See Figure 1 f = 1 kHz f = 10 Hz to 10 kHz f = 1 kHz AVD = 1, RS 1 k, MIN 5 TYP 13 0.1 20% 18 4 0.01 0.003 % MAX ALL OTHERS MIN 8 TYP 13 0.1 20% 18 4 0.01 nV/Hz V pA/Hz MAX UNIT V/s s
0.003%
PARAMETER MEASUREMENT INFORMATION
10 k VO + CL = 100 pF RL = 2 k VI VI
Figure 1. Unity-Gain Amplifier
Figure 2. Gain-of-10 Inverting Amplifier
TL071 OUT
IN IN+
N2 N1 100 k
1.5 k VCC
Figure 3. Input Offset-Voltage Null Circuit
DALLAS, TEXAS 75265
VO + RL CL = 100 pF 9
1 k
TYPICAL CHARACTERISTICS Table of Graphs
FIGURE IIB Input bias current vs Free-air temperature vs Frequency vs Free-air temperature vs Load resistance vs Supply voltage vs Free-air temperature vs Frequency vs Frequency vs Free-air temperature vs Free-air temperature vs Free-air temperature vs Supply voltage vs Free-air temperature vs Free-air temperature vs Free-air temperature vs Frequency vs Frequency vs Time vs Elapsed time 4 5, 6, 7 8 9 10 11 12 12 13 13 14 15 16 17 18 19 20 21 22
VOM
Maximum output voltage
AVD
Large-signal differential voltage amplification Phase shift Normalized unity-gain bandwidth Normalized phase shift
CMRR ICC PD Vn THD VO
Common-mode rejection ratio Supply current Total power dissipation Normalized slew rate Equivalent input noise voltage Total harmonic distortion Large-signal pulse response Output voltage
10
DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
INPUT BIAS CURRENT vs FREE-AIR TEMPERATURE
VOM Maximum Peak Output Voltage V VOM VCC = 15 V
MAXIMUM PEAK OUTPUT VOLTAGE vs FREQUENCY
12.5
IIIB Input Bias Current nA IB
10
7.5
0.1
2.5
0.01 75
50
25
25
50
75
100
125
0 100
1k
TA Free-Air Temperature C
Figure 4
15 VOM Maximum Peak Output Voltage V VOM VOM Maximum Peak Output Voltage V VOM VCC = 15 V RL = 2 k TA = 25C See Figure 2 15

VCC = 15 V RL = 2 k See Figure 2
12.5
12.5
TA = 25C
10
10
VCC = 10 V
7.5
7.5 TA = 125C
5 VCC = 5 V 2.5
2.5
0 100
1k
10 k 100 k f Frequency Hz
1M
10 M
0 10 k
40 k 100 k 400 k 1 M f Frequency Hz
Figure 6
Figure 7
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
DALLAS, TEXAS 75265
VCC = 10 V VCC = 5 V 10 k 100 k f Frequency Hz 1M 10 M
10

VCC = 15 V
100
15
RL = 10 k TA = 25C See Figure 2
Figure 5
TA = 55C
4M
10 M
11
MAXIMUM PEAK OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE
15 VOM VOM Maximum Peak Output Voltage V VOM Maximum Peak Output Voltage V VOM RL = 10 k 15 VCC = 15 V TA = 25C See Figure 2
MAXIMUM PEAK OUTPUT VOLTAGE vs LOAD RESISTANCE
10
7.5
VCC = 15 V See Figure 2 50 25 0 25 50 75 100 125
0 75
Figure 8
MAXIMUM PEAK OUTPUT VOLTAGE vs SUPPLY VOLTAGE

15 VOM Maximum Peak Output Voltage V VOM RL = 10 k TA = 25C AVD A VD Large-Signal Differential Voltage Amplification V/mV 1000 400 200 100 40 20 10 4 2 0 0 2 4 6 8 10 12 14 16 |VCC| Supply Voltage V
12.5
10
7.5
2.5
Figure 10
12
2.5

RL = 2 k
12.5
12.5
10
7.5
2.5
0 0.1
0.2
0.4
0.7 1
7 10
RL Load Resistance k
Figure 9
LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION vs FREE-AIR TEMPERATURE
VCC = 15 V VO = 10 V RL = 2 k 50 25 0 25 50 75 100 125
1 75
Figure 11
DALLAS, TEXAS 75265
LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT vs FREQUENCY
106 VCC = 5 V to 15 V RL = 2 k TA = 25C
AVD A VD Large-Signal Differential Voltage Amplification
105
103
Differential Voltage Amplification
45
102 Phase Shift
90
101
135
1 1 10 100 1k 10 k 100 k f Frequency Hz 1M
180 10 M
Figure 12
NORMALIZED UNITY-GAIN BANDWIDTH AND PHASE SHIFT vs FREE-AIR TEMPERATURE
1.3 1.03
Normalized Unity-Gain Bandwidth
1.2
Unity-Gain Bandwidth
1.02 Normalized Phase Shift
1.1 Phase Shift
1.01
0.9 VCC = 15 V RL = 2 k f = B1 for Phase Shift 50 25 0 25 50 75 100 TA Free-Air Temperature C
0.99
0.8
0.98
0.7 75
0.97 125
Figure 13
DALLAS, TEXAS 75265
Phase Shift
104
13
COMMON-MODE REJECTION RATIO vs FREE-AIR TEMPERATURE
89 CMRR Common-Mode Rejection Ratio dB ICC I CC Supply Current Per Amplifier mA VCC = 15 V RL = 10 k 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 |VCC| Supply Voltage V TA = 25C No Signal No Load
SUPPLY CURRENT PER AMPLIFIER vs SUPPLY VOLTAGE
88
87
86
85
83 75
50
25
25
50
75
100
125
Figure 14
SUPPLY CURRENT PER AMPLIFIER vs FREE-AIR TEMPERATURE
2 ICC I CC Supply Current Per Amplifier mA 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 75 50 25 0 25 50 75 100 125 VCC = 15 V No Signal No Load 250 PD Total Power Dissipation mW PD 225 200 175
75 50 25 0 75 50 25 0
TL071
25
Figure 16
Figure 17
14
DALLAS, TEXAS 75265
84
Figure 15
TOTAL POWER DISSIPATION vs FREE-AIR TEMPERATURE
VCC = 15 V No Signal No Load
TL074 150 125 100 TL072
50
75
100
125
NORMALIZED SLEW RATE vs FREE-AIR TEMPERATURE
1.15 VCC = 15 V RL = 2 k CL = 100 pF
EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY

VCC = 15 V AVD = 10 RS = 20 TA = 25C
Normalized Slew Rate V/ s
1.10
Vn V n Equivalent Input Noise Voltage nV/HzHz nV/
1.05
0.95
0.90
0.85 75
50
25
25
50
75
100
125
Figure 18
TOTAL HARMONIC DISTORTION vs FREQUENCY
1 THD Total Harmonic Distortion % 0.4 VI and VO Input and Output Voltages V VCC = 15 V AVD = 1 VI(RMS) = 6 V TA = 25C 0.1 0.04 6
0.01 0.004
0.001 100
400
1k 4 k 10 k f Frequency Hz
40 k 100 k
0.5 1 1.5 t Time s
Figure 20
Figure 21
DALLAS, TEXAS 75265

50 40 30 20 10 0 10 4 2 0 2
40 100
400 1 k 4 k 10 k f Frequency Hz
40 k 100 k
Figure 19
VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE

VCC = 15 V RL = 2 k CL = 100 pF TA = 25C
Output
Input
2.5
3.5
15
OUTPUT VOLTAGE vs ELAPSED TIME
28 24 Overshoot VO VO Output Voltage mV 20 90% 16 12 8 4 10% tr 0 0.1 0 VCC = 15 V RL = 2 k TA = 25C 0.6 0.7
16
4 0.2 0.3 0.4 0.5 t Elapsed Time s
Figure 22
DALLAS, TEXAS 75265
APPLICATION INFORMATION
Table of Application Diagrams
APPLICATION DIAGRAM 0.5-Hz square-wave oscillator High-Q notch filter Audio-distribution amplifier 100-kHz quadrature oscillator AC amplifier RF = 100 k VCC+ 3.3 k 15 V Output Input R1 C3 1 k R3 3.3 k 9.1 k f+ 1 2p R F C F C1 C2 R2 TL071 + CF = 3.3 F 15 V TL071 + Output VCC R1 + R2 + 2R3 + 1.5 MW C1 + C2 + C3 + 110 pF 2 1 fO + + 1 kHz 2p R1 C1 PART NUMBER TL071 TL071 TL074 TL072 TL071 FIGURE 23 24 25 26 27
Figure 23. 0.5-Hz Square-Wave Oscillator
Figure 24. High-Q Notch Filter
VCC+ 1 M VCC+ TL074 + VCC TL074 + VCC+ TL074 + Output B VCC+ VCC VCC+ 100 k TL074 + Output C VCC Output A
1 F Input
100 k
VCC 100 k 100 k
100 F
Figure 25. Audio-Distribution Amplifier
DALLAS, TEXAS 75265
17
APPLICATION INFORMATION
6 sin t 18 pF 18 pF VCC+ 88.4 k VCC+ 6 cos t 1 k VCC 15 V 1N4148 18 k (see Note A) 1 k 1N4148 18 k (see Note A) 15 V
TL072 88.4 k 18 pF + VCC 88.4 k 0.1 F 10 k 10 k IN 50 IN+ 0.1 F 10 k + N1

TL072 +
NOTE A: These resistor values may be adjusted for a symmetrical output.
Figure 26. 100-kHz Quadrature Oscillator

VCC+
1 M TL071 N2 OUT
100 k
Figure 27. AC Amplifier
18
DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM

www.ti.com
7-Mar-2005
PACKAGING INFORMATION
Orderable Device 8102304HA 81023052A 8102305HA 8102305PA 81023062A 8102306CA 8102306DA JM38510/11905BPA JM38510/11906BCA TL071ACD TL071ACDR TL071ACP TL071BCD TL071BCDR TL071BCP TL071CD TL071CDR TL071CP TL071CPSR TL071CPWLE TL071ID TL071IDR TL071IJG TL071IP TL071MFKB TL071MJG TL071MJGB TL072ACD TL072ACDR TL072ACJG TL072ACP Status (1) OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE OBSOLETE ACTIVE OBSOLETE OBSOLETE OBSOLETE ACTIVE ACTIVE OBSOLETE ACTIVE LCCC CFP CDIP LCCC CDIP CFP CDIP CDIP SOIC SOIC PDIP SOIC SOIC PDIP SOIC SOIC PDIP SO TSSOP SOIC SOIC CDIP PDIP LCCC CDIP CDIP SOIC SOIC CDIP PDIP FK U JG FK J W JG J D D P D D P D D P PS PW D D JG P FK JG JG D D JG P Package Type Package Drawing Pins Package Eco Plan (2) Qty 10 20 10 8 20 14 14 8 14 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 20 8 8 8 8 8 8 50 75 2500 50 75 2500 75 2500 50 75 2500 50 75 2500 50 2000 1 1 1 1 1 1 1 None None None None None None None None None Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) None Pb-Free (RoHS) Pb-Free (RoHS) None Pb-Free (RoHS) None None None Pb-Free (RoHS) Pb-Free (RoHS) None Pb-Free (RoHS) Lead/Ball Finish Call TI A42 SNPB A42 SNPB A42 SNPB A42 SNPB A42 SNPB Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI CU NIPDAU CU NIPDAU Call TI CU NIPDAU Call TI Call TI Call TI CU NIPDAU CU NIPDAU Call TI CU NIPDAU MSL Peak Temp (3) Call TI Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Call TI Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-NC-NC-NC Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-NC-NC-NC Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-NC-NC-NC Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Call TI Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Call TI Level-NC-NC-NC Call TI Call TI Call TI Level-2-250C-1 YEAR Level-2-250C-1 YEAR Call TI Level-NC-NC-NC
POST-PLATE Level-NC-NC-NC
POST-PLATE Level-NC-NC-NC
Addendum-Page 1

www.ti.com
7-Mar-2005
Orderable Device TL072ACPSR TL072BCD TL072BCDR TL072BCP TL072CD TL072CDR TL072CP TL072CPSLE TL072CPSR TL072CPWR TL072ID TL072IDR TL072IP TL072MFKB TL072MJG TL072MJGB TL072MUB TL074ACD TL074ACDR TL074ACJ TL074ACN TL074ACNSR TL074BCD TL074BCDR TL074BCN TL074BCNSR TL074CD TL074CDR
Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type SO SOIC SOIC PDIP SOIC SOIC PDIP SO SO TSSOP SOIC SOIC PDIP LCCC CDIP CDIP CFP SOIC SOIC CDIP PDIP SO SOIC SOIC PDIP SO SOIC SOIC
Package Drawing PS D D P D D P PS PS PW D D P FK JG JG U D D J N NS D D N NS D D
Pins Package Eco Plan (2) Qty 8 8 8 8 8 8 8 8 8 8 8 8 8 20 8 8 10 14 14 14 14 14 14 14 14 14 14 14 25 2000 50 2500 25 2000 50 2500 2000 2000 75 2500 50 1 1 1 1 50 2500 2000 75 2500 50 75 Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS)
Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU
MSL Peak Temp (3) Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-250C-1 YEAR Level-2-250C-1 YEAR Level-NC-NC-NC Level-2-250C-1 YEAR Level-1-260C-UNLIM Level-NC-NC-NC Call TI Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-1-250C-UNLIM Level-2-250C-1 YEAR Level-2-250C-1 YEAR Level-NC-NC-NC
2500 Green (RoHS & no Sb/Br) 50 Pb-Free (RoHS) None Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) None None None None Pb-Free (RoHS) Pb-Free (RoHS) None Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS)
POST-PLATE Level-NC-NC-NC A42 SNPB A42 SNPB A42 SNPB CU NIPDAU CU NIPDAU Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-2-250C-1 YEAR Level-2-250C-1 YEAR Call TI Level-NC-NC-NC Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-250C-1 YEAR Level-2-250C-1 YEAR Level-NC-NC-NC Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-250C-1 YEAR Level-2-250C-1 YEAR
Addendum-Page 2

www.ti.com
7-Mar-2005
Orderable Device TL074CN TL074CNSR TL074CPW TL074CPWLE TL074CPWR TL074ID TL074IDR TL074IJ TL074IN TL074MFK TL074MFKB TL074MJ TL074MJB TL074MWB
(1)
Status (1) ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type PDIP SO TSSOP TSSOP TSSOP SOIC SOIC CDIP PDIP LCCC LCCC CDIP CDIP CFP
Package Drawing N NS PW PW PW D D J N FK FK J J W
Pins Package Eco Plan (2) Qty 14 14 14 14 14 14 14 14 14 20 20 14 14 14 25 1 1 1 1 1 2000 50 2500 25 2000 90 Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) None Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) None Pb-Free (RoHS) None None None None None
Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU Call TI CU NIPDAU CU NIPDAU CU NIPDAU Call TI CU NIPDAU
MSL Peak Temp (3) Level-NC-NC-NC Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-1-250C-UNLIM Call TI Level-1-250C-UNLIM Level-2-250C-1 YEAR Level-2-250C-1 YEAR Call TI Level-NC-NC-NC
POST-PLATE Level-NC-NC-NC POST-PLATE Level-NC-NC-NC A42 SNPB A42 SNPB A42 SNPB Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
MECHANICAL DATA
MCER001A JANUARY 1995 REVISED JANUARY 1997
JG (R-GDIP-T8)
0.400 (10,16) 0.355 (9,00) 8 5
CERAMIC DUAL-IN-LINE
0.280 (7,11) 0.245 (6,22)
4 0.065 (1,65) 0.045 (1,14)
0.063 (1,60) 0.015 (0,38)
0.020 (0,51) MIN
0.310 (7,87) 0.290 (7,37)
0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN
0.023 (0,58) 0.015 (0,38) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20)
015
4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T8
DALLAS, TEXAS 75265
MECHANICAL DATA
MCFP001A JANUARY 1995 REVISED DECEMBER 1995
U (S-GDFP-F10)
CERAMIC DUAL FLATPACK
0.045 (1,14) 0.026 (0,66)
0.250 (6,35) 0.246 (6,10)
Base and Seating Plane
0.080 (2,03) 0.050 (1,27) 0.300 (7,62) MAX 1 10
0.008 (0,20) 0.004 (0,10)
0.019 (0,48) 0.015 (0,38)
0.050 (1,27) 0.280 (7,11) 0.230 (5,84)
6 4 Places 0.005 (0,13) MIN
0.350 (8,89) 0.250 (6,35)
0.350 (8,89) 0.250 (6,35) 4040179 / B 03/95
NOTES: A. B. C. D. E.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only. Falls within MIL STD 1835 GDFP1-F10 and JEDEC MO-092AA
DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B OCTOBER 1996
FK (S-CQCC-N**)
28 TERMINAL SHOWN
LEADLESS CERAMIC CHIP CARRIER
18
17
16
15
14
13
12
NO. OF TERMINALS ** 11 10 28 9 8 7 6 68 5 84 44 52 20
A MIN 0.342 (8,69) 0.442 (11,23) 0.640 (16,26) 0.739 (18,78) 0.938 (23,83) 1.141 (28,99) MAX 0.358 (9,09) 0.458 (11,63) 0.660 (16,76) 0.761 (19,32) 0.962 (24,43) 1.165 (29,59) MIN 0.307 (7,80) 0.406 (10,31) 0.495 (12,58) 0.495 (12,58) 0.850 (21,6) 1.047 (26,6)
B MAX 0.358 (9,09) 0.458 (11,63) 0.560 (14,22) 0.560 (14,22) 0.858 (21,8) 1.063 (27,0)
19 20 21 B SQ 22 A SQ 23 24 25
26
27
28
4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25)
0.020 (0,51) 0.010 (0,25)
0.055 (1,40) 0.045 (1,14)
0.045 (1,14) 0.035 (0,89)
0.028 (0,71) 0.022 (0,54) 0.050 (1,27)
0.045 (1,14) 0.035 (0,89)
4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004
DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI001A JANUARY 1995 REVISED JUNE 1999
P (R-PDIP-T8)
0.400 (10,60) 0.355 (9,02) 8 5
PLASTIC DUAL-IN-LINE
0.260 (6,60) 0.240 (6,10)
4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.010 (0,25) NOM Gage Plane
0.020 (0,51) MIN
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M
0.430 (10,92) MAX
4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
PW (R-PDSO-G**)
14 PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65 14 8
0,30 0,19
0,10 M
0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0 8 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
14
16
20
24
28
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TIs terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TIs standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2005, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless
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TL071, TL071A, TL071B, TL072 TL072A, TL072B, TL074, TL074A, TL074B LOW NOISE JFET INPUT OPERATIONAL AMPLIFIERS

SLOS080I SEPTEMBER 1978 REVISED APRIL 2004

D Low Power Consumption D Wide Common-Mode and Differential

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SLOS080I SEPTEMBER 1978 REVISED APRIL 2004

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

description/ordering information (continued)

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SLOS080I SEPTEMBER 1978 REVISED APRIL 2004

OFFSET N1 IN IN+ VCC

NC VCC+ OUT OFFSET N2

1OUT 1IN 1IN+ VCC

VCC+ 2OUT 2IN 2IN+

TL072 U PACKAGE (TOP VIEW)

1OUT 1IN 1IN+ VCC+ 2IN+ 2IN 2OUT

4OUT 4IN 4IN+ VCC 3IN+ 3IN 3OUT

NC 1OUT 1IN 1IN+ VCC

NC VCC+ 2OUT 2IN 2IN+

TL072 FK PACKAGE (TOP VIEW)

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

2IN 2OUT NC 3OUT 3IN

1IN+ NC VCC+ NC 2IN+

1IN 1OUT NC 4OUT 4IN 4IN+ NC VCC NC 3IN+

schematic (each amplifier)

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SLOS080I SEPTEMBER 1978 REVISED APRIL 2004

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

electrical characteristics, VCC = 15 V (unless otherwise noted)

Input offset voltage

Temperature coefficient of input offset voltage

Input offset current

Input bias current

Common-mode input voltage range

Maximum peak output voltage swing

Large-signal differential voltage amplification

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

Common-mode rejection ratio Supply-voltage rejection ratio (VCC /VIO)

Supply current (each amplifier)

SLOS080I SEPTEMBER 1978 REVISED APRIL 2004

AVD B1 ri CMRR kSVR ICC

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operating characteristics, VCC = 15 V, TA = 25C

PARAMETER MEASUREMENT INFORMATION

Figure 1. Unity-Gain Amplifier

Figure 2. Gain-of-10 Inverting Amplifier

Figure 3. Input Offset-Voltage Null Circuit

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SLOS080I SEPTEMBER 1978 REVISED APRIL 2004

Maximum output voltage

CMRR ICC PD Vn THD VO

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MAXIMUM PEAK OUTPUT VOLTAGE vs FREQUENCY

IIIB Input Bias Current nA IB