LabVIEW FPGA Implementation Of a PID Controller

For D.C. Motor Speed Control

Fakhrulddin H. Ali
Computer Engineering Dept.
College of Engineering
University of Mosul
Mosul-Iraq
fhali310@yahoo.com
Mohammed Mahmood Hussein
Computer Engineering Dept.
College of Engineering
University of Mosul
Mosul-Iraq
mohmah86@gmail.com
Sinan M.B. Ismael
Computer and Information Eng. Dept.
College of Electronics Engineering
University of Mosul
Mosul-Iraq
eng_sinan85@yahoo.com
Abstract This Paper presents a novel hardware design
methodology of digital control systems. For this, instead of
synthesizing the control system using Very high speed
integration circuit Hardware Description Language (VHDL),
LabVIEW FPGA module from National Instrument (NI) is used
to design the whole system that include analog capture circuit to
take out the analog signals (set point and process variable) from
the real world, PID controller module, and PWM signal
generator module to drive the motor. The physical
implementation of the digital system is based on Spartan-3E
FPGA from Xilinx. Simulation studies of speed control of a D.C.
motor are conducted and the effect of a sudden change in
reference speed and load are also included.
Keywords PID Controller, LabVIEW FPGA, Speed Control,
Spartan-3E, PWM.
I. INTRODUCTION
The development of PID (Proportional-Integral-
Derivative) control theories has already 60 years so far, PID
control has been one of the control system design method of
the longest history. However, this method is still extensively
used now [1, 2]. PID-controller and its modifications are the
most common controllers in the industry. It is robust and
simple to design, its operation is well known, it has a good
noise tolerance, it is inexpensive and it is commercially
available [2].
The design and development of PID controller is
habitually supported by simulation tools Matlab simulink and
LabVIEW control design and simulation toolkit, for instance,
once the controller is modeled its physical implementation can
be directly carried out in software such as microprocessor, and
microcontroller [3, 4] or hardware such as FPGA[5].
The FPGA is a superior alternative to mask programmed
ASICs. FPGAs avoid the high initial cost, the lengthy
development cycles, and the inherent inflexibility of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs[6].
The FPGA based system allows designers to create digital
designs, test them, make modification very easily , and reduce
development time greatly [7]. Digital designs can be modeled
using hardware description languages like Very high speed
integrated circuit Hardware Description Language (VHDL)
and verified by simulation.
In this paper, simulation studies of a PID controller for
D.C. motor speed control are conducted. Then, the hardware
implementation of a PID module (The PID module is
composed of several sub-modules including ADC module, a
PWM generation module, and a PID calculation module) is
designed using LabVIEW FPGA module and downloaded on
the Xilinx Spartan-3E board.
The National Instruments LabVIEW FPGA Module uses
LabVIEW Embedded technology to extend LabVIEW
graphical development to target FPGAs on NI reconfigurable
I/O (RIO) hardware or Xilinx Spartan-3E board. With the
LabVIEW FPGA Module, users can: create custom hardware
without VHDL coding or board design, Execute multiple tasks
simultaneously and deterministically, and solve many
applications, including unique timing and triggering routines,
ultra high-speed control, interfacing to digital protocols,
digital signal processing (DSP), and any other application
requiring high-speed hardware reliability and tight
determinism.
II. PID CONTROLLER
PID control, shown in fig. 1, is one of the earlier control
strategies . Its early implementation was in pneumatic devices,
followed by vacuum and solid state analog electronics, before
arriving at todays digital implementation via microprocessors
or FPGA. It has a simple control structure which was
understood by plant operators which they found relatively
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easy to tune. Since many control systems using PID control
have proved its satisfactory performance, it still has a wide
range of applications in industrial control [8] and it has been
an active research topic for many years.
Figure 1. Closed loop PID Controller
The general transfer function of the PID controller looks
like the following:

(1)
K
p
= Proportional gain
K
i
= Integral gain
K
d
= Derivative gain
The variable (e) represents the tracking error This error
signal is sent to the PID controller, and the controller
computes both the derivative and the integral of the error
signal. This signal (u) is sent to the plant, and the new output
(y) will be obtained. This new output (y) will be sent back to
the sensor again to find the new error signal (e). The controller
takes this new error signal and computes its derivative and
integral again, this process goes on and on until the error
signal (e) equals zero [9].
III. HARDWARE DESIGN AND IMPLEMENTATION
The hardware implementation of the controller has been
done by LabVIEW FPGA and downloaded into XC3S500E
FPGA from Xilinx. The Spartan-3E family of Field-
Programmable Gate Arrays (FPGAs) is specifically designed
to meet the needs of high volume, cost-sensitive consumer
electronic applications. The five-member family offers
densities ranging from 100,000 to 1.6 million system gates [6].
The XC3S500E FPGA has 4,656 slices, almost 10,476 logic
cells, twenty 18x18 hardware multipliers, as well as twenty
18Kbits modules of dedicated dual-port RAM. The block
diagram of the whole system is illustrated in fig. 2.
Figure 2. Block Diagram of the complete system implemented on Spartan-
3E kit
A. Analog capture circuit
The connection of a digital controller to a real world
requires ADC (Analogue to Digital Converter). The Spartan-
3E board includes a two-channel analog capture circuit,
consisting of a programmable scaling pre-amplifier and an
ADC. Both are serially programmed or controlled by the
FPGA [10]. The analog capture circuit converts the analog
voltage on VINA or VINB to a 14-bit digital representation,
D[13:0], as expressed by Eq. 2.

(2)
The Programmable Pre-Amplifier provides two
independent inverting amplifiers with a programmable gain.
The purpose of the amplifier is to scale the incoming voltage
on VINA or VINB so that it maximizes the conversion range
of the DAC, namely 1.65 1.25V. The GAIN is the current
setting loaded into the programmable pre-amplifier. The
various allowable settings for GAIN and allowable voltages
applied to the VINA and VINB inputs appear in Table I.
TABLE I. PROGRAMMABLE GAIN SETTINGS FOR PRE-AMPLIFIER
Gain
A3 A2 A1 A0 Input voltage range
B3 B2 B1 B0 Minimum Maximum
0 0 0 0 0
-1 0 0 0 1 0.4 2.9
-2 0 0 1 0 1.025 2.275
-5 0 0 1 1 1.4 1.9
-10 0 1 0 0 1.525 1.775
-20 0 1 0 1 1.5875 1.7125
-50 0 1 1 0 1.625 1.675
-100 0 1 1 1 1.6375 1.6625
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The reference voltage for the amplifier and the ADC is
1.65V. Consequently, the maximum range of the ADC is
1.25V, centered around the reference voltage 1.65V.
The FPGA uses a Serial Peripheral Interface (SPI) to
communicate with devices on the board. The SPI bus is a full-
duplex, synchronous, character-oriented channel employing a
simple four-wire interface. Since the SPI bus signals are
shared by other devices on the board, it is vital that other
devices are disabled when the FPGA communicates with the
amplifier or ADC to avoid bus contention. Table II provides
the signals and logic values required to disable the devices.
TABLE II. DISABLED DEVICES ON THE SPI BUS
Signal Disabled Device Disable Value
SPI_SS_B SPI Serial Flash 1
AMP_CS Programmable Pre-Amplifier 1
DAC_CS
Digital-to-Analog Converter
(DAC)
1
SF_CE0
StrataFlash Parallel Flash
PROM
1
FPGA_INIT_B Platform Flash PROM 1
AD_CONV
Analog-to-Digital Converter
(ADC)
0
The analog capture circuit is design with a flat sequence
structure. At the beginning all devices are disabled except
Programmable Pre-Amplifier. Then, pre-amplifier is disabled,
AD_CONV signal goes High, and ADC simultaneously
samples both analog channels.
B. PID (FPGA) Module
The PID block implements a fixed-point PID algorithm
for PID applications with high-speed control and/or high
channel count on an FPGA target. This Express VI can be
used with single-channel or multi-channel configurations. The
PID algorithm features control action range and uses an
integrator anti-windup calculation to limit the effect of the
integral action during transients. The PID algorithm also
features bumpless controller output for PID gain changes. Fig.
3 illustrates the block diagram of this module where:
x Value A represents the process variable which
specifies the value of the wanted variable to be
controlled. This value is represented by a fixed-point
number with a maximum word length of 16bit.
x Value B represents the set point which specifies the
value that the process variable to attain. This value is
represented by a fixed-point number with a maximum
word length of 16bit. This input is available only for
single-channel configurations, that is, when number of
channels is 1, The value wired to this input overrides
the value of initial set point in the configuration dialog
box.
x PID gains specifies the normalized PID gain
parameters.
x Output range specifies the allowable range of the
output.
x PWM High Time presents the control action (PWM
signal high time) that the PID algorithm calculates.
Figure 3. PID(FPGA) module block diagram
This Express VI represents the PID proportional, integral,
and derivative gains as signed fixed-point numbers with word
length 16bit and integer word length 8bit. Given the
Proportional gain (K
c
), Integral time (T
i
), and Derivative time
(T
d
), respectively, this Express VI normalizes these gains
according to the following formulas [11]:

(3)

(4)
K
u

K
c
T
u

T
s
(5)
where T
s
is the sampling time T
s
(s) at which the PID loop
runs.
This express VI calculates the output, u(k), according to
the following equation:
uk u
p
k u
i
k u
u
k
where
u
p
k K
p
ek
u
i
k K
p
K
i

ei ei

k
i

u
u
k K
p
K
u
Pvk Pvk
ek setpointk Pvk
PV(k) = value of process variable on the kth call after
initialization.
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C. PWM Generator Module
D.C. motor speed can be controlled by varying the power
applied to the armature, PWM is very well known method do
this task. In PWM technique, power is regulated by applying
pulses of variable width by changing the pulse width of the
power. With the pulse width small, the average voltage
applied onto the motor is low, and the motor's speed is slow. If
the width is wide, the average voltage is higher, and therefore
motor speed is higher [12, 13].
Fig. 4 shows PWM signal with 50% duty cycle, where T is
the signal period, V
H
is the signal amplitude. The average
output voltage in this case is 0.5 * V
H
. In general, the output
voltage will be:

(11)
Where, V
avg
is the average output voltage and D is a duty
cycle. From this equation the average voltage is linearly
related to the duty cycle. On the other hand, the period is fixed
as illustrated in fig. 5.
Figure 4. PWM signal with 50% duty cycle
Figure 5. Pulse width determines average voltage with fixed period
Fig. 6 shows LabVIEW block diagram that generate PWM
signal with different duty cycles dependent on PID control
signal and eduction this signal through one of the FPGA I/O
pins.
Figure 6. PWM signal generation block diagram
Table III shows FPGA logic resources used to implement
the complete control unit represented by analog capture
circuit, PID(FPGA) module, PWM generator module.
TABLE III. DEVICE UTILIZATION SUMMARY FOR A CONTROL UNIT
Device Type Percentage area occupied
Number of Slices 1473 out of 4656 31%
Number of Slice Flip Flops 1683 out of 9312 18%
Number of 4 input LUTs 2234 out of 9312 23%
Number of bonded IOBs 106 out of 232 45%
Number of MULT18X18SIOs 3 out of 20 15%
Number of GCLKs 2 out of 24 8%
Maximum Frequency 51.509MHz
IV. SIMULATION RESULTS
Simulation of a PID control action is applied upon the
armature of the D.C. motor. The equivalent circuit is
illustrated in fig. 7.
Figure 7. Armature controlled D.C. motor equivalent circuit
Equations 12 through 15 consider that the applied voltage
e
a
(t) is the cause, Eq. 12 considers that di
a
(t)/dt is the
immediate effect due to e
a
(t), in Eq. 13, i
a
(t) causes the torque
T
m
(t), Eq. 14 defines the back emf (electromotive force); and,
finally, in Eq. 15, the torque T
m
(t) produces the angular
velocity
m
(t). Fig. 8 shows the block diagram representing
the D.C. motor system [14].
Figure 8. diagram of a D.C. motor system
ui
a
t
ut


L
a
e
a
t
R
a
L
a
i
a
t

L
a
e
b
t
T
m
t K
i
i
a
t
e
b
t K
b

m
t
u

m
t
ut

}
m
T
L
t
B
m
}
m

u
m
t
ut

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The motor parameter values used in this paper are listed in
table IV. The PID controller parameters are K
p
=7, K
i
= 65, and
K
d
=0.08.
TABLE IV. D.C. MOTOR PARAMETERS
Value Measuring
units
descriptions Parameters
0.5 Nm/A torque constant

5
armature
resistance

0.1 H
armature
inductance

0.001 kg-m2
Armature
moment of
inertia

Negligible N-m/rad/sec
viscous-friction
coefficient

1.356Ki V/rad/sec Speed constant

To demonstrate the system performance, a sudden change

in reference speed is introduced. The response is illustrated in
fig. 9. Initially, the reference speed is 700 rpm, then increased
to 1400 rpm, and finally set back to 700 rpm. The control
performance parameters for the step response and sudden
change of speed reference are summarized in table V.
Figure 9. System response to the sudden change of speed reference
TABLE V. RESPONSE PARAMETERS FOR THE SUDDEN CHANGE OF
SPEED REFERENCE
Reference
(rpm)
OS
(%)
tr
(sec)
US
(%)
tf
(sec)
ts
(sec)
700
To 1400
6.56 0.02 0.26
1400
To 700
6.59 0.02 0.26
Fig 10 and 11 shows the system response when a load is
applied and released during a constant motor speed of 700 rpm
and 1400 rpm respectively. The load applied is 5 N.m. Table
VI and VII summarize the overshoot, drop speed, and rise
speed when load is applied and released respectively.
Figure 10. System response to sudden change of load at 700 rpm constant
speed
Figure 11. System response to sudden change of load at 1400 rpm constant
speed
TABLE VI. RESPONSE PARAMETERS WHEN 5 N-M LOAD APPLIED
Reference
(rpm)
Drop
(rpm)
tdrop
(sec)
OS
(%)
tos
(sec)
ts
(sec)
700 117.46 0.006 6.59 0.062 0.21
1400 114.79 0.007 3.55 0.052 0.17
TABLE VII. RESPONSE PARAMETERS WHEN 5 N-M LOAD RELEASED
Reference
(rpm)
Rise
(rpm)
trise
(sec)
ts
(sec)
700 118.26 0.006 0.21
1400 114.81 0.007 0.16
Finally, it is assumed that the reference speed and the
motor load are changing at the same time. The system
response is depicted in fig. 12 and its parameters are
summarized in table VIII.
TABLE VIII. RESPONSE PARAMETERS FOR THE SUDDEN CHANGE OF
SPEED REFERENCE AND LOAD
Reference
(rpm)
Load
(N.m)
OS
(%)
Drop or
Rise
(rpm)
tdrop or
trise
(sec)
ts
(sec)
700
To 1400
Zero
To 50
1.77 88.06 0.0004 0.16
1400
To 700
50
To Zero
1.84 88.11 0.0004 0.16
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Figure 12. System response to the sudden change of speed reference and
load
V. CONCLUSION
In this paper, a hardware digital controller is designed
using LabVIEW program. LabVIEW is a graphical
programming language used not only for data acquisition and
measurement but also for designing digital systems on FPGA
targets without prior knowledge of hardware description
language. The block diagram of a LabVIEW FPGA VI can
represent the parallelism and timing of embedded systems
much better than text-based languages. At present, the system
maximum operating frequency is (51.509MHz) this could take
advantage of the high speed achievable using hardware. The
design of PID controller based on FPGA allows their future
utilization to use this controller for other application.
Simulation results shows that the controller is provide stability
and minimum overshoot in response to sudden change in
reference speed and load.
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