ECE253 - Digital and Computer Systems University of Toronto Fall 2010

Lab 3 Addition and Binary-to-Decimal Conversion

The purpose of this laboratory is to gain familiarity with the most basic form of computation - addition - in digital circuits. In addition, we will work with a representation know as binary-coded-decimal (BCD), which is a way of representing the individual base 10 digits in a binary form. Part I The purpose of this part is to have the DE2 switches set to encode numbers that are then displayed on the 7 segment HEX displays. This part is similar, but not the same as parts 4 and 5 of Lab #2. We wish to display on the 7-segment displays HEX3 to HEX0 the numbers dened by the settings of switches SW150 . Your circuit will display the numbers denoted by SW1512 , SW118 , SW74 and SW30 on the displays HEX3, HEX2, HEX1 and HEX0, respectively. Your circuit should be able to display the digits from 0 to 9, and should treat the input valuations of the switches 1010 to 1111 as dont-cares. Each circuit that drives the HEX display is called a 7segment decoder, as it was in Lab 2, but here we are using a different code. Perform the following steps: 1. Design a circuit using Verilog that will display the state of the switches on the 7-segment displays, as explained above. 2. Create a new Quartus II project for your circuit. Select the Cyclone II EP2C35F672C6 as the target chip, as before. 3. Make the pin assignments by importing the DE2 pin assignments.csv le as you did in Lab 2. 4. Compile the project. 5. Examine the resulting circuit using the RTL Viewer. 6. Download the compiled circuit into the FPGA chip. 7. Test the functionality of your design by setting the switches and observing the displays. Prior to the lab, test your circuit using the Quartus simulator. These simulations will form part of your marked preparation. Part II You are to design a circuit that converts a four-bit binary number V = v3 v2 v1 v0 into its two-digit decimal equivalent D = d1 d0 . Table 1 below shows the required conversion. A partial design of this circuit is given in Figure 1. It includes a comparator that checks when the value of V is greater than 9, and uses the output of this comparator in the control of the 7-segment displays. You are to complete the design of this circuit. Perform the following steps: 1. Make a new Quartus II project. 2. Design a circuit using a Verilog module which includes the comparator, multiplexers, and circuit A (do not include circuit B or the 7-segment decoder at this point). 1

3. Compile the circuit and use functional simulation to verify the correct operation of your comparator, multiplexers, and circuit A. 4. Augment your Verilog circuit to include circuit B in Figure 1 as well as the 7-segment decoder. Change the inputs and outputs of your code to use switches SW30 on the DE2 board to represent the binary number V , and the displays HEX1 and HEX0 to show the values of decimal digits d1 and d0 . Make sure to include in your project the required pin assignments for the DE2 board. Again, test this circuit and make sure it works using functional simulation. 5. Recompile the project, and then download the circuit into the FPGA chip. 6. Test your circuit by trying all possible values of V and observing the output displays. Binary value v3 v2 v1 v0 0000 0001 0010 ... 1001 1010 1011 1100 1101 1110 1111 Decimal digits d1 d0 00 01 02 ... 09 10 11 12 13 14 15

Table 1. Binary-to-decimal conversion.

d1 z Comparator Circuit B v3 0
0 1 7

0 5 4 3 d0 6 1 2

m3

v2

0 1

m2 7-segment decoder
7

0 5 4 3 6 1 2

v1

0 1

m1

v0

0 1

m0

Circuit A

Figure 1. Partial design of the binary-to-decimal conversion circuit. Part III Figure 2a shows a circuit for a full adder, as discussed in class, which has the inputs a, b, and ci , and produces the outputs s and co . Figures 2b and 2c show a circuit symbol and truth table for the full adder, which produces the two-bit binary sum co s = a + b + ci . Figure 2d reviews how four instances of this full adder can be used to implement a ripple-carry adder which adds 2 four-bit numbers. Implement this circuit as described below.
ci a b s ci a
0

s FA co

co
1

a) Full adder circuit

b3 a3 c 3

b) Full adder symbol

b2 a2 c 2 b1 a1 c 1 b 0 a 0 c in

b a ci 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

co s 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1

FA

FA

FA

FA

c out s 3

s2

s1

s0

c) Full adder truth table

d) Four-bit ripple-carry adder circuit

Figure 2. A ripple-carry adder.

Perform the following: 1. Create a new Quartus II project. 2. Design a circuit using a Verilog module for the full adder subcircuit and write a top-level Verilog module that instantiates four instances of this full adder. Use switches SW74 and SW30 to represent the inputs A and B, respectively. Use SW8 for the carry-in cin of the adder. Connect the SW switches to their corresponding red lights LEDR, and connect the outputs of the adder, cout and S = (s3 , s2 , s1 , s0 ), to the green lights LEDG. 3. Add the Verilog le to the project and include the necessary pin assignments. 4. Make your circuit correct by testing (and xing it if necessary) using functional simulation. 5. Compile the circuit, and download it into the FPGA chip. 6. Test your circuit by trying different values for numbers A, B, and cin . Part IV In part II we discussed the conversion of binary numbers into decimal digits. It is sometimes useful to build 3

circuits that use this method of representing decimal numbers, in which each decimal digit is represented using four bits. This scheme is known as the binary coded decimal (BCD) representation. As an example, the decimal value 59 is encoded in BCD form as 0101 1001. You are to design a circuit that adds two BCD digits, which is different from the straight-up 8-bit adder described in class. The inputs to the circuit are BCD numbers A and B, plus a carry-in, cin . The output should be a two-digit BCD sum S1 S0 , which has to be displayed on the 7-segment displays. Note that the largest sum that needs to be handled by this circuit is S1 S0 = 9 + 9 + 1 = 19. Perform the following: 1. Create a new Quartus II project for your BCD adder. 2. Design a circuit using Verilog as specied. You should use the four-bit adder circuit from part III to produce a four-bit sum and carry-out for the operation A + B. A circuit that converts this ve-bit result, which has the maximum value 19, into two BCD digits S1 S0 can be designed in a similar way as the binary-to-decimal converter from part II. In your design, you should: Use switches SW74 and SW30 for the inputs A and B, respectively, and use SW8 for the carry-in. Connect the SW switches to their corresponding red lights LEDR, and connect the four-bit sum and carry-out produced by the operation A + B to the green lights LEDG. Display the BCD values of A and B on the 7-segment displays HEX6 and HEX4, and display the result S1 S0 on HEX1 and HEX0. Draw a block diagram of your circuit before you write the Verilog code. 3. Include the necessary pin assignments for the DE2 board, and test and correct your circuit using functional simulation. 4. Compile the circuit, and download it into the FPGA chip. 5. Test your circuit by trying different values for numbers A, B, and cin . Part V Design a circuit that can add 2 two-digit BCD numbers, A1 A0 and B1 B0 to produce the three-digit BCD sum S2 S1 S0 . Use two instances of your circuit from part IV, which may have to be slightly modied, to build this two-digit BCD adder. Perform the following steps: 1. Use switches SW158 and SW70 to represent 2-digit BCD numbers A1 A0 and B1 B0 , respectively. The value of A1 A0 should be displayed on the 7-segment displays HEX7 and HEX6, while B1 B0 should be on HEX5 and HEX4. Display the BCD sum, S2 S1 S0 , on the 7-segment displays HEX2, HEX1 and HEX0. 2. Make the necessary pin assignments and test and correct the circuit using functional simulation. 3. In the lab, compile the circuit, download it into the FPGA chip, and test its operation.

Preparation and Performance Your preparation has to include the following: 1. Verilog code for circuits in Parts I, II, III, IV and V (0.5 mark each) 2. Simulation for the circuits in Parts I, II, III, IV and V (0.5 mark each)

In the lab you have to demonstrate to your TA the operation of circuits for Parts I to V (1 mark each). 4