Thespecificnumbersofabovemeasurementsde pendonthebenchmarkschosenandthe compilertechnologyused.

Althoughwefeelthat ourmeasurementsarereasonablyindicativeof theusageofthetwoarchitectures,otherprogra msordifferentcompilersmayyieldslightly differentnumbers.Butwebelievewhatwedoh eretoIntel80386andMIPSR2000primarily displaysthemostcommondifferencesbetweent hetwoarchitecturesbehindthem. 4.Discussions 4.1Whowins? RISCprocessorsgainareputationforhighperfo rmance,andourexperimentsabovedoverify thispoint.However,nowadays,thedifferencebet weenRISCandCISCchipsisgettingsmaller andsmaller.RISCandCISCarchitecturesareb ecomingmoreandmorealike.Manyoftoday's RISCchipssupportjustasmanyinstructionsas yesterday'sCISCchips.ThePowerPC601,for example,supportsmoreinstructionsthanthePen tium.Yetthe601isconsideredaRISCchip, whilethePentiumisdefinitelyCISC.Furthermor etoday'sCISCchipsusemanytechniques formerlyassociatedwithRISCchips.Heremaybe wecansimplysaythatRISCandCISCare growingtoeachotherintheirarchitectureinthe theoreticalpointofview. Inreality,whatcountsishowfastachipcane xecutetheinstructionsitisgivenandhowwelli

t runsexistingsoftware.yetmostdeal withshrinkingtime-tomarketrequirements.mostnewgen erationsofprocessorsemployamixedbagof architecturalfeatures.Thi sallhappenedquicklyand .Today.forcingdownthe priceofthe486.Thereisaproblemofensuringqualitysoft waredevelopmenttoolsareavailable.andfloating-point integration.The typicalhighendembeddedproductthesedaysincorporatesc omplexsoftware.ManyofthenewerRI SCprocessorscannotyetofferatools environmentcomparablewithx86offerings.includingmultipleexecution units.caches.In90's.Thisnecessitatesaproducti vesoftware developmentenvironment.Intelrapidl yloweredPentiumprices.Inan efforttoacceleratetheintroductionof5th generationprocessorsonthedesktop.pipelining.Consequentlyhighperformance 486processors-costingmulti-millionsof dollarstodevelopbecameavailableatveryaggressiveprices. Makingaprocessorsuccessfulismorethanjust havingthefastestchipavailableatanattractive price.bothRISCandCI SCmanufacturersaredoingeverythingtogetan edgeonthecompetition.thusmakesperformancecomparisons almostuselessoutsideofaspecific application.

evenifthebattlelinesarenow becomingfuzzy.whowins?Noone wins.So.When chooseaprocessorforembeddedrealtimeapplication. Butthe futuremightnotbringvictorytooneofthem.Also.and manyotherlow-costRISCprocessorsarenot goingtoeasilygainasignificantperformancead vantageoverfutureimplementationofthex86 architecture.Embeddedproductdesignersarego odatidentifyingwherethebestvalueis.Inanembeddedsystem.EPICstands .sincemostofrealtimesystemsrequireveryfastinterrupthandling andhighcode density.RISCgenerallydon'thaveadva ntages overCISC. CISCchipssuchasMotorola's68Kfamily providebettersoftwareavailabilityforsuchsyste m. ItseemslikelythatthePowerPC.[5] ThedebatebetweenRISCandCISCwilllikelyc ontinue.itisunlikelytohavelarge memory.bu tmakesbothextinct. Finally.CISCba ttlefield.nomatterwh atyourRISCorCISCpersuasion[1].wewanttopointoutthatthebiggestthr eatforCISCandRISCmightnotbeeachother .duetothesiz elimitationofchips. butanewtechnologycalledEPIC.Thisseemsclear.sohighcodedensityisimportant.thei960.changedthelandscapeoftheRISCvs.

AllofthebigC PUmanufacturesbutSunandMotorolaarenow sellingx86basedproducts. EPICisacreatedbyIntelandisinawayac ombinationofbothCISCandRISC.itappearsthattheoretically .forExplicitlyParallelInstructionComputing. SothefuturemightbringEPICprocessorsand moreCISCprocessors.Likethenamesays. EPICmightmakefirstRISCobsoleteandlater CISCtoo. IfIntel'sEPICarchitectureissuccessful.Becauseofthex8 6marketitisnotlikelythatCISCwilldiesoon.whiletheRISC processorsarebecomingextinct. LikethewordparallelalreadysaysEPICcando manyinstructionexecutionsinparalleltoone another.SGI).Mercedwill bea64-bitchip.Microsoftisalreadydevelopingthe irWin64 standardforit.Thiswillin theoryallowtheprocessingofWindowsbasedaswellasUNIXbasedapplicationsbythesame CPU. Andfinally. butRISCmay.2Summary Fromourlimitedexperiencebasedontheresults ofourbenchmarks. IntelisworkingonitundercodenameMerced. 4.andsomearejustwaitingforMe rcedtocomeout(HP.itmight bethebiggestthreadforRISC.

Millerforhisexcellentteaching.peopleonlycareabouthowwellasyste m canservethem.inreal world.howfastachipcanexecuteth einstructionsitisgivenandhowwellitruns existingsoftware.however. Withtimefleeting.thebottomline betweenCISCandRISCbecomesblur. Acknowledgements Wewouldliketoexpressoursinceregratitudet oDr. References [1]DanielMann. timelyhelpandsupport.andenlighteningdiscuss ion.from .EthanL.Also.Wethinktheadoptionofeach other’stechnologytoovercomeitsown drawbacksmaybemoreandmoreatrendinfut ureCPUdesign.otherarchitectures differentfromCISCandRISCmayappear.thepureRISCmachinesuchasMIPSR2000is amorepromisingstyleofcomputerdesign comparedtoIntel80386CISCChipatthatera."Whythex86CISCbeatRISC" .

"HistoryofthePowerPCar chitecture".R.inf.htm [2]KeithDiefendorff.de/lehre/WS94/RA/RISC9.Patterson.In ProceedingsoftheSymposiumonArchitectural SupportforProgrammingLanguagesandOperati ngSystems(March1982).html [8]MargaritaEsponda. [5]DennisTerry.“RISCvs.pp."The801Minicomputer".com/pcmag/pctech/content/14/18/tu 1418.25-33.25 yearsoftheinternationalsymposiaonComputer .D.“ReducedInstructionSet Computers”.ACM28.1994).amdembedded.G.1(Jan. pp.Commun.Patterson.Commun."Thecasefo rthereducedinstructionsetcomputer". Pages8-21 [7]JeffProsise.CarloH.1980).“TheRISC Concept-ASurveyofImplementations”.CISC:TheRealStory --WhatmakesthePowerPCaRISCprocessor andthePentiumaCISC?“.“RISCI :AReducedInstructionSetVLSIComputer”.15.ACM37.html [6]DavidA.html [9]DavidA."ChoosingaProcessorforEmb eddedReal-TimeApplications". ComputerArchitectureNews8:6(Oct.1985).http://www. Pages28-33 [3]Radin.com/cp/html/choosingproc.zdnet.from http://www.S.Ra'ulRojas.D.from http://www.Sequin.zytec.6(Jun.fu-berlin.from http://www.andDitzel.001.39-47 [4]Patterson.com/Benchmarks/whyx86.

architecture(selectedpapers).Gross.BarcelonaSpain.June27July2.1998.Pages216-230 [10]ThomasR.Przybylski. “MeasurementandevaluationoftheMIPSarchite ctureandprocessor”.JohnL.Volume6.Pages229-257 .Steve nA.Issue3 (1988).ChristopherRowen.Hennessy.