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Thespecificnumbersofabovemeasurementsde pendonthebenchmarkschosenandthe compilertechnologyused.

Althoughwefeelthat ourmeasurementsarereasonablyindicativeof theusageofthetwoarchitectures,otherprogra msordifferentcompilersmayyieldslightly differentnumbers.Butwebelievewhatwedoh eretoIntel80386andMIPSR2000primarily displaysthemostcommondifferencesbetweent hetwoarchitecturesbehindthem. 4.Discussions 4.1Whowins? RISCprocessorsgainareputationforhighperfo rmance,andourexperimentsabovedoverify thispoint.However,nowadays,thedifferencebet weenRISCandCISCchipsisgettingsmaller andsmaller.RISCandCISCarchitecturesareb ecomingmoreandmorealike.Manyoftoday's RISCchipssupportjustasmanyinstructionsas yesterday'sCISCchips.ThePowerPC601,for example,supportsmoreinstructionsthanthePen tium.Yetthe601isconsideredaRISCchip, whilethePentiumisdefinitelyCISC.Furthermor etoday'sCISCchipsusemanytechniques formerlyassociatedwithRISCchips.Heremaybe wecansimplysaythatRISCandCISCare growingtoeachotherintheirarchitectureinthe theoreticalpointofview. Inreality,whatcountsishowfastachipcane xecutetheinstructionsitisgivenandhowwelli

Inan efforttoacceleratetheintroductionof5th generationprocessorsonthedesktop.Thisnecessitatesaproducti vesoftware developmentenvironment.pipelining.andfloating-point integration.ManyofthenewerRI SCprocessorscannotyetofferatools environmentcomparablewithx86offerings.Intelrapidl yloweredPentiumprices.mostnewgen erationsofprocessorsemployamixedbagof architecturalfeatures.thusmakesperformancecomparisons almostuselessoutsideofaspecific application.includingmultipleexecution units.Thereisaproblemofensuringqualitysoft waredevelopmenttoolsareavailable.Thi sallhappenedquicklyand .yetmostdeal withshrinkingtime-tomarketrequirements.The typicalhighendembeddedproductthesedaysincorporatesc omplexsoftware.Consequentlyhighperformance 486processors-costingmulti-millionsof dollarstodevelopbecameavailableatveryaggressiveprices.Today.caches.In90's. Makingaprocessorsuccessfulismorethanjust havingthefastestchipavailableatanattractive price.t runsexistingsoftware.forcingdownthe priceofthe486.bothRISCandCI SCmanufacturersaredoingeverythingtogetan edgeonthecompetition.

and manyotherlow-costRISCprocessorsarenot goingtoeasilygainasignificantperformancead vantageoverfutureimplementationofthex86 architecture.sohighcodedensityisimportant.Inanembeddedsystem. butanewtechnologycalledEPIC.Embeddedproductdesignersarego odatidentifyingwherethebestvalueis. Butthe futuremightnotbringvictorytooneofthem.EPICstands .changedthelandscapeoftheRISCvs.sincemostofrealtimesystemsrequireveryfastinterrupthandling andhighcode density.nomatterwh atyourRISCorCISCpersuasion[1].[5] ThedebatebetweenRISCandCISCwilllikelyc ontinue.So.bu tmakesbothextinct.Also. CISCchipssuchasMotorola's68Kfamily providebettersoftwareavailabilityforsuchsyste m.thei960.wewanttopointoutthatthebiggestthr eatforCISCandRISCmightnotbeeachother .Thisseemsclear. ItseemslikelythatthePowerPC.CISCba ttlefield. Finally.duetothesiz elimitationofchips.whowins?Noone wins.evenifthebattlelinesarenow becomingfuzzy.When chooseaprocessorforembeddedrealtimeapplication.itisunlikelytohavelarge memory.RISCgenerallydon'thaveadva ntages overCISC.

Thiswillin theoryallowtheprocessingofWindowsbasedaswellasUNIXbasedapplicationsbythesame CPU.SGI).Likethenamesays. EPICisacreatedbyIntelandisinawayac ombinationofbothCISCandRISC. IntelisworkingonitundercodenameMerced.Becauseofthex8 6marketitisnotlikelythatCISCwilldiesoon. SothefuturemightbringEPICprocessorsand moreCISCprocessors.whiletheRISC processorsarebecomingextinct.itmight bethebiggestthreadforRISC.Microsoftisalreadydevelopingthe irWin64 standardforit. EPICmightmakefirstRISCobsoleteandlater CISCtoo.itappearsthattheoretically . 4.2Summary Fromourlimitedexperiencebasedontheresults ofourbenchmarks. IfIntel'sEPICarchitectureissuccessful.forExplicitlyParallelInstructionComputing.AllofthebigC PUmanufacturesbutSunandMotorolaarenow sellingx86basedproducts. Andfinally.andsomearejustwaitingforMe rcedtocomeout(HP. LikethewordparallelalreadysaysEPICcando manyinstructionexecutionsinparalleltoone another. butRISCmay.Mercedwill bea64-bitchip.

andenlighteningdiscuss ion.from . Acknowledgements Wewouldliketoexpressoursinceregratitudet oDr.Also.thebottomline betweenCISCandRISCbecomesblur.Wethinktheadoptionofeach other’stechnologytoovercomeitsown drawbacksmaybemoreandmoreatrendinfut ureCPUdesign.peopleonlycareabouthowwellasyste m canservethem.otherarchitectures differentfromCISCandRISCmayappear."Whythex86CISCbeatRISC" .inreal world. timelyhelpandsupport.Millerforhisexcellentteaching.however.howfastachipcanexecuteth einstructionsitisgivenandhowwellitruns existingsoftware. References [1]DanielMann. Withtimefleeting.thepureRISCmachinesuchasMIPSR2000is amorepromisingstyleofcomputerdesign comparedtoIntel80386CISCChipatthatera.EthanL.

1(Jan. ComputerArchitectureNews8:6(Oct.from http://www.Ra'ulRojas.Commun.15.CarloH.CISC:TheRealStory --WhatmakesthePowerPCaRISCprocessor andthePentiumaCISC?“.andDitzel.de/lehre/WS94/RA/RISC9.“RISCI :AReducedInstructionSetVLSIComputer”."HistoryofthePowerPCar chitecture".http://www. pp.html [8]MargaritaEsponda.S.25-33."The801Minicomputer".D.1980).com/Benchmarks/whyx86.6(Jun.com/pcmag/pctech/content/14/18/tu 1418.“RISCvs.In ProceedingsoftheSymposiumonArchitectural SupportforProgrammingLanguagesandOperati ngSystems(March1982). [5]DennisTerry.fu-berlin.zdnet.25 yearsoftheinternationalsymposiaonComputer .Patterson.html [6]DavidA.htm [2]KeithDiefendorff.from http://www.ACM28.pp. Pages8-21 [7]JeffProsise.G.Commun.“ReducedInstructionSet Computers”.“TheRISC Concept-ASurveyofImplementations”. Pages28-33 [3]Radin."Thecasefo rthereducedinstructionsetcomputer".html [9]DavidA.1994).Sequin.39-47 [4]Patterson."ChoosingaProcessorforEmb eddedReal-TimeApplications".Patterson.D.inf.ACM37.R.amdembedded.com/cp/html/choosingproc.from http://www.001.1985).zytec.

“MeasurementandevaluationoftheMIPSarchite ctureandprocessor”.1998.ChristopherRowen.Przybylski.architecture(selectedpapers).Pages229-257 .Steve nA.JohnL.Hennessy.Issue3 (1988).Pages216-230 [10]ThomasR.BarcelonaSpain.June27July2.Volume6.Gross.