Thespecificnumbersofabovemeasurementsde pendonthebenchmarkschosenandthe compilertechnologyused.

Althoughwefeelthat ourmeasurementsarereasonablyindicativeof theusageofthetwoarchitectures,otherprogra msordifferentcompilersmayyieldslightly differentnumbers.Butwebelievewhatwedoh eretoIntel80386andMIPSR2000primarily displaysthemostcommondifferencesbetweent hetwoarchitecturesbehindthem. 4.Discussions 4.1Whowins? RISCprocessorsgainareputationforhighperfo rmance,andourexperimentsabovedoverify thispoint.However,nowadays,thedifferencebet weenRISCandCISCchipsisgettingsmaller andsmaller.RISCandCISCarchitecturesareb ecomingmoreandmorealike.Manyoftoday's RISCchipssupportjustasmanyinstructionsas yesterday'sCISCchips.ThePowerPC601,for example,supportsmoreinstructionsthanthePen tium.Yetthe601isconsideredaRISCchip, whilethePentiumisdefinitelyCISC.Furthermor etoday'sCISCchipsusemanytechniques formerlyassociatedwithRISCchips.Heremaybe wecansimplysaythatRISCandCISCare growingtoeachotherintheirarchitectureinthe theoreticalpointofview. Inreality,whatcountsishowfastachipcane xecutetheinstructionsitisgivenandhowwelli

pipelining.ManyofthenewerRI SCprocessorscannotyetofferatools environmentcomparablewithx86offerings.andfloating-point integration.The typicalhighendembeddedproductthesedaysincorporatesc omplexsoftware.Inan efforttoacceleratetheintroductionof5th generationprocessorsonthedesktop.t runsexistingsoftware.bothRISCandCI SCmanufacturersaredoingeverythingtogetan edgeonthecompetition.caches. Makingaprocessorsuccessfulismorethanjust havingthefastestchipavailableatanattractive price.forcingdownthe priceofthe486.Thisnecessitatesaproducti vesoftware developmentenvironment.yetmostdeal withshrinkingtime-tomarketrequirements.Thereisaproblemofensuringqualitysoft waredevelopmenttoolsareavailable.Intelrapidl yloweredPentiumprices.mostnewgen erationsofprocessorsemployamixedbagof architecturalfeatures.In90's.includingmultipleexecution units.Thi sallhappenedquicklyand .thusmakesperformancecomparisons almostuselessoutsideofaspecific application.Consequentlyhighperformance 486processors-costingmulti-millionsof dollarstodevelopbecameavailableatveryaggressiveprices.Today.

Finally.nomatterwh atyourRISCorCISCpersuasion[1].Embeddedproductdesignersarego odatidentifyingwherethebestvalueis.duetothesiz elimitationofchips.itisunlikelytohavelarge memory.bu tmakesbothextinct. Butthe futuremightnotbringvictorytooneofthem. ItseemslikelythatthePowerPC.CISCba ttlefield.Thisseemsclear.So.sohighcodedensityisimportant.Also.When chooseaprocessorforembeddedrealtimeapplication.[5] ThedebatebetweenRISCandCISCwilllikelyc ontinue. butanewtechnologycalledEPIC.thei960.RISCgenerallydon'thaveadva ntages overCISC. CISCchipssuchasMotorola's68Kfamily providebettersoftwareavailabilityforsuchsyste m.Inanembeddedsystem.changedthelandscapeoftheRISCvs.sincemostofrealtimesystemsrequireveryfastinterrupthandling andhighcode density.and manyotherlow-costRISCprocessorsarenot goingtoeasilygainasignificantperformancead vantageoverfutureimplementationofthex86 architecture.wewanttopointoutthatthebiggestthr eatforCISCandRISCmightnotbeeachother .EPICstands .evenifthebattlelinesarenow becomingfuzzy.whowins?Noone wins.

SothefuturemightbringEPICprocessorsand moreCISCprocessors.Likethenamesays.andsomearejustwaitingforMe rcedtocomeout(HP. butRISCmay. EPICisacreatedbyIntelandisinawayac ombinationofbothCISCandRISC. IfIntel'sEPICarchitectureissuccessful.Becauseofthex8 6marketitisnotlikelythatCISCwilldiesoon. 4.Thiswillin theoryallowtheprocessingofWindowsbasedaswellasUNIXbasedapplicationsbythesame CPU.SGI). LikethewordparallelalreadysaysEPICcando manyinstructionexecutionsinparalleltoone another.AllofthebigC PUmanufacturesbutSunandMotorolaarenow sellingx86basedproducts.itappearsthattheoretically . EPICmightmakefirstRISCobsoleteandlater CISCtoo.2Summary Fromourlimitedexperiencebasedontheresults ofourbenchmarks. Andfinally.forExplicitlyParallelInstructionComputing.Mercedwill bea64-bitchip.itmight bethebiggestthreadforRISC.Microsoftisalreadydevelopingthe irWin64 standardforit.whiletheRISC processorsarebecomingextinct. IntelisworkingonitundercodenameMerced.

otherarchitectures differentfromCISCandRISCmayappear.andenlighteningdiscuss ion.inreal world.however.Wethinktheadoptionofeach other’stechnologytoovercomeitsown drawbacksmaybemoreandmoreatrendinfut ureCPUdesign.thepureRISCmachinesuchasMIPSR2000is amorepromisingstyleofcomputerdesign comparedtoIntel80386CISCChipatthatera.Millerforhisexcellentteaching.howfastachipcanexecuteth einstructionsitisgivenandhowwellitruns existingsoftware.peopleonlycareabouthowwellasyste m canservethem. Withtimefleeting. Acknowledgements Wewouldliketoexpressoursinceregratitudet oDr.from ."Whythex86CISCbeatRISC" .thebottomline betweenCISCandRISCbecomesblur.Also. timelyhelpandsupport.EthanL. References [1]DanielMann.

from http://www.Ra'ulRojas.htm [2]KeithDiefendorff.D.001.1985).inf.“ReducedInstructionSet Computers”. pp. Pages8-21 [7]JeffProsise.com/pcmag/pctech/content/14/18/tu 1418.com/cp/html/choosingproc.CarloH.html [6]DavidA.html [9]DavidA.1994).In ProceedingsoftheSymposiumonArchitectural SupportforProgrammingLanguagesandOperati ngSystems(March1982). [5]DennisTerry.com/Benchmarks/whyx86.D.25 yearsoftheinternationalsymposiaonComputer .1980).html [8]MargaritaEsponda.15.zytec.Patterson.ACM28."The801Minicomputer".pp.Commun.Commun."Thecasefo rthereducedinstructionsetcomputer"."HistoryofthePowerPCar chitecture".amdembedded.6(Jun.de/lehre/WS94/RA/RISC9.http://www.S.andDitzel.zdnet. Pages28-33 [3]Radin.from http://www.“RISCvs.fu-berlin.1(Jan.39-47 [4]Patterson.G. ComputerArchitectureNews8:6(Oct.R.25-33.Sequin.“TheRISC Concept-ASurveyofImplementations”."ChoosingaProcessorforEmb eddedReal-TimeApplications".from http://www.Patterson.“RISCI :AReducedInstructionSetVLSIComputer”.CISC:TheRealStory --WhatmakesthePowerPCaRISCprocessor andthePentiumaCISC?“.ACM37.

Steve nA.BarcelonaSpain.architecture(selectedpapers).JohnL.Hennessy.Issue3 (1988).Pages216-230 [10]ThomasR. “MeasurementandevaluationoftheMIPSarchite ctureandprocessor”.June27July2.Przybylski.Pages229-257 .1998.Volume6.Gross.ChristopherRowen.