CXD3152AR

Signal Processor LSI for Single-chip CCD B/W Camera

Description The CXD3152AR is a digital signal processor LSI for CCD black-and-white cameras. In addition to the CDS and AGC circuits of conventional analog signal processor LSI, this chip also features the ease of use and functions of digital signal processing. Features Supports 510H/760H system CCD image sensors Supports EIA/CCIR modes Built-in CDS and AGC circuits Built-in 10-bit A/D converter Built-in 9-bit D/A converter Analog and digital signal output Right/left inverted (mirror image) output function Horizontal and vertical aperture correction function Gamma correction curve variable function Serial communication function (I2C bus) Supports external sync functions (when using the CXD2463R) Line lock/Vreset HPLL Supports backlight compensation functions (when using the CXD2463R) Character input pin Blemish detection and compensation function Absolute Maximum Ratings Supply voltage VDD (3.3V) VSS 0.3 to +4.6 V VDD (5.0V) VSS 0.3 to +6.0 V Input voltage VI (3.3V) VSS 0.3 to VDD3 + 0.3 V VI (5.0V) VSS 0.3 to VDD5 + 0.3 V Output voltage VO (3.3V) VSS 0.3 to VDD3 + 0.3 V VO (5.0V) VSS 0.3 to VDD5 + 0.3 V Operating temperature Topr 20 to +75 C Storage temperature Tstg 55 to +125 C Recommended Operating Conditions Supply voltage VDD (3.3V) 3.0 to 3.6 VDD (5.0V) 4.75 to 5.25 64 pin LQFP (Plastic)

Applications Various CCD black-and-white cameras Applicable CCD Image Sensors 510H system CCDs (Type 1/3, 1/4 EIA/CCIR) 760H system CCDs (Type 1/2, 1/3, 1/4 EIA/CCIR) Supported Related LSIs TG : CXD2463R EEPROM : S-24C01B (Seiko Instruments Co., Ltd.) or equivalent product

Applicable CCD Image Sensors are applicable products as of preparing this data sheet. They may be changed according to the version up and production stop of CCD image sensor.

V V

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

E03551B46

Block Diagram

SHP SHD

2MCKI

CCD, EIA

BLCW1, 2 AGC, DGC

CSYNC_IN

SDA, SCL, REGRES

Y0 to Y7

63, 62

55 58, 57 60, 61, 25, 26

59

41, 42, 40

44 to 48, 50 to 52

37, 33, 34

9bit DAC

PREF, CVREF, COMP

CDS Register

CAP1, CAPA2

3, 4

Timing Generator

Sync Separator

GAIN

CCDIN

39, 38

ANA, ANAB

Over Sampling CSYNC

IRISOUT AGC Controller

AMP

DAC Blemish Detector HV AP. Con

REFH, REFL

REFHIN, REFLIN

MONITOR

MIRROR

CHARA

2
CLP Blemish Correction AMP 3H Memory 15, 16 27 54

WC SW PED BLK

GOUT 64

AGC

YOUT

YIN

CLP

10bit ADC

CAPB2

Gamma

Y. Gain

V. follower

GAIN

10

13, 14

CXD3152AR

CXD3152AR

Description of Functions by Block CDS & AGC CDS VDD1 = 5.0V SHD/SHP external input: <SHD/SHP> Brightness signal output for iris detection: <IRISOUT> AGC VDD2 = 5.0V AGC gain variable range: 6 to 19dB (typ.) The gain is controlled by the 8-bit DAC for DC voltage generation. Manual setting possible by the register A/D Converter ADC 10 bits VDD3 = 3.3V The input block clamp circuit pulse is generated internally, and external input is impossible. Built-in voltage follower for the reference voltage Digital Signal Processing DGC DGC (digital gain control) operates at the maximum AGC (analog gain control) gain. The gain can be controlled from 0 to approximately 8 times. The aperture signal coring level is automatically controlled in conjunction with the gain. MIRROR Right/left inverted output possible <MIRROR> APCON Horizontal and vertical aperture correction circuit The circuit can be turned on and off by the setting pin. <APCON> Fine adjustment possible by the register The position at which the aperture correction signal is added can be switched to before or after gamma. Gamma correction 4 patterns can be selected by the setting pins. <GAMMA1, GAMMA2> 7-line approximation Adjustable by the register Oversampling Sampling frequency selectable from 2MCKI or (2MCKI/2) PED Standard setting: 7.5 IRE Adjustable by the register Character input A 1-bit signal from an external pin can be added to the luminance signal. <CHARA> The gain can be set by the register. Blemish detection and compensation function Up to a total of 10 white point blemishes can be detected and compensated during dark signal. Blemish addresses can be read out by serial communication. Digital output 8-bit digital signal output 3

CXD3152AR

D/A Converter DAC 9 bits VDD6 = 3.3V Supports 40 to +130 IRE output Timing Generation Timing Generation of various DSP internal signal processing pulses Input clock frequencies: EIA (510 492) : 19.06993MHz CCIR (500 582) : 18.9375MHz EIA (768 494) : 28.63636MHz CCIR (752 582) : 28.375MHz Slave operation according to the sync signal <CSYNC_IN> from an external TG: Composite sync input Gain Control Built-in auto gain control circuit The maximum AGC (analog gain control) and DGC (digital gain control) gains can be set individually by the registers. AGC and DGC can be turned on and off individually by external pins. <AGC, DGC> The gain control time constants can be set by the registers. Supports backlight compensation Registers I2C bus Various register settings: <SCL, SDA, REGRES> Slave address: [A6:A0] = 0011111 (b) Related pins: <SCL, SDA, REGRES> External EEPROM An EEPROM which supports the I2C bus can be connected. Register values can be automatically read out during power-on.

CXD3152AR

Pin Configuration

VDD6 (3.3V)

REGRES

48 VSS7 49 Y5 50 Y6 51 Y7 52 MCKO 53 CHARA 54 2MCKI 55 VDD7 (3.3V) 56 EIA 57 CCD 58 CSYNC_IN 59 BLCW1 60 BLCW2 61 SHD 62 SHP 63 GOUT 64 1 VDD1 (5V)

47

46

45

44

43

42

41

40

39

38

37

36

35

VSS6

34

33 32 VSS5 31 MCKPHS 30 GAMMA2 29 GAMMA1 28 APCON 27 MIRROR 26 DGC 25 AGC 24 VDD5 (3.3V) 23 DEFECT 22 TEST 21 VSS4 20 VDD4 (3.3V) 19 REFBIAS 18 VDD3 (3.3V) 17 VSS3

2 CCDIN

3 CAP1

4 CAPA2

5 IRISOUT

6 YOUT

7 YIN

8 CAPB2

9 VSS1

10 MONITOR

11 VSS2

12 VDD2 (5V)

13 REFHIN

14 REFLIN

15 REFH

16 REFL

CVREF

COMP

ANAB

RREF

OEB

SDA

ANA

SCL

Y4

Y3

Y2

Y1

Y0

CXD3152AR

Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symbol VDD1 CCDIN CAP1 CAPA2 IRISOUT YOUT YIN CAPB2 VSS1 MONITOR VSS2 VDD2 REFHIN REFLIN REFH REFL VSS3 VDD3 REFBIAS VDD4 VSS4 TEST DEFECT VDD5 AGC DGC MIRROR APCON GAMMA1 GAMMA2 I/O P I O(A) O(A) Analog power supply (5.0V) Image signal input from CCD CDS DC bias output Connect to GND via an approximately 0.1F capacitor. Gain control amplifier DC bias output Connect to GND via an approximately 0.1F capacitor. Description

O(A) Image signal output for iris detection O(A) AGC image signal output I(A) I(A) P Image signal input to ADC Normally input YOUT via an approximately 0.1F capacitor. ADC input clamp level (DC) input High reference (REFHIN) reference level Analog GND

O(A) Output for monitoring the signal input to ADC P P I(A) I(A) O(A) O(A) P P O(A) P P I I P I I I I I I Analog GND Analog power supply (5.0V) ADC high reference input ADC low reference input ADC high reference output Connect to GND via an approximately 0.1F capacitor. ADC low reference output Connect to GND via an approximately 0.1F capacitor. Analog GND Analog power supply (3.3V) ADC DC bias output Connect to GND via an approximately 0.1F capacitor. Digital power supply (3.3V) Digital GND Test pin. Normally fix high. Blemish compensation function switching 0: Off, 1: On Digital power supply (3.3V) Analog gain switching 0: Fixed, 1: Auto Digital gain switching 0: Fixed, 1: Auto Mirror inversion switching 0: Standard, 1: Mirror Aperture correction switching 0: Off, 1: On Gamma correction characteristics switching 00: 0.45, 01: 0.6 (register setting), 10: 1.0, 11: S curve 6

CXD3152AR

Pin No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Symbol MCKPHS VSS5 CVREF COMP VSS6 VDD6 (3.3V) RREF ANAB ANA REGRES SDA SCL OEB Y0 Y1 Y2 Y3 Y4 VSS7 Y5 Y6 Y7 MCKO CHARA 2MCKI VDD7 EIA CCD CSYNC_IN BLCW1 BLCW2 SHD

I/O I P O(A) 2MCKI input polarity switching 0: Through, 1: Inverted Digital GND DAC reference voltage output Connect to GND via 0.1F.

Description

O(A) DAC phase compensation. Connect to GND via 0.1F. P P O(A) Digital GND Digital power supply (3.3V) DAC reference voltage generation Normally connect to GND via 3.3k.

O(A) DAC negative output. Normally connect to GND via 200. O(A) DAC positive output. Normally connect to GND via 200. I Register reset. All registers reset to the default when low. I2C bus data line I/O I/O I O O O O O P O O O O I I P I I I I I I I2C bus clock line Digital output (Y0 to Y7) control. 0: Output, 1: Hi-Z Digital signal output (LSB) Digital signal output Digital signal output Digital signal output Digital signal output Digital GND Digital signal output Digital signal output Digital signal output (MSB) Y0 to Y7 latch clock output Character signal input Reference clock input Digital power supply (3.3V) TV mode switching 0: EIA, 1: CCIR CCD number of horizontal pixels switching 0: 510H system, 1: 760H system Composite sync input Backlight compensation window switching 00: Full-screen photometry, 01: Bottom photometry 10: Center photometry, 11: Bottom + center photometry Data block sampling pulse input 7

CXD3152AR

Pin No. 63 64

Symbol SHP GOUT

I/O I O(A)

Description Precharge block sampling pulse input AGC gain control voltage output (DAC output) Connect to GND via an approximately 0.1F capacitor.

Note 1) Asterisks () indicate that either 3.3V or 5.0V input is possible. Note 2) The I/O column symbol meanings are as follows. I : Digital input O : Digital output I/O : Digital input/output I(A) : Analog input O(A) : Analog output P : Power supply/GND

CXD3152AR

Logic Block Electrical Characteristics DC Characteristics 3.3V Block Item Input high level voltage Input low level voltage Input high level voltage Input low level voltage Output low level voltage Output high level voltage Output low level voltage Input leak current Output leak current Symbol VIH VIL VIH VIL VOL VOH VOL IIL IOZ Conditions CMOS supported Min. 0.7VDD 0.75VDD VDD 0.8 10 10 Typ. (VDD = 3.0 to 3.6V, VSS = 0V) Max. 0.2VDD 0.15VDD 0.4 0.4 +10 +10 Unit V V V V V V V A A Applicable pins 1 2, 4 4 3 1, 2, 4 3, 4

CMOS Schmitt supported IOL = 4mA IOH = 4mA IOL = 4mA VI = VDD, VSS At high impedance output

Note 1) The applicable pins correspond to the following symbols. 1 AGC, APCON, BLCW1, BLCW2, CCD, CHARA, MCKPHS, CSYNC_IN, DEFECT, DGC, EIA, GAMMA1, GAMMA2, 2MCKI, MIRROR, TEST, OEB (input) 2 REGRES 3 MCKO, Y0 to Y7 (output) 4 SCL, SDA (I/O) Note 2) The ANA, ANAB, COMP, CVREF, REFBIAS, REFH, REFL and RREF pins are not included in the DC characteristics.

5.0V Block Item Input high level voltage Input low level voltage Input leak current Symbol VIH VIL IIL Conditions CMOS supported VI = VDD, VSS Min. 0.7VDD 10

(VDD = 4.75 to 5.25V, VSS = 0V) Typ. Max. 0.3VDD +10 Unit V V A Applicable pins 5 5

Note 1) The applicable pins correspond to the following symbols. 5 SHD, SHP (input) Note 2) The CAP1, CAPA2, CAPB2, CCDIN, REFHIN, REFLIN, YIN, GOUT, IRISOUT, MONITOR and YOUT pins are not included in the DC characteristics.

CXD3152AR

AC Characteristics Item CSYNC_IN fall setup time, activated by the falling edge of 2MCKI CSYNC_IN fall hold time, activated by the falling edge of 2MCKI Delay time from the falling edge of 2MCKI to MCKO output CSYNC_IN fall setup time, activated by the rising edge of 2MCKI CSYNC_IN fall hold time, activated by the rising edge of 2MCKI Delay time from the rising edge of 2MCKI to MCKO output CHARA setup time, activated by the falling edge of MCKO CHARA hold time, activated by the falling edge of MCKO Delay time from the falling edge of MCKO to Y0 to Y7 output Power-on reset time Reset pulse width SCL clock frequency SCL clock high level width SCL clock low level width SDA setup time, activated by the rising edge of SCL SDA hold time, activated by the falling edge of SCL Delay time from the falling edge of SCL to SDA low level output Delay time from the falling edge of SCL to SDA output floating SHP rise time, activated by the falling edge of 2MCKI SHD rise time, activated by the falling edge of 2MCKI Symbol Min. 10 10 10 10 0 20 1 1 700 700 30 0 0

(Output load: CL = 50pF) Typ. Max. 20 20 15 500 20 15 30 Unit ns ns ns ns ns ns ns ns ns s s kHz ns ns ns ns ns ns ns ns

tsu1 thd1 tdly1 tsu2 thd2 tdly2 tsu3 thd3 tdly3 tpor trst
fscl

thigh tlow tsu4 thd4 tdly4 tdly5 tdly6 tdly7

10

CXD3152AR

Master Clock Generation Timing (1) MCKPHS = Low

2MCKI

thd1 CSYNC_IN

tsu1

tdly1 MCKO

tdly1

tdly1

(2) MCKPHS = High

2MCKI

thd2 CSYNC_IN

tsu2

tdly2 MCKO

tdly2

tdly2

Video Signal Related Input/Output Timing

MCKO tsu3 CHARA thd3 tdly3

Y0 to Y7

11

CXD3152AR

Reset Timing

3V VDD tpor VIH trst

REGRES

I2C bus Timing

SCL thigh SDA (input) tsu4 SDA (output) Hi-Z tdly4 tdly5 thd4 tlow

Analog Signal Processing Sampling Pulse Timing

2MCKI

SHP

tdly6

SHD

tdly7

ADCLK

tdly8

tdly8

Note 1) When MCKPHS = Low

12

CXD3152AR

Analog Block Electrical Characteristics 10-bit A/D Converter Electrical Characteristics Item Resolution Conversion frequency Nonlinearity error Differential nonlinearity error Symbol RES Fs I.L. D.L. Min. Typ. 15 Max. 10 20 2.0 1.0 (VDD3 = 3.3V, VSS = 0V, Ta = 25C) Unit Bits MSPS LSB LSB DC accuracy DC accuracy Test conditions

For the power supply names, refer to the symbols in the Pin Description.

9-bit D/A Converter Electrical Characteristics Item Resolution Conversion frequency Zero scale output voltage Full scale output voltage Full scale output current Nonlinearity error Differential nonlinearity error Symbol RES Fs VZERO VFULL IFULL I.L. D.L. Min. 15 1.21 0 Typ. 0 1.30 6.6 Max. 10 20.0 15 1.43 16.5 2.0 1.0

(VDD6 = 3.3V, VSS = 0V, Ta = 25C) Unit Bits MSPS mW V mA LSB LSB DC accuracy DC accuracy Test conditions

For the power supply names, refer to the symbols in the Pin Description.

13

CXD3152AR

CDS-AGC Electrical Characteristics Item CAP1 DC level Symbol CAP1 Min. 1.5

(VDD1, 2 = 5.0V, VDD3 = 3.3V, VSS = 0V, Ta = 25C) Typ. 1.6 Max. 1.7 Unit V Test conditions CAP1 output DC level CCDIN = 1.6V (DC) GOUT = 1.5V CAPA2 output DC level CCDIN = 1.6V (DC) GOUT = 1.5V YOUT output DC level CCDIN = 1.6V (DC) GOUT = 2.5V GCOF1 = V4 CDSDC V4 = YOUT output DC level CCDIN = 1.6V (DC) GOUT = 1.5V GCOF2 = V5 CDSDC V5 = YOUT output DC level CCDIN = 1.6V (DC) GOUT = 0.5V YOUT output gain CCDIN = S1 (Note 2) GOUT = 3.3V YOUT output gain CCDIN = S1 (Note 2) GOUT = 0V YOUT output AC level CCDIN = S1 (Note 3) GOUT = 0.5V YOUT output AC level CCDIN = S1 (Note 3) GOUT = 2.5V IRISOUT DC level CCDIN = 1.6V (DC) GOUT = 3.3V IRISOUT gain CCDIN = S2 (Note 4) GOUT = 3.3V IRISOUT AC level CCDIN = S2 (Note 5) GOUT = 3.3V

CAPA2 DC level

CAPA2

2.5

3.0

3.5

CDS DC level

CDSDC

2.9

3.4

3.9

AGC DC offset 1

GCOF1

0.2

0.2

mV

AGC DC offset 2

GCOF2

0.4

0.4

mV

AGC minimum gain characteristics (Note 1) AGC maximum gain characteristics (Note 1)

AGCG1

3.3

6.4

8.7

dB

AGCG2

15.7

18.8

21.1

dB

AGC D range 1

AGCD1

1.9

2.2

2.7

AGC D range 2

AGCD2

1.6

2.0

2.7

IRIS DC level

IRISDC

1.6

2.2

2.6

IRIS gain

IRISG

8.3

9.5

10.7

dB

IRIS D range

IRISDR

1.6

2.1

2.7

For the power supply names, refer to the symbols in the Pin Description. Note 1) Refer to the AGC Gain Characteristics. Note 2) S1: Va = 100 to 400mV, Vb = 1.6V (Va = peak to peak, Vb = peak to GND) Note 3) S1: Va = 1000mV, Vb = 1.6V Note 4) S2: Va = 400mV, Vb = 1.6V Note 5) S2: Va = 1000mV, Vb = 1.6V 14

CXD3152AR

CLP Electrical Characteristics Item CAPB2 DC level Symbol CAPB2 Min. 2.6

(VDD1, 2 = 5.0V, VDD3 = 3.3V, VSS = 0V, Ta = 25C) Typ. 2.7 Max. 2.8 Unit V Test conditions CAPB2 output DC level SW1 = A, SW2 = A MONITOR output DC level CLP = "H" SW1 = A, SW2 = A MONITOR output gain SW1 = B, SW2 = B YIN = S4 (Note 1) MONITOR output AC level SW1 = B, SW2 = A YIN = S3 (Note 2)

CLP DC level

CLPDC1

2.6

2.7

2.8

CLP gain

CLPG

0.6

1.2

dB

CLP D range

CLPD

2.0

2.4

2.7

For the power supply names, refer to the symbols in the Pin Description. Note 1) S4: Va = 1000mV, Vb = 2.75V (Va = peak to peak, Vb = peak to GND) Note 2) S3: Va = 2000mV, Vb = 3.6V

OPAMP Electrical Characteristics Item OPAMP DC H OPAMP DC L Symbol OPH OPL Min. 2.8 0.8

(VDD1, 2 = 5.0V, VDD3 = 3.3V, VSS = 0V, Ta = 25C) Typ. 2.9 0.9 Max. 3.0 1.0 Unit V V Test conditions REFH output DC level SW1 = A, SW2 = A REFL output DC level SW1 = A, SW2 = A

For the power supply names, refer to the symbols in the Pin Description.

AGC Gain Characteristics (VDD1, 2 = 5.0V, VDD3 = 3.3V, VSS = 0V, Ta = 25C)
25 20 AGC gain [dB] 15 10 5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.3 GOUT voltage [V]

AGC Gain Characteristics

15

CXD3152AR

Analog Input/Output Pin Equivalent Circuits Pin No. 5 Symbol I/O Equivalent circuit Description Video signal output pin for iris detection Maximum output amplitude = 2.10Vp-p (typ.) Video signal output pin of gain control amplifier (AGC) Maximum output amplitude = 2.25Vp-p (typ.) Black level = 3.40V DC (typ.) Video signal output of analog clamp circuit Monitor pin for input signal to ADC Black level = 2.75V DC (typ.)
VDD1, 2

IRISOUT

O
VDD1, 2

YOUT

6 10

10

MONITOR

CCDIN

I
2 13

Maximum input amplitude = 3.40Vp-p (Maximum video signal amplitude from precharge level = 2.00Vp-p) DC input bias = 1.80 0.1V High reference input pin for ADC 2.92V DC input (typ.) Low reference input pin for ADC 0.82V DC input (typ.)

13 14

REFHIN REFLIN

I I

14

VDD1, 2

YIN

Input pin for video signal to undergo A/D conversion Maximum input amplitude = 2.30Vp-p (typ.) Black level = 2.73V DC (typ.)

VDD1, 2

CAPA2

4 1k 10k 10k

DC bias output pin of the gain control amplifier 3.00V DC output (typ.)

CAP1

O
3 8

VDD1, 2

DC bias output pin of the CDS circuit 1.58V DC output (typ.)

CAPB2

Clamp level (DC) input pin of the clamp circuit for A/D conversion 2.73V DC input (typ.) 16

CXD3152AR

Pin No.

Symbol

I/O

Equivalent circuit
VDD7 1.5k VDD1, 2 64

Description

64

GOUT

Gain control signal (8-bit DAC for gain control) output pin for AGC

VDD7

15

REFH

15

High reference output pin for ADC Voltage follower output 2.90V DC output (typ.)

VDD3

16

REFL

16

Low reference output pin for ADC Voltage follower output 0.80V DC output (typ.)

VDD3

19

REFBIAS

19

DC bias output pin for ADC 1.55V DC output (typ.)

VDD6

38

ANAB

D/A converter negative output 0 to 1.24V output

38

39

ANA

39

D/A converter positive output 0 to 1.24V output

17

CXD3152AR

Pin No.

Symbol

I/O

Equivalent circuit
VDD6

Description

37

RREF

O
37

DAC reference voltage generation pin 1.32V DC output (typ.)

VDD6

33

CVREF

33

DAC reference voltage output pin 1.32V DC output (typ.)

VDD6

34

COMP

O
34

DAC phase compensation pin 2.18V DC output (typ.)

Note) For the power supply names in the equivalent circuits, refer to the symbols in the Pin Description.

18

CXD3152AR

Timing Chart Horizontal Direction Timing 2MCK: MCK: MCKO: CCDIN: SHP: SHD: cblk: CSYNC: A_CLP: D_CLP: DOUT[7:0]: ANA: Master clock input for the CXD3152AR Internal reference clock produced by dividing the input reference clock (2MCK) in half. Latch clock for digital output signal (Inverted MCK signal) Imaging signal from CCD Precharge level sampling pulse input Video level sampling pulse input Internal composite blanking pulse (for VIDEO output signal) Composite sync pulse input (in phase for CSYNC_IN and the VIDEO output signal) Internal pulse for analog clamp Internal pulse for digital clamp 8-bit digital output signal Analog output signal

Vertical Direction Timing HD: cblk: CSYNC: A_CLP: D_CLP: CCDIN: DOUT[7:0]: Internal horizontal sync signal Internal composite blanking pulse (for VIDEO output signal) Composite sync pulse input (in phase for CSYNC_IN and the VIDEO output signal) Internal pulse for analog clamp Internal pulse for digital clamp Video signal from the CCD 8-bit digital output signal

19

Horizontal Direction Timing Chart Count CLK = 606fH = 19.0699/2MHz

EIA 510H System

0 20 90 110 100 80

10 60

30

120

2MCK

MCK

MCKO

CCDIN

SHP

ANA
2 6 11 16 19

499

499 500 501 502 503 504 505

DOUT[7:0]

505

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

20
14 59 14 24 16

SHD

CSYNC

A_CLP

506 507 508 509 510

D_CLP 104

cblk 17.5 clocks

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

CXD3152AR

Horizontal Direction Timing Chart Count CLK = 606fH = 18.9375/2MHz

CCIR 510H System

0 110 120

10 20 30 60 90 100

130

2MCK

MCK

MCKO

CCDIN

SHP

ANA
2 6 11 16 19

489

489 490 491 492 493 494 495

DOUT[7:0]

495

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

21
14 59 14 24 16

SHD

CSYNC

A_CLP

496 497 498 499 500

D_CLP 114

cblk 17.5 clocks

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

CXD3152AR

Horizontal Direction Timing Chart Count CLK = 910fH = 28.63636/2MHz

EIA 760H System

0 20 30 40 90 150 160 140

10

170

2MCK

MCK

MCKO

CCDIN

SHP

ANA
7 11 16 21 24

758

758 759 760 761 762 763 764

DOUT[7:0]

764

7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

22
22

SHD

CSYNC

A_CLP

764 765 766 767 768

12

D_CLP 154

cblk 15.5 clocks

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

CXD3152AR

Horizontal Direction Timing Chart Count CLK = 908fH = 28.375/2MHz

CCIR 760H System

0 20 30 40 90 170 150 160

10

180

2MCK

MCK

MCKO

CCDIN

SHP

ANA
9 13 18 21

743

743 744 745 746 747 748 749

DOUT[7:0]

749

9 10 11 12 13 14 15 16 17 18 19 20 21

23
22 12

SHD

CSYNC

A_CLP

D_CLP 169

cblk 13.5 clocks

748 749 750 751 752

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

CXD3152AR

258 260 262 (520) (522) (524) 0

476 478 480 482 484 486

475 477 479 481 483 485

480 482 484 486 488 490 492 494 OB

479 481 483 485 487 489 491 493 OB

3 5 7 9 11 13 15 17 19 21 23 25

2 4 6 8 10 12 14 16 18 20 22 24

OB OB OB OB OB OB 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

OB OB OB OB OB OB 2 4 6 8 10 12 14 16 18 20 22 24 26 28

475 474 477 476 479 478 481 480 483 482 485 484 487 486

479 481 483 485 487 489 491 493 OB

478 480 482 484 486 488 490 492 494 OB

4 6 8 10 12 14 16 18 20 22 24 26 28

1 3 5 7 9 11 13 15 17 19 21 23 25 27

OB OB OB OB OB OB 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32

OB OB OB OB OB OB 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31

24
HD cblk A_CLP CSYNC D_CLP CCDIN

Vertical Direction Timing Chart

DOUT[7:0] 2H

Even field Odd field Odd field Even field

2 4 6 8 10 15 20 25 30 258 0 4 8 2 10 6 260 (262) (264) (266) (268) (270) (272) 15 (277) 20 (282) 25 (287) 30 (292)

EIA 510H/760H System

CXD3152AR

564 566 568 570 572 574 576

563 565 567 569 571 573 575

568 570 572 574 576 578 580 582 OB

567 569 571 573 575 577 579 581 OB

1 3 5 7 9 11 13 15

OB 2 4 6 8 10 12 14

OB OB OB OB OB OB 1 3 5 7 9 11 13 15 17

OB OB OB OB OB OB 2 4 6 8 10 12 14 16

565 567 569 571 573 575

564 566 568 570 572 574

569 571 573 575 577 579 581 OB

568 570 572 574 576 578 580 582 OB

2 4 6 8 10 12 14 16 18

1 3 5 7 9 11 13 15 17

OB OB OB OB OB OB 2 4 6 8 10 12 14 16 18 20 22

OB OB OB OB OB OB 1 3 5 7 9 11 13 15 17 19 21

25
HD cblk A_CLP CSYNC D_CLP CCDIN

Vertical Direction Timing Chart

DOUT[7:0] 2H

Even field

308 310 312 (620) (622) (624)0 2 4 6 8 10 15 20 25 30 308 310 10 6 8 2 4 0 (313) (315) (317) (319) (321) (323) 15 (328) 20 (333) 25 (338) 30 (343)

Odd field Odd field Even field

CCIR 510H/760H System

CXD3152AR

CXD3152AR

I2C Serial Communication 1. Description of communication The CXD3152AR performs serial communication between a PC or an external EEPROM via the I2C bus. In communication with a PC, the PC is the master device and the CXD3152AR is the slave device. On the other hand, in communication with an EEPROM, the CXD3152AR is the master device and the EEPROM is the slave device. Communication is performed using two signal lines: SDA and SCL. SDA is a bidirectional serial data transfer line, and is used to transfer addresses from master to slave and to transfer data between master and slave. SDA is normally pulled up to VDD by external resistance of several k. (Therefore, SDA is high at high impedance.) SCL is a bidirectional serial clock transfer line, and is used as the data transfer synchronization clock. SCL is driven by the master device, and like SDA is pulled up to VDD by external resistance of several k. 2. Slave address The CXD3152AR I2C slave address is as follows. [A6:A0] = 0011111 (b) 3. I2C protocol Communication conforms to the I2C bus protocol. Data transfer is started when the bus is not in the busy status. During the data transfer period, the data line must be kept stable while the clock line is high. Otherwise, data line changes while the clock line is high are interpreted as START or STOP conditions. START condition The START condition occurs before all commands to the device, and is defined as SDA changing from high to low when SCL is high. STOP condition The STOP condition is defined as SDA changing from low to high when SCL is high. All operations must end in the stop condition. 4. Communication timing During read, the SDA data is taken in sync with the falling edge of SCL. During write, the data is output to SDA after a certain delay time from the falling edge of SCL. The communication data is MSB first. An overview of the byte-write and byte-read timings are described below. Byte-write timing In the byte-write mode, the master device transmits the START condition and the slave address information (the R/W bit is set to 0) to the slave device. After the slave returns an acknowledgement, the master transmits the byte address to be written in the slave address pointer. After receiving the next acknowledgement from the slave, the master transfers the data to be written to the preceding address. The slave device returns an acknowledgement again, and the master generates the STOP condition.
SLAVE ADDRESS BYTE ADDRESS STOP P ACK ACK ACK BUS ACTIVITY MASTER SDA LINE START

DATA

BUS ACTIVITY

26

CXD3152AR

Byte-read timing In the byte-read mode, the master device first transmits the START condition, the slave address, and the byte address of the position to be read to the slave device as a write operation. After the slave returns an acknowledgement, the master transmits the START condition and slave address (at this time the R/W bit is set to 1) again. After that, the slave issues an acknowledgement and transfers the read data. The master generates the STOP condition without transmitting an acknowledgement.
START START

MASTER SDA LINE

SLAVE ADDRESS

BYTE ADDRESS

SLAVE ADDRESS

DATA

S ACK ACK

S NO ACK ACK

BUS ACTIVITY

Note 1) The upper 7 bits of the slave address indicate the device address, while the lowermost bit indicates the R/W mode. (Read mode when this bit is high, and write mode when it is low.) Note 2) The CXD3152AR slave address is [A6:A0] = 0011111 (b). Note 3) ACK is the response acknowledgement signal, and the slave device goes to low. Note 4) NO ACK means that a response acknowledgement signal is not returned. Note 5) S: START condition, P: STOP condition

27

STOP

BUS ACTIVITY

CXD3152AR

Description of Registers Address Symbol Part symbol REGRES bit 0 1 2 00 (h) REGRES dummy 3 4 5 6 7 0 1 2 3 0F (h) WSTART WSTART 4 5 6 7 0 1 2 3 10 (h) RSTART RSTART 4 5 6 7 0 1 YGAM1 14 (h) YGAM1 2 3 4 5 dummy 6 7 Gamma correction curve adjustment-1 Sets the intersection between the 1st approximation line (slope = 1) and the 2nd approximation line (slope = 3). Setting range: 00 (h) to 1F (h) Horizontal timing for read start from line memory Set in MCKI clock units 0x00 : Earliest (advanced) position 0xFE : Latest (delayed) position 0xFF : Internal fixed value EIA510 system = 5C (h) CCIR510 system = 66 (h) EIA760 system = 89 (h) CCIR760 system = 96 (h) Horizontal timing for write start to line memory Set in MCKI clock units 0x00 : Earliest (advanced) position 0xFE : Latest (delayed) position 0xFF : Internal fixed value EIA510 system = 67 (h) CCIR510 system = 71 (h) EIA760 system = 95 (h) CCIR760 system = A3 (h) W Description Register reset 0: Reset, 1: Normal (The REGRES pin (Pin 40) has precedence.) Default R/W

FF (h)

FF (h)

00 (h) W

28

CXD3152AR

Address

Symbol

Part symbol

bit 0 1 2

Description

Default R/W

YGAM2 15 (h) YGAM2

3 4 5 6

Gamma correction curve adjustment-2 Sets the intersection between the 2nd approximation line (slope = 3) and the 3rd approximation line (slope = 3/2). Setting range: 00 (h) to 3F (h)

0A (h) W

dummy

7 0 1 2 Gamma correction curve adjustment-3 Sets the intersection between the 3rd approximation line (slope = 3/2) and the 4th approximation line (slope = 1). Setting range: 00 (h) to 7F (h)

16 (h)

YGAM3

YGAM3

3 4 5 6

20 (h)

dummy

7 0 1 2 Gamma correction curve adjustment-4 Sets the intersection between the 4th approximation line (slope = 1) and the 5th approximation line (slope = 3/4). Setting range: 00 (h) to 7F (h)

17 (h)

YGAM4

YGAM4

3 4 5 6

2E (h)

dummy

7 0 1 2 Gamma correction curve adjustment-5 Sets the intersection between the 5th approximation line (slope = 3/4) and the 6th approximation line (slope = 1/2). Setting range: 00 (h) to 7F (h)

18 (h)

YGAM5

YGAM5

3 4 5 6

36 (h)

dummy

29

CXD3152AR

Address

Symbol

Part symbol

bit 0 1 2

Description

Default R/W

19 (h)

YGAM6

YGAM6

3 4 5 6

Gamma correction curve adjustment-6 Sets the intersection between the 6th approximation line (slope = 1/2) and the 7th approximation line (slope = 1/8). Setting range: 00 (h) to 7F (h) The 7th approximation line is used for knee processing.

41 (h)

dummy

7 0 1 Horizontal aperture correction signal gain setting The gain changes linearly from 0 (h) to 7 (h). 0 (h): 0 F (h): Maximum gain

HAPGAIN

2 3

09 (h)

1A (h)

HAPGAIN

4 5 dummy 6 7 0 1 2 HAPCORE1 3 4 Horizontal aperture correction signal noise suppression (coring) characteristics setting OUTPUT = INPUT HAPCORE1 If (OUTPUT < 0), OUTPUT = 0 00 (h): Noise suppression off 3F (h): Maximum noise suppression level

02 (h)

1B (h)

HAPCORE

5 6 HAPCORE2 7 0 1 VAPGAIN 2 3 Horizontal aperture correction signal noise suppression (coring) characteristics setting OUTPUT = INPUT If (OUTPUT HAPCORE2), OUTPUT = 0 00 (h): Noise suppression off 03 (h): Maximum noise suppression level Vertical aperture correction signal gain setting The gain changes linearly from 0 (h) to F (h). 0 (h): 0 F (h): Maximum gain

00 (h)

04 (h)

1C (h)

VAPGAIN

4 5 dummy 6 7

30

CXD3152AR

Address

Symbol

Part symbol

bit 0 1 2

Description Vertical aperture correction signal noise suppression (coring) characteristics setting OUTPUT = INPUT VAPCORE1 If (OUTPUT < 0), OUTPUT = 0 00 (h): Noise suppression off 3F (h): Maximum noise suppression level

Default R/W

VAPCORE1

3 4

02 (h)

1D (h)

VAPCORE

5 6 VAPCORE2 7 0 1 LCLIP 2 3 Vertical aperture correction signal noise suppression (coring) characteristics setting OUTPUT = INPUT If (OUTPUT VAPCORE2), OUTPUT = 0 00 (h): Noise suppression off 03 (h): Maximum noise suppression level Aperture correction signal minus side clip level setting OUTPUT = INPUT If (INPUT LCLIP), OUTPUT = LCLIP 0 (h): Maximum clip level F (h): Minimum clip level Aperture correction signal plus side clip level setting OUTPUT = INPUT If (INPUT HCLIP), OUTPUT = HCLIP 0 (h): Maximum clip level F (h): Minimum clip level

00 (h)

04 (h)

1E (h)

APCLIP

4 5 HCLIP 6 7 0 1 AT_APCORE 2 3

06 (h)

Aperture correction signal coring level DGC link setting 0x0: Coring off 0x1F: Maximum coring level

1F (h) W

1F (h)

AT_APCORE

4 5 dummy 6 7 0 1 2 YGAIN1 Signal gain setting when GAMMA1 and GAMMA2 are set to 00 (gamma = 0.45) 3C (h)

20 (h)

3 4 5 6

YGAIN1

dummy

31

CXD3152AR

Address

Symbol

Part symbol

bit 0 1 2

Description

Default R/W

YGAIN2 21 (h) YGAIN2

3 4 5 6

Signal gain setting when GAMMA1 and GAMMA2 are set to 10 (gamma = 0.6)

1F (h) W

dummy

7 0 1 2

YGAIN3 22 (h) YGAIN3

3 4 5 6

Signal gain setting when GAMMA1 and GAMMA2 are set to 01 (gamma = 1.0)

18 (h) W

dummy

7 0 1 2

YGAIN4 23 (h) YGAIN4

3 4 5 6

Signal gain setting when GAMMA1 and GAMMA2 are set to 11 (gamma = S)

3A (h) W

dummy

7 0 1 2 Pedestal level setting The pedestal level changes linearly from 0 (h) to F (h). 00 (h): Low 17 (h): 7.5 IRE 3F (h): High

24 (h)

PED

PED

3 4 5 6

17 (h)

dummy

32

CXD3152AR

Address

Symbol

Part symbol LCLIP

bit 0 1 2

Description Clip level setting for the black level and lower 0: 20 IRE, 1: Pedestal level

Default R/W 00 (h)

25 (h)

LOWCLIP dummy

3 4 5 6 7 0 1 2 CHARA_G Externally input 1-bit character signal gain setting 00 (h): 85 IRE 20 (h): 0 3F (h): +85 IRE

27 (h)

3 4 5 6

32 (h) W

CHARA_G

dummy

7 0 1 2

28 (h)

3 WT_CLIP WT_CLIP 4 5 6 7 0 1 2 BK_CLIP

White clip level setting

C4 (h)

Video signal minus component clip level setting 1D (h) W

29 (h)

3 4 5 6

BK_CLIP

dummy

33

CXD3152AR

Address

Symbol

Part symbol

bit 0 1 2

Description Aperture signal gamma correction characteristics setting Sets the intersection of the 1st approximation line (slope = 2) which passes through the origin and the 2nd approximation line (slope = 1). Setting range: 00 (h) to 3F (h)

Default R/W

APGAM1 2A (h) APGAM1

3 4 5 6

3F (h) W

dummy

7 0 1 2 Aperture signal gamma correction characteristics setting Sets the intersection of the 2nd approximation line (slope = 1) and the 3rd approximation line (slope = 7F (h) 1/2). Setting range: 00 (h) to 7F (h)

2B (h)

APGAM2

APGAM2

3 4 5 6

dummy APSW

7 0 1 2 Aperture correction signal added position setting 01 (h) 0: After gamma correction, 1: Before gamma correction

2C (h)

APSW dummy

3 4 5 6 7 0 1 2 Reference level setting for auto gain control integral value

32 (h)

AGC_REF

AGC_REF

3 4 5 6

18 (h)

dummy

34

CXD3152AR

Address

Symbol

Part symbol

bit 0 1 2

Description

Default R/W

33 (h)

3 DGCMIN DGCMIN 4 5 6 7 0 1 2

Digital gain control (DGC) minimum gain limiter setting Valid when DGC = 1 When DGC = 0, this is the digital gain manual 20 (h) setting register. 20 (h) : 1.0 times (1F (h) and lower settings are prohibited) FF (h) : 8.0 times

34 (h)

3 DGCMAX DGCMAX 4 5 6 7 0 1 2

Digital gain control (DGC) maximum gain limiter setting Valid when DGC = 1 20 (h) : 1.0 times A0 (h) (1F (h) and lower settings are prohibited) 0xA0 : 5.0 times 0xFF : 8.0 times

35 (h)

AGCMIN

AGCMIN

3 4 5 6

Analog gain control (AGC) minimum gain limiter setting (Sets the upper 7 bits for gain signal generating 8-bit DAC. The lowest digit is "0".) Valid when AGC = 1 When AGC = 0, this is the analog gain manual setting register. 00 (h) : Min. 7F (h) : Max.

00 (h)

dummy

7 0 1 2 Analog gain control (AGC) maximum gain limiter setting (Sets the upper 7 bits for gain signal generating 8-bit DAC. The lowest digit is "0".) Valid when AGC = 1 00 (h) : Min. 7F (h) : Max.

36 (h)

AGCMAX

AGCMAX

3 4 5 6

59 (h)

dummy

35

CXD3152AR

Address

Symbol

Part symbol

bit 0 1

Description Auto gain control time constant setting Hold time (Hold_time) or feedback time (FB_time) can be selected by the SW setting. Hold_time = (AGCWAIT 2 + 2) Vt Vt: 1/60 (EIA), 1/50 (CCIR) (FB_time also uses the above formula.) Hold time/feedback time selection 0: Hold_time, 1: FB_time

Default R/W

AGCWAIT 37 (h) AGCWAIT SW dummy

2 3 4 5 6 7 0 1 2

1D (h) W 00 (h)

AGCTM

Auto gain control feedback time setting 0: Low speed, 1: High speed

00 (h)

38 (h)

AGCTM dummy

3 4 5 6 7 AGCHD 0 1 2 Auto gain control hold setting 0: Normal operation, 1: Hold 00 (h)

39 (h)

AGCHD dummy

3 4 5 6 7 0 1 2 Time constant setting Insensitive range setting (00: Short, 11: Long) (0: Narrow, 1: Wide) 3 (h) 0 1 1 0 0

3A (h)

DCLP

DCLP

3 4 5 6

Digital clamp operation mode setting (011: V period, 100: H period) 6 bit is also used. Digital clamp function ON/OFF (= 1) Digital clamp operation mode setting

dummy

36

CXD3152AR

Address

Symbol

Part symbol NEWCLPH

bit 0 1 2 3

Description Clamp system changing (1 = New system)

Default R/W 1

3B (h)

NEWCLPH

dummy

4 5 6 7 0 1 2 Period setting (effective more than 000111) of digital clamp data renewal (setting value + one field) 1 1 0 0 1 0

CLPCYCL 3C (h) CLPCYCL

3 4 5 6

dummy

7 0 0 Digital clamp insensitive range setting 1 0 W

HLDAREA

1 2 3

3D (h)

HLDAREA dummy

4 5 6 7 0 1 MAX_N_DEF 2 3 Maximum number of registered blemishes setting Maximum 10 points 0A (h)

4C (h)

MAX_N_DEF

4 5 dummy 6 7

37

CXD3152AR

Address

Symbol

Part symbol DEFRES

bit 0 1 2

Description Blemish detection operation reset 0: Reset, 1: Normal

Default R/W 01 (h)

5A (h)

DEFRES dummy

3 4 5 6 7 0 1 2

64 (h)

3 DEF01 X[0:7] 4 5 6 7 0 X[8:9] 1 2

Lower 8 bits of blemish pixel X address

00 (h) R/W

Upper 2 bits of blemish pixel X address

00 (h)

65 (h)

3 DEF02 Y[0:5] 4 5 6 7 0 Y[6:8] 1 2 3 D0: EVEN Y address offset data relative to ODD 0: Offset value 0, 1: Offset value 1 Fixed to 1 D2: Valid data/invalid data 0: Invalid data, 1: Valid data D3: Internal data/external data 0: External, 1: Internal dummy 00 (h) Upper 3 bits of blemish pixel Y address 00 (h) Lower 6 bits of blemish pixel Y address 00 (h)

R/W

66 (h)

DEF03 D[0:4]

4 5 6 7

R/W

38

CXD3152AR

Address 67 (h) 68 (h) 69 (h) 6A (h) 6B (h) 6C (h) 6D (h) 6E (h) 6F (h) 70 (h) 71 (h) 72 (h) 73 (h) 74 (h) 75 (h) 76 (h) 77 (h) 78 (h) 79 (h) 7A (h) 7B (h) 7C (h) 7D (h) 7E (h) 7F (h) 80 (h) 81 (h)

Symbol DEF11 DEF12 DEF13 DEF21 DEF22 DEF23 DEF31 DEF32 DEF33 DEF41 DEF42 DEF43 DEF51 DEF52 DEF53 DEF61 DEF62 DEF63 DEF71 DEF72 DEF73 DEF81 DEF82 DEF83 DEF91 DEF92 DEF93

Part symbol

bit

Description

Default R/W

Omitted: Same as DEF01 Omitted: Same as DEF02 Omitted: Same as DEF03 Omitted: Same as DEF01 Omitted: Same as DEF02 Omitted: Same as DEF03 Omitted: Same as DEF01 Omitted: Same as DEF02 Omitted: Same as DEF03 Omitted: Same as DEF01 Omitted: Same as DEF02 Omitted: Same as DEF03 Omitted: Same as DEF01 Omitted: Same as DEF02 Omitted: Same as DEF03 Omitted: Same as DEF01 Omitted: Same as DEF02 Omitted: Same as DEF03 Omitted: Same as DEF01 Omitted: Same as DEF02 Omitted: Same as DEF03 Omitted: Same as DEF01 Omitted: Same as DEF02 Omitted: Same as DEF03 Omitted: Same as DEF01 Omitted: Same as DEF02 Omitted: Same as DEF03

39

CXD3152AR

Address

Symbol

Part symbol DGC

bit 0

Description Digital gain switching (Same function as DGC pin) 0: Fixed, 1: Auto Analog gain switching (Same function as AGC pin) 0: Fixed, 1: Auto Register setting/pin setting selection 0: Pin setting, 1: Register setting

Default R/W 00 (h)

AGC

00 (h)

96 (h)

ADGC

SW

2 3 4

00 (h)

dummy

5 6 7

GAM1 GAM2 SW 97 (h) GAMMA

0 1 2 3 4

Gamma correction characteristics switching (Same function as GAMMA1 and GAMMA2 pins) 00: 0.45, 01: 0.6, 10: 1, 11: S curve Register setting/pin setting selection 0: Pin setting, 1: Register setting

00 (h)

00 (h) W

dummy

5 6 7

BLCW1 BLCW2 SW 98 (h) BLCW

0 1 2 3 4

Backlight compensation window switching (Same function as BLCW1 and BLCW2 pins) 00 (h) 00: Full-screen photometry, 01: Lower photometry 10: Center photometry, 11: Lower + center photometry Register setting/pin setting selection 0: Pin setting, 1: Register setting 00 (h) W

dummy

5 6 7

40

CXD3152AR

Address

Symbol

Part symbol EIA

bit 0

Description TV mode switching (Same function as EIA pin) 0: EIA, 1: CCIR Register setting/pin setting selection 0: Pin setting, 1: Register setting

Default R/W 00 (h)

SW 99 (h) EIA

1 2 3 4

00 (h) W

dummy

5 6 7

CCD

CCD number of horizontal pixels switching (Same function as CCD pin) 0: 510H system, 1: 760H system Register setting/pin setting selection 0: Pin setting, 1: Register setting

00 (h)

SW 9A (h) CCD

1 2 3 4

00 (h) W

dummy

5 6 7

MIR

Mirror inversion switching (Same function as MIRROR pin) 0: Standard, 1: Mirror Register setting/pin setting selection 0: Pin setting, 1: Register setting

00 (h)

SW 9B (h) MIRROR

1 2 3 4

00 (h) W

dummy

5 6 7

41

CXD3152AR

Address

Symbol

Part symbol APCON

bit 0

Description Aperture correction switching (Same function as APCON pin) 0: Off, 1: On Register setting/pin setting selection 0: Pin setting, 1: Register setting

Default R/W 00 (h)

SW 9C (h) APCON

1 2 3

00 (h) W

dummy

4 5 6 7

DACSW

0 1 2

DA conversion frequency setting 0: 2MCKI/2, 1: 2MCKI

01 (h)

9D (h)

OVSA

3 dummy 4 5 6 7 DEFECT 0 Blemish compensation function switching (Same function as DEFECT pin) 0: Off, 1: On Register setting/pin setting selection 0: Pin setting, 1: Register setting 00 (h)

SW 9E (h) DEFECT

1 2 3

00 (h) W

dummy

4 5 6 7

DSCSW

0 1 2

Video output DAC on/off 0: On, 1: Off

00 (h)

9F (h)

DACSW dummy

3 4 5 6 7 42

CXD3152AR

Address

Symbol

Part symbol OEB

bit 0

Description Digital output (Y0 to Y7) switching (Same function as OEB pin) 0: Output, 1: Hi-Z Register setting/pin setting selection 0: Pin setting, 1: Register setting

Default R/W 00 (h)

SW A0 (h) OEB

1 2 3

00 (h) W

dummy

4 5 6 7

CHARA SW

0 1 2

1-bit character signal input switching (Same function as CHARA pin) Register setting/pin setting selection 0: Pin setting, 1: Register setting

00 (h) 00 (h)

A1 (h)

CHARA dummy

3 4 5 6 7

43

CXD3152AR

Using the EEPROM The CXD3152AR can connect an external EEPROM which supports the I2C bus. Normally, read and write to and from the EEPROM are performed from the PC master via the I2C bus to the slave EEPROM. Also, this IC can automatically read the user-set register values during power-on by writing the addresses and setting values for up to 64 registers in the EEPROM. (At this time this IC is the master device and the EEPROM is the slave device.) The serial EEPROM S-24C01B made by Seiko Instruments Co., Ltd. or equivalent product can be used as the external EEPROM. The external EEPROM load timing during power-on or register reset is shown below for when an EEPROM is mounted and not mounted. The I2C bus is occupied by the EEPROM load at this period, so when using the I2C bus, other communication by the master device is prohibited for the following times from the rising edge of REGRESS.

When an EEPROM is mounted REGRES SCL/SDA Max. 135ms active (read from the EEPROM) When an EEPROM is not mounted REGRES SCL/SDA Max. 2ms active (checking for EEPROM presence)

44

CXD3152AR

Package Outline

Unit: mm

64PIN LQFP (PLASTIC)

12.0 0.2 10.0 0.2 48 49 33 32 0.15 0.05 0.1

A 64 17

1 1.25 0.5

+ 0.08 0.18 0.03

16

1.7 MAX 0.1 M

0.1 0.1

0 to 10

DETAIL A

0.5 0.2

(0.5)

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING 42 ALLOY 0.3g LEAD TREATMENT LEAD MATERIAL PACKAGE MASS

SONY CODE EIAJ CODE JEDEC CODE

LQFP-64P-L061 LQFP064-P-1010-AY

LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL SOLDER COMPOSITION PLATING THICKNESS SPEC. 42 ALLOY Sn-Bi 5-18m

45

Sony Corporation