Beruflich Dokumente
Kultur Dokumente
Design
The TS interface supports 188 and 204 byte packets as standardized for
Digital Video Broadcasting (DVB) MPEG-2 transport. The reference
design supports both multi-program TS (MPTS) and single-program TS
(SPTS) data. The reference design does not make any attempt to identify
or separate individual programs from an MPTS input.
Encapsulation of the TS data for Ethernet uses IP and the user datagram
protocol (UDP). The real-time transport protocol (RTP) can also
optionally be used. Dedicated hardware performs the encapsulation,
which maximizes the throughput of the reference design and minimizes
latency. Frames can be processed, transmitted, and received at the
Ethernet line rate, which supports an aggregate TS bandwidth of over 900
Mbps for a gigabit Ethernet link.
Altera Corporation 1
AN-374-1.3 Preliminary
Video Over IP Reference Design
Specifications & Many standards and industry specifications have been referenced in
creating this reference design. These standards are summarized in this
Standards section.
DVB-ASI
The DVB Project defined an ASI for the transmission of MPEG-2 TS data.
It is specified by European Standard EN 50083-9.
ASI is a 270-Mbps serial link that carries 188 or 204 byte MPEG-2 TS
packets over a physical and signalling interface layer based on fibre
channel. One or more programs can be carried over a single ASI.
RTP is primarily aimed at the distribution of audio and video over the
internet for applications such as video conferencing and video streaming.
However, this protocol is also useful for the distribution of video over
Ethernet in the more controlled environment of a broadcast facility. RTP
offers features for time stamping and detection of packet loss or re-
ordering.
2 Altera Corporation
Preliminary
Specifications & Standards
RFC2250 defines an RTP payload format for MPEG-1 and MPEG-2 video.
It includes details for the encapsulation of MPEG-2 TS data, and is
referenced by the Pro-MPEG code of practice #3 and the DVB-IP
Handbook.
UDP/IP
RTP is a transport protocol. Most commonly, it uses UDP as the host-to-
host layer and IP as the internet layer.
Altera Corporation 3
Preliminary
Video Over IP Reference Design
DVB-IPI
There is a DVB IP Infrastructure (IPI) group that is defining technology
for the distribution of DVB services over IP. This is primarily targeted at
direct-to-home (DTH) content delivery, but some of the work is also
applicable to contribution and primary distribution applications.
Overview The reference design accepts TS data and encapsulates it for transmission
over Ethernet. This function is a TS-to-Ethernet bridge (see Figure 1).
TS FIFO Buffer
Input
Transmit
Queue
Transmit
DMA Encapsulate
Host
MII/ PHY
Transmit
GMII
Queue Receive
DMA
Host
Receive
Queue
4 Altera Corporation
Preliminary
Overview
The design can also receive frames from Ethernet and generate TS data.
This function is an Ethernet-to-TS Bridge (see Figure 2).
Receive
Queue
Receive
DMA De-encapsulate
Host
MII/ PHY
Receive
GMII
Queue Transmit
DMA
Host
Transmit
Queue
Altera Corporation 5
Preliminary
Video Over IP Reference Design
TS-to-Ethernet
Figure 3 shows the data flow for TS-to-Ethernet.
Transmit MII/
Pointer
Queue GMII
Transmit
DMA Encapsulate PHY
Free
List
The received TS packets are accumulated to create the payload for the
Ethernet frames. Typically seven packets from an individual input port
are combined to make the payload for a single Ethernet frame, although
this number is configurable.
The frame buffer module provides storage for the Ethernet frame payload
for multiple input ports. A pointer identifies an individual frame storage
location within the frame buffer. Pointer value 0 identifies the first
location, pointer value 1 identifies the second location, etc. A list of
pointers to free locations is maintained by a stack. This stack is referred to
as the buffer free list.
Before an input port can accept data, it requests a pointer from the buffer
free list. Data is then received, retimed through a FIFO buffer, and written
to the frame store location in the frame buffer that corresponds to the
allocated pointer.
6 Altera Corporation
Preliminary
Overview
When enough TS data has been accumulated to fill an Ethernet frame, the
payload length and input port identifier (channel number) are written to
a special location (parameter word) in the frame buffer. An entry is then
made to the transmit queue to indicate that the payload is ready for
encapsulation and transmission to Ethernet. The only data required by
the queue is the allocated pointer. Figure 4 shows the TS input logic flow
diagram.
If there are multiple TS input ports, each one performs the operations. At
any point in time, multiple inputs may be simultaneously writing to the
frame buffer and queuing transmit requests. The reference design
includes arbitration to handle this situation.
When there is an entry in the transmit queue, the first pointer is read. This
provides the location in the frame buffer where the Ethernet frame
payload is stored. Next, the parameter word for the location is read to
Altera Corporation 7
Preliminary
Video Over IP Reference Design
determine which input port the data came from, and what the payload
length is. The frame payload is then read and forwarded to the Ethernet
encapsulator.
(optional)
The complete Ethernet frame is passed to the physical layer (PHY) device
using a media independent interface (MII) or Gigabit MII (GMII).
8 Altera Corporation
Preliminary
Overview
Altera Corporation 9
Preliminary
Video Over IP Reference Design
Ethernet-to-TS
Figure 7 shows data flow for Ethernet-to-TS.
Receive
MII/
Queue
Receive GMII
DMA De-encapsulate PHY
Free
List
Ethernet frames are received from the PHY device using MII or GMII.
All frames forwarded by the PHY are parsed by the de-encapsulator. This
block identifies key parameters such as IP destination address and UDP
source and destination ports. It also identifies frames that contain
correctly encapsulated video data. The time that the start of frame was
received is also noted (timestamp).
The receive DMA block requests a pointer from the buffer free list. The
received Ethernet frame data is then written to the allocated location in
the frame buffer. When storage of the frame is complete, the receive DMA
stores the frame length, start of payload offset (for video frames) and
timestamp. It then loads the appropriate receive queue (for video frames),
host receive queue (for frames being routed to the host), or discards the
frame by releasing the allocated pointer. Figure 8 shows the Ethernet
input flow diagram.
10 Altera Corporation
Preliminary
Overview
Each TS output port has its own receive queue. Whenever there is an
entry in the related queue, the port fetches the head entry to get the
pointer to the related data in the frame buffer. It then reads the frame
parameters (length and start of payload offset) for that pointer from the
frame buffer.
The frame payload for the received frame is read from the frame buffer
and written to a FIFO buffer. The TS output reads from this FIFO buffer
and generates the output data. A minimum inter-packet gap is inserted
between individual packets in the output. A more complex mechanism
for averaging the output rate of the packets, or for correcting errors in the
PCR packet locations or timestamp, is possible but is not implemented in
this reference design.
When all the data for the received frame has been read from the frame
buffer, the pointer is released to the buffer free list. Figure 9 shows the TS
output flow diagram.
Altera Corporation 11
Preliminary
Video Over IP Reference Design
12 Altera Corporation
Preliminary
Overview
Payload
3
Frame Buffer
Host Interface Transmit
Channel
Info
Payload
Pointer Host
4 Transmit
Pointer MII/
Queue
GMII
Transmit
DMA Encapsulate PHY
2 Free
Pointer
List
6
Done Flag
5
The host has its own transmit queue to prevent its requests being stuck
behind those from the input ports. However the data path from the frame
buffer to the Ethernet output is the same as that used for TS data.
Packets sent by the host can be treated in the same way as those from the
TS input ports, with an Ethernet frame header being added by the
encapsulator, or the packets can just be sent out directly without any
modification. By using the encapsulator, the host can off load to hardware
operations such as the IP header checksum calculation. If the
encapsulator is used, the host has to configure a specific channel in the
transmit channel information block, thereby setting the encapsulation
parameters, before sending the frame.
When the host frame has been sent, the related pointer can either be
automatically released to the buffer free list, or the host can be informed
that the transmission is complete and then it can release (or reuse) the
pointer. Figure 11 shows the host transmit flow diagram.
Altera Corporation 13
Preliminary
Video Over IP Reference Design
Yes Auto-
Release
No
Another Yes
Frame
No
14 Altera Corporation
Preliminary
Overview
Payload
3 Frame Buffer
Receive
Channel
Info
Host Interface
MII/
Interrupt/ Receive GMII
Flag DMA De-encapsulate PHY
1 Host
2 Pointer Receive
Queue
Pointer Free
4
List
Ethernet frames that are received and address matched but not matched
for forwarding to a TS output are routed to the host processor. There is a
dedicated host receive queue that is loaded with an entry when one of
these frames is received.
The host can poll the host receive queue to see if there is an entry, or it can
receive an interrupt.
The receive frame is processed by reading the entry from the host receive
queue to get the pointer to the frame location in the frame buffer. The
frame length and content are then read from the frame buffer. When the
frame has been processed, the pointer is released to the buffer free list.
Alternatively the pointer can be used for a host transmit, such as when a
reply to a received message might be required. Figure 13 shows the host
receive flow diagram.
Altera Corporation 15
Preliminary
Video Over IP Reference Design
16 Altera Corporation
Preliminary
Functional Description
Nios Processor
System
MII/
GMII
TS TS-to-Ethernet Ethernet-PHY
Interfaces Bridge Interface
Clock
The reference design has the following three main clock domains:
■ TS interface clock
■ Host processor clock
■ Main system clock
The TS interface clock is typically 27 MHz, but can be any rate required
and does not have to be synchronous to other clocks in the design.
The host processor clock is constrained by the speed of the processor and
its system. It does not have to be synchronous to other clocks in the
design. The reference design uses a frequency of 50 MHz for Cyclone
devices and 85 MHz for Cyclone II devices.
The speed of the main system clock is constrained by the Ethernet data
rate and the bandwidth required by the TS interfaces.
For gigabit Ethernet operation, the system clock must be 125 MHz.
Altera Corporation 17
Preliminary
Video Over IP Reference Design
For 100 MHz Ethernet operation, a lower frequency system clock can be
used. The exact frequency required depends upon the number of TS
interfaces implemented by the design, and the data bandwidth used by
each port. For simplicity, this reference design uses 125 MHz for the
system clock regardless of the Ethernet rate that is supported.
Processor System
The reference design uses an SOPC Builder-generated processor system.
It consists of a Nios II processor and the following associated peripherals
and memory interfaces:
■ Flash interface
■ SDRAM controller and interface
■ SRAM interface
■ Timer peripheral
■ JTAG UART peripheral
■ LCD controller
■ Various parallel IOs for LED control and switch inputs
f For details on how to configure and generate this processor system using
SOPC Builder, see “Getting Started” on page 34.
Ethernet-PHY Interface
The Ethernet-PHY interface provides the interface between the TS-to-
Ethernet bridge and an external Ethernet PHY device. It provides an MII
and GMII connection to the PHY device, plus MDIO for control purposes.
It uses a FIFO interface to the TS-to-Ethernet bridge, which is based on the
Altera Atlantic™ interface. The reference design requires the Ethernet
connection to operate in full-duplex mode; half-duplex operation is not
supported.
f For more information on the Atlantic interface, see FS13: The Atlantic
Interface.
18 Altera Corporation
Preliminary
Functional Description
f For details on how to configure the MorethanIP MAC core for use in this
design, see “Getting Started” on page 34.
TS-to-Ethernet Bridge
The TS-to-Ethernet bridge instantiates the following modules to provide
the main functionality of the design:
■ TS input interface
■ TS output interface
■ MAC interface
■ Host processor interface
TS Input Interface
The TS input interface supports a configurable number of TS inputs. Each
of these inputs accepts either 188 or 204 byte TS packets. Data from the
interface is encapsulated and sent to an IP destination specified for that
interface.
Altera Corporation 19
Preliminary
Video Over IP Reference Design
There is a bus for each signal. Table 1 shows the TS input interface.
Note to Table 1:
(1) i is the port number, e.g., ts_in_ena[1] is data valid signal for port 1 and ts_in_dat[15:8] is its associated
data.
The design does not handle packet errors. Only provide complete, legal
packets to the interface. If errors are likely to occur, implement an external
buffer to discard any errors packets.
If the TS input is not required, tie the input signals identified above to
logic 0.
TS Output Interface
The TS output interface supports a configurable number of TS outputs. TS
data received from Ethernet is output on this interface, and the output
selection is determined by the encapsulation parameters of the received
frame.
The data is output in 188 or 204 byte packet format, depending on the size
of packet received. Typically, seven consecutive packets are output, with
a minimum interpacket gap between them. For this design, no attempt is
made to smooth the rate of the output, or to correct any jitter introduced
by the IP network.
20 Altera Corporation
Preliminary
Functional Description
There is a bus for each signal. Table 2 shows the TS output interface.
Note to Table 2:
(1) i is the port number, e.g., ts_out_ena[1] is data valid signal for port 1 and ts_out_dat[15:8] is its associated
data.
If the TS output is not required, tie the input signals identified above to
logic 0.
MAC Interface
The MAC transmit interface sends encapsulated TS data or frames
generated by the host processor to the Ethernet-PHY interface.
Altera Corporation 21
Preliminary
Video Over IP Reference Design
Both ports run synchronous to the main system clock. The Ethernet-PHY
interface retimes these signals to the appropriate PHY clock domains if
necessary. Table 3 shows the MAC interface.
22 Altera Corporation
Preliminary
Functional Description
TS Input Logic
The base address offset is 0x1140. Table 4 shows the TS input logic
registers.
TS Output Logic
The base address offset is 0x1160. Table 5 shows the TS output logic
registers.
Altera Corporation 23
Preliminary
Video Over IP Reference Design
Frame Buffer
The base address offset is 0x0000. Table 6 shows the frame buffer
registers
To access the data relating to a specific frame, write the buffer pointer
value to the pointer selection register. The frame content is then directly
addressable from the associated frame data locations.
The register provides two separate pointer selection and frame data
locations to allow re-entrancy issues to be avoided when processing
receive traffic and transmit traffic in different software threads.
24 Altera Corporation
Preliminary
Functional Description
Queue System
The base address offset is 0x1100. Table 7 shows the queue system
registers.
Table 8 shows additional registers that are defined to give direct access to
specific queues without having to first select the queue using the queue
select register.
Altera Corporation 25
Preliminary
Video Over IP Reference Design
Host Transmit
To transmit an Ethernet frame, request a buffer pointer from the free list
by reading from the free list queue. A negative value is returned if no
pointers are available.
When the frame payload and length have been written to the frame
buffer, generate a transmit request by writing the buffer pointer to the
host transmit queue. You may read the host transmit status bit to
determine when the transmission has completed.
If the host release mode is not set to auto release, manually return the
buffer pointer to the free list when the transmission is complete. If the
host release mode is set to auto release, the design automatically releases
the pointer to the free list when the transmission is complete. In this
mode, the host does not need to poll the transmission status flag.
Host Receive
The host processor can either poll the host receive queue level to
determine when an Ethernet frame has been received for processing, or it
can receive an interrupt.
To use the interrupt, clear the interrupt mask bit. The queue system
interrupt flag to the processor is then asserted whenever the host receive
queue is not empty. If the mask bit is set, the interrupt flag is negated
regardless of the level of the host receive queue.
When there is an entry in the host receive queue, read the buffer pointer
value from the queue. After the received frame has been processed,
release the buffer pointer to the free list.
26 Altera Corporation
Preliminary
Functional Description
De-Encapsulator
The base address offset is 0x11B0. Table 9 shows the de-encapsulator
registers.
Altera Corporation 27
Preliminary
Video Over IP Reference Design
To set the UDP destination port for a specific TS output, write the port
number of the TS output to the port select register, then write the UDP
destination port number to the UDP destination port register. Write the
enable bit to enable the matcher.
Statistics
The base address offset is 0x1200. All read only. Table 12 shows the
statistics registers.
28 Altera Corporation
Preliminary
Functional Description
Design Configuration
The base address offset is 0x11A0. Table 11 shows the design
configuration registers.
Parameters
A number of features of the reference design can be parameterized to
customize it for the desired operation. Table 14 shows the parameters
Parameter Definition
P_TARGET_DEVICE The target device, e.g., Cyclone or Stratix.
P_BUFFER_RAM_TYPE Frame buffer RAM internal memory type, e.g., M4K or M-RAM.
P_POINTERS Total number of pointers (frame buffer locations).
P_TS_OUTPUT_PORTS The number of TS outputs (set to 1 if no outputs are implemented).
Altera Corporation 29
Preliminary
Video Over IP Reference Design
Parameter Definition
P_TS_INPUT_PORTS The number of TS inputs (set to 1 if no input ports are implemented).
P_IMPLEMENT_MAC Set to 1 to use reference design MAC implementation. Set to 0 to use
the MorethanIP 10/100/1000 MAC core.
To set the parameters use the Verilog HDL include file, video_over_ip.h.
A template include file is provided in source/cyclone_demo.
Basic Demonstration
The reference design includes a basic demonstration.
f For details on how to run the basic demonstration, “Run the Basic
Demonstration” on page 40.
30 Altera Corporation
Preliminary
Demonstration Description
Figure 15. Nios II Development Kit, Cyclone Edition & Cyclone Video Development Board
Nios Development
Board, Cyclone Edition
Ethernet CAT5e
Cable
Parallel Transport
Stream Interface
Cable Cyclone Video ASI Output Cable
Demonstration Board
ASI Input Cable
The basic demonstration uses one set of boards (see Figure 15) to receive
TS and generate encapsulated Ethernet frames. A second set of boards
receives these Ethernet frames and regenerates the TS data.
Altera Corporation 31
Preliminary
Video Over IP Reference Design
Figure 16 shows the connector pinout for the TS interface to the Cyclone
Video Demonstration Board.
Pin 1 GND
TX_DAT[1] TX_DAT[0]
TX_DAT[3] TX_DAT[2]
TX_DAT[5] TX_DAT[4]
TX_DAT[7] TX_DAT[6]
TX_ENA
RX_EOP RX_LOCK[0]
RX_ENA RX_SOP
RX_DAT[1] RX_DAT[0]
GND
RX_DAT[2] GND
RX_DAT[3] GND
RX_DAT[4] GND
RX_DAT[5] RX_DAT[6]
RX_DAT[7] GND
CLK RX_LOCK[1]
An eCos driver has been created for the Video over IP reference design.
This provides the functions required by the eCos operating system to
initialise the network interface and transmit and receive network traffic.
A series of functions have also been created to generate the HTML code
served by the eCos web server. These pages can be viewed by any web
browser attached to the network.
32 Altera Corporation
Preliminary
Resource Requirements
Resource The device resource requirement for the reference design depends upon
the design parameterization. It is affected by the number of pointers that
Requirements the frame buffer uses, the number of TS input and output channels, and
the type of encapsulation/de-encapsulation required.
Memory
Module LEs
(M4K RAM Blocks)
Nios II system 3,000 15
MorethanIP 100/1000 MAC 3,300 9
Bridge 3,700 33
Memory
Module LEs
(M4K RAM Blocks)
Nios II system 3,000 15
MAC 400 2
Bridge 3,900 33
Memory
Module LEs
(M4K RAM Blocks)
Nios II system 3,000 15
MAC 335 2
TS-to-Ethernet Bridge logic 1,700 17
Altera Corporation 33
Preliminary
Video Over IP Reference Design
Memory
Module LEs
(M4K RAM Blocks)
Nios II system 3,000 15
MAC 375 2
Ethernet-toTS Bridge logic 2,300 30
System Requirements
Table 19 shows the demonstration hardware requirements.
Hardware Manufacturer
Nios II Development Kit, Cyclone Edition (or Nios II Altera Corporation
Development Kit, Cyclone II Edition)
DBGIG1 Gigabit Ethernet PHY Module Richter Industrie
Elektronik,
www.devboards.de
Cyclone Video Development Board (1) Altera Corporation
Parallel cable (for TS connection) Supplied with Cyclone
Video Development Board
USB-Blaster™ download cable Altera Corporation
34 Altera Corporation
Preliminary
Getting Started
The reference design requires a license for product ID BC01 and vendor
ID 6A7B. Contact Altera for a license.
Altera Corporation 35
Preliminary
Video Over IP Reference Design
auk_video_over_ip
demo
Contains the precompiled demonstration files.
doc
Contains the documentation.
ecos_demo
Contains the Nios II software for the web server demonstration.
lib
Contains the Quartus II models for encypted components.
quartus
Contains the Quartus II project files.
cyclone_demo
Contains the Quartus II project for the Cyclone demonstration.
cycloneii_demo
Contains the Quartus II project for the Cyclone II demonstration.
sim_lib
Contains the functional simulation models for encrypted components.
simulation
Contains the simulation scripts and waveforms.
software
Contains the Nios II project for the Cyclone demonstration.
source
Contains the source files.
avalon_system
Contains the SOPC Builder system for register access.
channel_info
Contains the transmit and receive channel information blocks.
cyclone_demo
Contains the top-level design files for the Cyclone demonstration.
ethernet_system
Contains the encapsulation and de-encapsulation functions.
frame_buffer
Contains the frame buffer and transmit and receive DMAs.
mac_wrapper
Contains the Ethernet MAC design files.
port_logic
Contains the TS interface logic.
queue_system
Contains the queue system files.
ts_ethernet_bridge
Contains the top level design files for TS-to-Ethernet bridge.
tb
Contains the testbench.
36 Altera Corporation
Preliminary
Getting Started
2. Choose Open Project (File menu) and open the Quartus II project in
the quartus\cyclone_demo or quartus\cycloneii_demo directory.
f For details on how to generate the VQM file, see the MorethanIP
10/100/1000 Ethernet MAC Reference Guide.
Altera Corporation 37
Preliminary
Video Over IP Reference Design
1. Start the Nios II IDE by choosing Programs > Altera > Nios II 5.1 >
Nios II IDE (Windows Start menu).
38 Altera Corporation
Preliminary
Getting Started
or
Altera Corporation 39
Preliminary
Video Over IP Reference Design
9. Click Finish.
f For details on how to build and run the project, see the Nios II
Development Kit Getting Started User Guide.
40 Altera Corporation
Preliminary
Getting Started
5. Connect the two Ethernet ports on the PHY boards using CAT5E
cable. The ports can either be connected directly or through a gigabit
Ethernet switch.
or
Altera Corporation 41
Preliminary
Video Over IP Reference Design
8. Monitor the output from the software using the following nios2-
terminal command:
nios2-terminal -c USB-Blaster
This monitor output shows that the device initialization process. If the
PHY auto-negotiation does not complete, check the Ethernet connection
on both boards.
42 Altera Corporation
Preliminary
Getting Started
6. Repeat the test in the other direction to check that both sides are
capable of receiving and transmitting data.
The TS data received by the first board is output by the second board. You
can connect a second TS generator and analyzer to the other pair of TS
inputs and outputs to show traffic being sent in both directions.
You can generate a test stream containing null packets by briefly pressing
button SW1 on one of the Nios II Development Board, Cyclone Edition.
LED D5 illuminates on the board. This test stream is routed to the second
Altera Corporation 43
Preliminary
Video Over IP Reference Design
board using a different UDP/IP socket so does not interfere with the first
stream. LED D6 illuminates on the second board to indicate that the TS
data is being received. Press the button again to stop the test generator.
LED Use
D0 Flashes to indicate the 125-MHz system clock is running.
D1 Flashes to indicate the 50-MHz processor clock is running.
D2 Flashes to indicate the 27-MHz TS clock is running.
D3 Illuminates when TS input from Cyclone Video Demonstration Board is
valid.
D4 Illuminates when TS output to Cyclone Video Demonstration Board is
valid.
D5 Illuminates when the second test TS data is being generated.
D6 Illuminates when received the test TS data is valid.
Button Use
SW0 Hold down during the download of the software executable to set the
board number to 01 instead of 00.
Connector Use
ASI_RX0 TS input.
ASI_RX1 TS input (can be used instead of ASI_RX0 if cable equalizer is
required).
ASI_TX TS output.
44 Altera Corporation
Preliminary
Getting Started
Connector Use
SDI_TX TS output from test generator.
SDI_RX TS input for test checker. LED D2 Illuminates when valid packets
are detected.
LED Use
D0 Illuminates when valid packets are detected on ASI_RX0.
D1 Illuminates when valid packets are detected on ASI_RX1.
D2 Illuminates when valid packets are detected on SDI_RX.
D3 Illuminates when valid packets are output on ASI_TX.
DIP
Switch Use
S5
8 Closed (default): ASI output taken from parallel cable; open: ASI output
taken from ASI input.
7 Open (default): pattern generator creates 188 byte packets; closed:
204 byte packets.
5 Open (default): pattern generator creates ~33 Mbps; closed: pattern
generator creates ~204 Mbps
Altera Corporation 45
Preliminary
Video Over IP Reference Design
or
Acquire an IP Address
By default, the design attempts to acquire an IP address using the
dynamic host configuration protocol DHCP. If a DHCP server is not
present on the network, an IP address is created for the demonstration
that is based on the least significant byte of the board's MAC address,
using the reserved 169.254.197 subnet.
When the board has acquired an IP address, you can ping it from a PC
attached to the demonstration network.
46 Altera Corporation
Preliminary
Getting Started
The demonstration uses two systems to show the transfer of video traffic
over the network. To establish communication between the boards, the
first board needs to know the IP address of the second. Enter this address
information in to the Destination IP box and click Submit.
When the destination IP address has been entered and accepted, click on
the link to go to the main configuration page.
Altera Corporation 47
Preliminary
Video Over IP Reference Design
The global parameters that you can change are the encapsulation type
(UDP or RTP) and the number of transport stream packets per frame.
1 Ensure that the encapsulation type is set to the same value on all
boards in the demonstration system. The number of transport
stream packets per frame value only has to be set for boards that
are transmitting TS data to Ethernet.
For the TS to Ethernet ports, you can modify the target IP address, UDP
source and destination ports, IP type of service (TOS), and IP time to live
(TTL) fields. Each port can also be enabled or disabled.
For the Ethernet-to-TS ports, the target IP address and UDP port can be
modified. Each port can also be enabled or disabled.
1 The IP address should match the address of the board for unicast
traffic, or be set to an IP multicast address for multicast traffic.
48 Altera Corporation
Preliminary
Getting Started
4. On the Configuration web page for the first system, click on the TS-
to-Ethernet port 0 link to open the state editor for the port.
6. Click Submit.
7. The TS data is now transferred from the first system to the second
and output to the analyzer.
8. View the Stats page for both boards to see the reported statistics.
Altera Corporation 49
Preliminary
Video Over IP Reference Design
Copyright © 2005 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company,
the stylized Altera logo, specific device designations, and all other words and logos that are identified as
trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera
Corporation in the U.S. and other countries. All other product or service names are the property of their re-
spective holders. Altera products are protected under numerous U.S. and foreign patents and pending
101 Innovation Drive applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products
San Jose, CA 95134 to current specifications in accordance with Altera's standard warranty, but reserves the right to make chang-
(408) 544-7000 es to any products and services at any time without notice. Altera assumes no responsibility or liability
arising out of the application or use of any information, product, or service described
www.altera.com herein except as expressly agreed to in writing by Altera Corporation. Altera customers
Applications Hotline: are advised to obtain the latest version of device specifications before relying on any pub-
(800) 800-EPLD lished information and before placing orders for products or services.
Literature Services:
literature@altera.com
50 Altera Corporation
Preliminary