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Courses In Electrical Engineering

Volume II DIGITAL ELECTRONICS CHAPTER EIGHT: SEQUENTIAL LOGIC PART B: COUNTERS

By J-P. NGOUNE DIPET I (Electrotechnics), DIPET II (Electrotechnics) DEA (Electrical Engineering) Teacher in the Electrical Department, GTHS KUMBO, Cameroon.

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Chapter Eight

COUNTERS
8.0 Specific objectives: At the end of this chapter, the student will be able to: Define asynchronous and synchronous counters; Design asynchronous and synchronous counters using flip-flops; Know the use of counters in digital systems.

8.1 Introduction: A counter is an electronic device which is able to generate an orderly sequence of binary numbers. The addresses which command digital circuits as decoder, multiplexer, demultiplexer etc. are most of the time generated by counters. There two main basic types of counters: asynchronous counter and synchronous counter. Counters are designed using flip-flops, usually J-K flip-flops. Asynchronous counters functions in such a way that the clock signal does not affect all the flip-flops at the same instant; in fact, the clock signal triggers the first flipflop which in his turn trigger the second flip-flop using its output signal. The second flip-flop in his turn will trigger the third one, and so on, till the last flip-flop. It is just like the triggering signal was being propagated from the first flip-flop to the last. For this reason, asynchronous counters are also called propagation counters. The flip-flops of a synchronous counter are all triggered by the same clock signal at the same instant. In fact, all the flip-flops function in synchronism with the clock signal. The outputs of all the flip-flops change their status at the same instant.

8.2 Asynchronous counters: Let us consider the following binary count sequence. The numbers are coded in four bits. Q0 is the LSB and Q3 is the MSB.

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Q3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0

Q2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0

Q1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1

Q0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2

It can be noticed that each bit in this four bit sequence toggles when the bit before it (the bit having a lesser significance or place weight), toggles from 1 to 0. Small arrows are used to indicate those places in the above count sequence. So, to design an asynchronous counter which is able to generate the above sequence of numbers, we need to determine how to connect the clock inputs of each of the four J-K flip-flops ( each flip-flop generating one bit) in such a way that each bit will toggle only when the bit just before it is transitioning from 1 to 0. The easier way of doing that is to use flip-flops with negative edge triggering. The clock input of each flip-flop will simply be connected to the non complemented output Q of the flip-flop situated just before it (Flip-flop having one lesser place weight). In this condition, each flip-flop will toggle any time the output of the flip-flop

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one place lesser weighted than it is transitioning from 1 to 0 (negative edge). Such a connection is done as shown in the following figure.
Vcc

Q0

Q1

Q2

Q3

Figure 8.1: Four bits asynchronous counter.

From the functioning of this asynchronous counter, the following waveforms can be generated.
Clock

Q0

LSB

Q1

Q2

Q3

MSB

10

11

12

13

14

15

Each of the signals generated by the outputs of the flip-flops is used as the clock signal for the following flip-flop. So, the falling edge of each signal causes the output of the following flip-flop to toggle. It can also be clearly observed that those waveforms sketch the count sequence from 010 (0000) to 1510 (1111). When the maximum number of the sequence is reached, the counter is automatically reset (brought back to 0).

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8.3 Counter modulus: The modulus of a counter can be defined as the number of different states that it occupies within a count sequence. The four bits counter above has 16 different states (from 0000 to 1111), therefore its modulus is 16. In general, N being the number of flip-flops used to design a counter, the modulus of the counter is given by the following formula: Modulus = 2N

Therefore, to add the modulus of a counter, we just need to add the number of counters used to design it. Exercise 8.1: Conceive an asynchronous counter modulus 8, modulus 32. 8.4 Counters having modulus < 2N: It is possible to conceive a counter which is such that its modulo is not a power of 2 as in the cases above. For this issue, asynchronous inputs presented in the previous chapter will be used. Let us realise an asynchronous counter modulo 5 ( the count sequence goes from 000 to 100). 22 = 4 < 5; 23 = 8 > 5. Therefore, we cannot use 2 flip-flops to design the counter. The suitable number of flip-flops is 3. The three flip-flops should be connected in such a way that, the count sequence will end at 410 (100) instead of ending at 710 (111) as expected. It means that the counter should be obliged to reset when the binary number 101 (510) occurs. 1 Q2 0 Q1 1 Q0

To achieve this task, one method consists in gathering all the bits of the number which are in high logic state to the input of a NAND gate. The output of that NAND gate (which is low only when all its inputs are high) will be used to reset the counter when the number 101 occurs. The NAND gate is used in the case were the asynchronous inputs CLR of the flip-flops function in low logic level. If they were
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functioning at high logic level, AND gate would have been used in such a way that, when all its inputs are high, it outputs a high logic level that reset the counter. The following figure shows how the connection can be done.
Q0 Vcc Q1 Q2

K
CLR CLR

K
CLR

Clock

Figure 8.2: Asynchronous counter modulo 5. From the functioning of the above asynchronous counter modulus 5, the following waveforms can be generated.

Clock

Q0

Q1

Q2

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The output Z of the NAND gate is connected to the CLR input of the three J-K flip-flops. When Z = 1, the counter is not affected. However, when Z = 0 (Q0 = 1 and Q2 = 1), the counter is reset. Therefore, a new count sequence can start. The count sequence is as follows: Q2 0 0 0 0 1 0 0 Q1 0 0 1 1 0 0 0 Q0 0 1 0 1 0 0 1 The number 101 does not occur, for the counter is immediately reset after 1002.

Exercise 8.2: Conceive an asynchronous counter modulus 10, modulus 15, modulus 20.

8.5 Advantages and disadvantages of asynchronous counters: The main advantage of the synchronous counter is its simplicity as far as the conception is concern. However, this type of counter has a great problem: the ripple effect. This is the time delay due to the propagation of the signal throughout the flipflops which the counter is made up of. The ripple effect can cause error in computer circuits. To avoid the ripple effect, another type of counter has been designed: The synchronous counter.

8.6 Synchronous counter: A synchronous counter, in contrary to an asynchronous counter functions in such a way that all its flip-flops toggle at the same instant, because they are triggered by the same clock signal.

8.6.1 Principle of an asynchronous counter: Let us consider again a four bit count sequence:

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Q3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0

Q2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0

Q1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1

Q0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2

While examining this count sequence, it can be noticed that, for a bit belonging to a given rank to toggle (Q0, Q1, Q2, Q3), the bits of all the previous rank lesser weighted than it should be at high logic level. This property can be exploited to design a synchronous counter, as shown by the following diagram.
Vcc

Q2

Q1

Q0

Clock

Q2

Q1

Q0

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The flip-flop Q0 toggles on every rising edge of the clock pulse. The flip-flop Q1 toggles only when Q0 is high. The flip-flop Q2 toggles only when Q0 and Q1 are high. We can also notice that all the flip-flops are triggered by the same clock signal. Each of the higher order flip-flops are made ready to toggle (both J and K inputs are high) if the Q input of all the previous flip-flops are high. Otherwise, the J and K inputs for that flip-flop will be both low, placing it into the latch mode where it will maintain its present output state. Since the first flip-flop (LSB) needs to toggle at every clock pulse, its J and K inputs are connected to Vcc. The following equations can be deduced. J0 = K 0 = 1 J1 = K 1 = Q 0 J2 = K2 = Q0Q1 J3 = K3 = Q0Q1Q2 Generally Jn =Kn = Q0Q1Q3Qn-1 Exercise 8.3: Design a synchronous counter modulo 8.

Remark 8.1: For the conception of synchronous counters having modulo < 2N, N being an integer, asynchronous inputs should be used in the same manner as they were used for asynchronous counters.

Exercise 8.4: Design a synchronous counter modulus 6.

8.6.2 Shift register A register can be defined as a set of flip-flops connected together and intended to store a memory word. Each flip-flop of the register store one bit. A shift register is a set of register connected together and intended to be used for the transfer of data. The transfer of data can be serial or parallel. In serial transfer, data are sent one bit after another over long distances. In parallel transfer, a whole memory word is transmitted at once, over a relatively short distance.
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Serial data transmission over a distance of meters to kilometres, uses shift registers to convert parallel data to serial form. Serial data transmission replaces many slow parallel wires with a single high speed transmission line. Basic shift registers are classified by structure according to the following types: Serial in / Serial out; Parallel in / Serial out; Serial in / Parallel out; Parallel in / Parallel out; Ring counters.

a. Serial in/ serial out shift register: Data are sent in the register one bit after another and are sent out from it one bit after another. The following diagram illustrates this type of transfer.

Data in

Q0

Q1

Q2

Data out

Clock

Clock

Clock

Clock

Figure 8.3: Serial in / serial out shift register using D flip-flops.

Once the pulse of the clock signal occurs, the bit available at the input of the first flip-flop is shifted to that of the next flip-flop. The same process is repeated till the last flip-flop. J-K flip-flops can also be used to achieve the same task. The diagram is done as follows.

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Data in

Q0

Q1

Q2

Data out

Clock

Clock

Clock

/Q0

/Q1

/Q2

Clock

Figure 8.4: Serial in/ Serial out shift register using J-K flip-flops.

b. Ring counter: A ring counter is obtained when the output of a shift register is fed back to the input. One of the most known ring counter is the Johnson counter. The principle of the Johnson counter is presented by the following diagram.

Q0

Q1

Q2

Clock

Clock

Clock

Clock

Figure 8.5: Johnson counter.

During the functioning of the Johnson counter, a single bit is being transferred from one flip-flop to another in a ring made up of the flip-flops connected together. This functioning can be described using the following table ( it is assumed that initially Q0 = 1, Q1 = Q2 = Q3 = 0).

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Q0 1 0 0 0 1 0 0 0

Q1 0 1 0 0 0 1 0 0

Q2 0 0 1 0 0 0 1 0

Q3 0 0 0 1 0 0 0 1

Clock 1 2 3 4 5 6 7 8

The following waveforms can be deduced from the functioning of the Johnson counter.
1 Clock 2 3 4 5 6 7 8 9 10 11 12 13

Q0

Q1

Q2

Q3

8.7 Conclusion: The topic of this chapter was the counter, which is a direct application of the flip-flops studied in the previous chapter. Asynchronous and synchronous counters have been studied. The notions of memory and data transmission have been introduced through the study of the shift register. The following chapter is focused on the study of storage devices and the presentation of the properties of integrated circuits.

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REVIEW QUESTIONS
1. Give the difference between a synchronous counter and an asynchronous counter. 2. Give the difference between serial transmission and parallel transmission of data. 3. Give two advantages of series transmission over parallel transmission. 4. Which type of transmission is used by the following: USB flash, LPT port? 5. Conceive a synchronous counter modulus 9. 6. Conceive an asynchronous modulus 10.

Problem 1: Study of a seven segments display. The circuit below is used to display the first 8 symbols of the digital system of numeration. The system is composed of: A modulo 8 JK flip flop asynchronous binary counter; A 3/7 (3 inputs and 7 outputs) decoder; A seven segments display used to display used to display the first 8 symbols as shown below.

01234567
a a b c d e f g

Q3 COUNTER Q2 Q1

f g

e d

3/7 Decoder

Display

a, b, c, d, e, f, g are the seven segments of the display. Q3, Q2 and Q1 are the outputs of the asynchronous counter (Q3 is the most significant bit while Q1 is the least significant bit). 1. Draw the truth table of the JK flip flop. 2. Draw the complete electric diagram of the asynchronous counter using the JK flip flops.

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3. Draw the truth table of the decoder following the model given below. Q3 0 0 Inputs Q2 0 0 Q1 0 1 a 1 b 1 c 1 Outputs d 1 Display e 1 f 1 g 0 0 1

4. Using the Karnaughs map, give the simplified logic expression of each output of the decoder. 5. Draw the logigram of the display 0 using NAND gates of two inputs, taking Q1, Q2 and Q3 as inputs variables.

Problem 2: Study of a JK flip-flop According to the JK flip-flop truth table established in the previous exercise, complete the following chronogram. Initially, Q = 0.
Clk

t J 1 0 K 1 0 Q t t

Problem 3: Counter The circuit of the following figure represents a counter. The flip-flops are positive edge triggered.

D H

Q3

D H

Q2

D H

Q1

D H

Q0

/Q3 Clock

/Q2

/Q1

/Q0

Figure 1.

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1. Precise the nature of this counter (synchronous or asynchronous). 2. State the difference between series transfer and parallel transfer. 3. Draw the wave forms of Q3, Q2, Q1, Q0 knowing the initial state Q3 = 1, Q2 = Q1= Q0 = 0.

References: 1. Digital systems, principles and applications, Ronald J.Tocci, 3rd edition, Prentice-Hall inc., Englewood Cliffs, New Jersey , USA,1985. 2. Lessons In Electric Circuits Volume IV Digital, Tony R. Kuphaldt, Fourth Edition, 2007, www.allaboutcircuits.com , www.ibiblio.org/obp/electricCircuits. 3. Cours de systmes logiques, Notes de cours, Premire anne du gnie lectrique, ENSET de Douala, J.C Tsokezo, 2004-2005. 4. Past questions of official examinations by the Cameroon General Certificate of Education board.

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