Beruflich Dokumente
Kultur Dokumente
12.1
Nov 2007
12.2
Nov 2007
Step 2: Construct Karnaugh maps for each input from the state transition table and the flip-flop transition table
State Transition Table
Procedure Step 1: Start with the transition table of the flip-flop to be used
E.g. D-type
Output Transition Required 0 to 0 0 to 1 1 to 0 1 to 1 Input D 0 1 0 1
Current State Q2 Q1 Q0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
12.3
Nov 2007
12.4
Nov 2007
D2
Q2\Q1Q0 0 1 00 0 1 01 0 1 11 1 0 10 0 1
Q2\Q1Q0 0 1
00 0 1
01 0 1
11 1 0
10 0 1
D1
Q2\Q1Q0 0 1
00 0 0
01 1 1
11 0 0
10 1 1
Q2\Q1Q0 0 1
00 0 0
01 1 1
11 0 0
10 1 1
D1 = Q1. Q0 + Q1. Q0 = Q1 Q0
D0
Q2\Q1Q0 0 1
00 1 1
01 0 0
11 0 0
10 1 1
Q2\Q1Q0 0 1
Nov 2007
00 1 1
01 0 0
11 0 0
10 1 1
12.6
D0 = Q0
Nov 2007
12.5
It may be necessary to design counters which count sequences other than a binary count Examples:
C1 1D Q0 Q1 Q2
Q2 Q1 Q2 Q1 Q0 Q2 Q1 Q0
The design procedure presented for binary counters can be extended to arbitrary code counters
12.7
Nov 2007
12.8
Nov 2007
Example
A 3-bit counter to count the decimal sequence 0, 2, 5, 6. Counting sequence: Decimal Q2 Q1
0 2 5 6 0 0 1 1 0 1 0 1
Current State Q2 0 0 Q1 0 1 0 1 Q0 0 0 1 0 0 1 1 0
Q0 0 0 1 0
1 1
Undefined States
In this example, some of the possible 8 states are undefined What happens if the circuit gets into one of the undefined states?
e.g. at power-on
State Diagram:
000 010 101 110
12.9
Nov 2007
12.10
Nov 2007
Q2\Q1Q0 0 1
Q2\Q1Q0 0 1
Q2\Q1Q0 0 1
00 0 X
00 1 X
00 0 X
01 X 1
01 X 1
01 X 0
11 X X
11 X X
11 X X
10 1 0
10 0 0
10 1 0
CLOCK Q0 Q1 Q2 D0 D1 D2
C1 1D Q0 Q1 Q2
D1
D0
C u rre n t S ta te Q2 0 0 1 1
E1.2 Digital Electronics I 12.11 Nov 2007
N e x t S ta te Q 2+ 0 1 1 0 Q 1+ 1 0 1 0 Q 0+ 0 1 0 0
12.12
Q1 0 1 0 1
Q0 0 0 1 0
Q2+ 0 0 1 0 0 1 0 0
D2
Q2\Q1Q0 0 1 Q2\Q1Q0 0 1
00 0 0 00 1 0
01 0 1 01 0 1
11 0 0 11 0 0
10 1 0 10 0 0
D1
D0
Q2\Q1Q0 0 1
00 0 0
01 0 0
11 0 0
10 1 0
D0 = Q2. Q1. Q0
001
000
010
101
110
The term Q 2. Q1. Q 0 can be re-used to simplify the circuitry This implementation is a bit more complicated but will always work (unlike the "don't care" implementation)
12.13
Nov 2007
12.14
Nov 2007
0 0 1
CLOCK Q0 Q1 Q2 D0 C1 1D Q0 Q1 Q2
0 1 0 1
0 0 1 0
0 1 1 0
1 0 1 0
0 1 0 0
CLOCK C1 D0 1D
ROM
D1 D2
Q0 Q1 Q2
Q0 Q1 Q2
ROM
D1 D2
12.15
Nov 2007
12.16
Nov 2007