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Lecture #4

Assignment

#1 due today! Assignment #2 to be posted right thereafter DIS 101 (Th 11am-noon) in GPB (Genetics and Plant Biology) 107 starting next week Office hours of TAs in 557 Cory Labs start next week (Monday)

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Last

lecture

Basic metrics for IC design Manufacturing

Todays

lecture

Design Rules Introduction to switch logic

Reading

(2.3, 3.3.1-3.3.2)
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(well contacts)

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Interface

between designer and process

engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules)

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Intra-layer

Widths, spacing, area

Inter-layer

Enclosures, distances, extensions, overlaps

Special

rules (sub-0.25m)

Antenna rules, density rules, (area)

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Dimensionless layout entities Only topology is important

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N Well PMOS

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VDD 2

Contacts

In Polysilicon

Out Metal 1

NMOS GND

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Share power and ground

Abut cells

Connect in Metal

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An MOS Transistor
G |VGS| S D S

A Switch!
|VGS| |VT|

Ron D

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G |VGS| S D

Ron S |VGS| < |VT| D S |VGS| > |VT| D

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G |VGS| S D

Roff S |VGS| < |VT| D

Ron S |VGS| > |VT| D

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NMOS Transistor
G VGS > 0 S X Y Y=Z IF X=1
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PMOS Transistor
G VGS < 0

D Ron Z Y

S X Ron

Z Y=Z IF X=0

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V DD

V in

V out CL

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V DD

V DD Rp V out

V out Rn

VOL = 0 VOH = VDD VM = f(Rn, Rp)

V in = V DD
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V in = 0
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VOH

= VOL = VIL = VIH = NMH = NML = VM =

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VOH

= VDD = 2.5V VOL = 0V VM = 1.2V VIL = 1.05V VIH = 1.45V NMH =1.05V NML = 1.05V
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tpHL = f(RonCL) = 0.69 Rn CL

(a) Low-to-high
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(b) High-to-low
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Full

rail-to-rail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power dissipation Direct path current during switching

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VDD 0 VDD VGS

D

0? CL

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VDD VGS
S

VDD VDD 0? CL VDD ? VGS

D

0? CL VDD ?

VDD VGS
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CL

VGS

CL

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In

Out CL

For

some given CL:

How many stages are needed to minimize delay? How to size the inverters?
Anyone
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want to guess the solution?

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Get

fastest delay if build one very big inverter

So big that delay is set only by self-loading

Likely

not the problem youre interested in

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Someone has to drive this inverter

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Need

to have a set of constraints key to:

Constraints

Making the result useful Making the problem have a clean solution
For

sizing problem:

Need to constrain size of first inverter

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You

are given:

A fixed number of inverters The size of the first inverter The size of the load that needs to be driven
Your

goal:

Minimize the delay of the inverter chain

Need

model for inverter delay vs. size

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Delay: tpHL = (ln 2) RNCL

tpLH = (ln 2) RpCL CP = 2WCg 2W

Assume we want equal rise/fall delays tpHL = tpLH

Need approximately equal resistances, RN = RP PMOS approximately 2 times larger resistance for same size; Must make PMOS 2 times wider, WP = 2WN = 2W tp = (ln 2) (Rinv/W) CL with Rinv resistance of CN = WCg minimum size NMOS

Loading on the previous stage: Cin = WCginv = W(3CG)

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2W W

R = Rinv/W Cint = W(3Cd) = WCdinv

Cint

CL

Replace ln(2) with k (a constant): Delay = kR(Cint + CL) Delay = k(Rmin/W)(WCdinv + CL)
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Delay

Cin W

2W

Cint

CL
Load

Delay = kR Cin(Cint/Cin+ CL /Cin) = kRminCginv[Cdinv/Cginv + CL/(WCginv)] = Delay (Internal) + Delay (Load) Cdinv/Cginv = = Constant independent of size
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Cint = Cin ( 1 for CMOS inverter) f = CL/Cin electrical fanout tinv = kRminCginv tinv is independent of sizing of the gate!!!
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