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Annexure ll Homework title/No: Course Code: ECE-304 Course Instructor: Ms.

Ritu Date of Allotment: Date of Submission: 22/04/10 Students Section No: H6802 Declaration: I declare that this is my individual work. I have not copied fron any other students work or from any other sourse except where due acknowledgement is made explicitly in the text , nor has any part has been written from me by another person. Students Signature Ramjee prasad Roll No: 07/04/10 RH6802B54 Assignment -3

1. What is the purpose of low pass filter in BPSK demodulator model? What determines its bandwidth? Solution: Block diagram of BPSK:


Balance d


level converter

Binary output

Coherent carrier recovery

Clock recovery

The above circuit arrangement is for BPSK demodulator or BPSK receiver. In this the LPF used is set at cut off frequency. And this LPF blocks all the frequency components Which are above c. it results in the output to appear in the form of logic 1and logic 0. Their would be two outputs of balanced modulator: (1) (2) 1/2 cos2ct/2 1/2+cos2ct/2

When the LPF comes in to role having cut-off frequency c then the output becomes 1/2 volt i.e logic 1

(2) 2 volt i.e logic 0

Bandwidth: The bandwidth of bpsk is determined by the bit rate of the system

Minimum nyquist bandwidth

0 0

Fundamental frequency = Fa = Fb/2 Output of modulator = sinat.sinct = 2/2 sinat.sinct =1/2[ cos 2 (fc-fa)t cos2(fc+fa)t] Bandwidth = (fc+fa) - (fc-fa)

Upper band Bw = 2fa = 2(fb/2)

lower band

Bandwidth = fb

Where fb = Bitrate Q(2) Draw the DPSK modulator diagram and then determine the output phase sequence for the following input bit sequence : 00110011010101( assume reference bit=1). Solution: DPSK modulator: It is an alternate form of digital modulation where the binary input information is contained in the difference between two signals. If the data bit firstly with reference bit is same then the output is 1 otherwise 0.

XNOR gate Data input

Balance modulator


1-bit delay


A 0 0 1 1

B 0 1 0 1

o/p 1 0 0 1

0 0

1 0

1 1

0 1 1 1

0 1 1 1

0 0 1 1

0 0 1

0 1

0 0

1 1 1

1 1

0 0 0

1 1

Q(3)Explain the significance of the I and Q channels in a

QPSK modulator.

Solution: QPSK modulator: In ouadrature phase shift keying (QPSK) two successive bits in the data sequence are grouped together. The reduces the bit rates are or signaling rate and reduces the bit rate or signaling rate(i.e fb)and thus reduces the bandwidth the channel. By this method the frequency of the carrier needed is also reduced. Sin ct I/P


Bit splitter



90pha se shift

summe r



Balanced modulator


Q 0 0 1 1

I 0 1 0 1

output phase -135 -45 +135 +45

o/p of the summer Cosct +sin ct Cosct -sin ct sin ct- Cosct -sin ct- Cosct


(4) For the QPSK demodulator, determine the I and Q bits for an input signal ( -sinc t + cosc t). Solution: For the QPSK demodulator is product detector 1 (i- channel) = cosct-sinct).sinct = - sin2 ct+ sinct. cosct = -[1- cos2ct/2]+[2 sinct +cosct] = -1/2 + cos2ct/2+1/2[ sin(c+c)t+ sin(c+c)t] = -1/2 + cos2ct/2+1/2sin2ct+0

When it passes through LPF,the final output comes as:

o/p = -1/2v logic 0 Product modulator 2(Qchannel) = cosct (cosct-sinct) = cos2ct sinct. cosct

= [1+cos2ct/2]- 1/2[ sin(c+c)t+ sin(c-c)t] = 1/2+ cosct- sin2ct/2-0 When it passes through LPF the final o/p comes as: o/p = 1/2v=logic 1 Q( 5): Which technique is more preferred OQPSK or QPSK? Give reasons to support your answer . Solution: The offset QPSK technique is more preferred than the simple QPSK technique. In the QPSK technique when there is two bit change the phase shift is more than 90 degree as given in the thruth table:

phase o/p

0 0 1 1

0 1 0 1

-135 -45 +135 +45

Where QPSK eliminates the condition of two bit change to limit the maximum phase shift to a value 90 degree.