PWM-Inverter Drive Control operating with a standard Personal Computer

Wolfgang Frank Federal Armed Forces University 85579 Neubiberg - Germany

Abstract: Today, often special and complex computing systems are common in laboratories for investigations of inverter drive control. But it is also possible to control drives using a simple personal computer (PC). With such systems, even PWM control methods can be realized. A system, which complies with these demands is described. Realizations about the feasibilities, e.g. the maximum pulse frequency, and first practical results are presented. are often missed. So, normally assembler or low level language programs must be generated for the complete control system, even for parts, which are not time-critical . Thus, installation and operation of these high performing test drives take a high expenditure of man power. Therefore, a simpler arrangement for investigations of inverter drive systems was searched. We found out, that modern PC - by adding some components - may be qualified to handle all tasks of the control unit of fig. 1.

1. Introduction
In drive systems, specially developed, high performing computer systems are mostly used. They contain digital signal processors (DSP) and/or microcontrollers (C). For development and investigation, they still need an additional host, such as a personal computer (PC) is. The principle of such a system is

2. Concept using a standard PC solely

2.1. Hardware equipment Fig. 2 shows an arrangement for such an inverter drive system. The PC must contain a Pentium processor (or comparable unit), desirably clocked with 166 MHz or higher. For acquisition of the

Figure 1: System with special control unit for drive control and additional PC for communication and service routines shown in fig.1. The controller manages and performs all procedures for inverter and machine. Additional components, as e.g. timers, A/D-converters and I/O-ports, are needed. In C/DSP some of these elements may be integrated ([7], [8]). The installed PC works like a tool to provide a suitable environment. With a system of fig.1, it is possible to compute complex control strategies even for PWM-inverters in real-time. But these systems demand high development costs of hardware. Programming and data transfer of C/DSP require an extensive environment, as development kit, assembler, linker, etc. But important tools like debugger or high level language compiler Figure 2: Drive system with a standard PC for all functions analogue measurement signals (A/D-conversion), input and output of digital signals (firing signals, state feedback, etc.), and timer functions a high speed multi-I/O card must be inserted into the PC. The card may be a commercial one. Of course, the measuring transducer and firing amplifier stay the same as in other systems. So, the complete drive control may be performed without any further hardware. On the other hand, the integration of special chips for drive functions is also possible, but it demands hardware developments with an expenditure similar to those needed in fig.1.

First considerations and tests resulted in, that during on-line operation data input via keyboard or data output via screen must be evidently restricted. Nevertheless, the whole system still gains its whole capability at off-line tests or simulations and keeps its advantages concerning the programming facilities. 2.2. Software and operating system for on-line operation DOS as a single task operating system was selected. For DOS, a big variety of hardware drivers and software is available. In contrast to advanced multitasking operating systems, both real-mode and protected-mode operation are possible in DOS. In protectedmode, another way of address computation is necessary, because the tasks arent allowed to influence each other. Therefore, every task needs its own corresponding operation environment, which contains the Interrupt Descriptor Table (IDT), stacks, registers and other protected-mode specific tables and structures [10]. This causes an evident expenditure of additional computing. For high speed operation, especially for fast interrupt processing, real-mode operation must be used. So, extended memory managers, such as Microsofts EMM386.EXE, arent allowed to be installed. Because of the time-critical processes, which the processor has to cope with in real-time, even the act of switching between several possible tasks would take too much time. Consequently, multitasking operating systems are not suited for these systems. In order to concentrate on the main targets, the execution of Terminate and Stay Resident (TSR-) programs, such as mouse drivers, must be prevented. With this system, the programming of nearly all control procedures may be performed using common high level languages (C, Pascal, etc.). The use of high level languages effects short development time and gives advantages for teaching or operating efforts. The students/operators are enabled to generate and test or simulate programs by themselves using the same routines, which are programmed for inverter operation. The resulting solution depends on the compilers facilities for using the instruction set of the used processor type (386, 486, Pentium, etc.). But different compiler (e.g. Borland, Microsoft, GNU, etc.) compile the same program in a different way. Therefore, the solution also depends on the compiler itself. Besides, extremely time-critical processes can be realized by assembler programming. If off-line process simulations need more memory, the operating system may be switched into protected-mode. The change from real-mode to protected-mode is no problem for software in high level languages. And even the reorganization of assembler parts is fairly uncomplicated.

there are up to 256 different interrupts to handle with. Generally, these interrupts are divided into hardware interrupts and software interrupts. Software interrupts are caused by an explicit call of an interrupt routine during the programs run time. They are applied to events, which always occur at well defined instants. Therefore, they cant be used in processes with stochastic events. For the recognition of stochastic events, like income of data, hardware interrupts are used. They are triggered by external hardware components and surveilled by Programmable Interrupt Controllers (PIC). In PC-systems, only 15 external hardware sources can cause an interrupt, so the rest are software triggered interrupts. But not all Interrupt Request lines (IRQ) of the PIC are occupied initially by the system. Some can be used by peripheral components and it is also possible to replace nearly every interrupt-routines by individual ones.

Figure 3: principle of interrupt driven operation in PC architecture (ISR = Interupt Service Routine) in realmode Fig. 3 shows the process of interrupt handling of a PC system in case of a hardware interrupt caused by a timer termination at IRQ3 in real-mode. After having counted down to zero, the timer output rises high, what invokes a high signal at pin INTR of the processor. The processor itself answers with an interrupt acknowledge signal back to the PIC. The processor stores its registers on the stack and jumps into the corresponding interruptroutine. After the interrupt return command (IRET) the processor loads the registers from the stack again, returns to its last routine and continues with the next instruction. In PC-systems operating in real-mode, the start address of all interrupt-routines is stored in the IDT. After the detection of an interrupt, the processor receives the number of the interrupt and multiplies it with 4. The result is the address of the IDT entry for this specific interrupt. The table itself begins at 000h and every entry contains two words of 2 bytes each, representing the memory segment and the offset of the start address of the interrupt-routines. Fig. 4 shows the structure of the IDT [9]. In PC-systems, hardware interrupts are located from interrupt type

3. Realization
3.1. Interrupts in PC systems The generation and the output of the pulse pattern is realized by the use of timers generating hardware interrupts. Unlike in C, the handling of interrupts is more difficult in PC systems, since

8 to 15 (PIC 1, partially shown in fig. 4) and from 70 to 77 (PIC 2). The remaining interrupt types are shared by internal processor interrupts (e.g. division by zero), interrupts of the operating system and the BIOS (e.g. for mass storage media), and individually programmable software interrupts.

Figure 4: Structure of the Interrupt Descriptor Table (IDT) Although there is a Programmable Interval Timer (PIT) already wired with the PCs PIC on the motherboard (IRQ0), it is not recommended to use it. There are important system functions, such as hard disk drive and floppy disk drive operation, which are triggered by the system timer. Therefore, it is not possible to replace that interrupt-routine by another one. It is only possible to chain an individual interrupt-routine to the existing routine of the operating system. As a consequence, the duration of working out a modified interrupt 8 (i.e. individual system timer interrupt-routine for (IRQ0) stays longer than another modified hardware interrupt-routine, like e.g. interrupt 11 (= COM2 on IRQ3). Thus, an additional timer is necessary. The timer should desirably be clocked with 1 MHz or higher in order to obtain a suitable resolution of interrupt intervals. Most of the commercial timer plug-in cards, even the lowest cost ones, meet this demand. 3.2. Setup and programming of peripheral hardware Every peripheral component is related to a base address. It is not relevant, if this component is a discrete chip or a complete unit, like a plug-in card. Therefore, hardware programming means to write on or to read from those base addresses. Unlike peripheral motherboard-mounted chips, plug-in cards often contain dip switches to set the base address. The output of the I/O-cards timer must be connected directly with the desired IRQ of the ISA-slot. Many I/O-cards provide an interrupt selection via jumper bar. In any other case, a dummy ISA plug-in card must be inserted, which the timer output is connected to on the desired

IRQ. In the used system, the timer is initialized for single shot interrupt and 16-bit operation (mode 0) ([1], [2]). This provides both a maximum range of time intervals as well as a suitable signal processing. The control data and the data concerning the interval length is transferred to the plug-in card via ISA-bus and loaded into the corresponding base addresses. The Programmable Interrupt Controller (PIC) decides, whether an interrupt is serviced or not. Since the computation must concentrate on inverter control at on-line operation, other interrupts must be disabled in order to get no delay of the important interrupt routines. That will be achieved by writing in the interrupt mask register of the PIC ([3], [4]). Masking of interrupts means, that these interrupts will not be serviced in case of a high signal being detected at its request line. Thus, only the interrupt lines, which are related to the keyboard (IRQ 1) and the line, which the plug-in timer works on (e.g. IRQ 5), are allowed to be enabled. This minimum number of interrupts cares for a concentration of computation on the control tasks. The input/output of digital signals, such as the output of firing signals or the input of failure signals, is managed by the Programmable Peripheral Interface (PPI), which may be located on a multi-I/O-card mentioned above. Most cards use Intels chip 82C55A, which is easily programmable for bidirectional operation ([5], [6]). 3.3. Interrupt programming Since low level interrupt programming in assembler is very complex, many high level languages provide convenient commands or routines to manage it. An example of an individual interrupt routine in C++ syntax will be demonstrated. #include <dos.h> /* interrupts, outportb */ #include <.....> /* other functions/procedures being used */ #ifdef __cplusplus /* asking for compilation mode C <--> C ++*/ #define __CPPARGS ... #else #define __CPPARGS #endif int intnr = 0x0d; /*variable of interrupt type, 0x0d = IRQ 5*/ /* interrupt prototype */ void interrupt new_handler(__CPPARGS); /* interrupt function pointer */ void interrupt (*old_handler)(__CPPARGS); void main() { old_handler = getvect(intnr); /* save the old interrupt */ setvect(intnr,new_handler); /* install interrupt handler */ ... instructions ... /* restore original interrupt routine */ setvect(intnr,old_handler);

} void interrupt new_handler(__CPPARGS) { ... instructions ... outportb(0x20, 0x20); } The operating system interprets the entries of the IDT as values of pointer variables. Therefore, the key word interrupt provides the definition of the handler as a pointer to a procedure. The following tasks must be considered for programming individual interrupt routines (C or C ++): 1. Every interrupt routine to be replaced must be saved before. Thus, a variable of the type pointer to procedure is defined and specified with the key word interrupt. The storage process is executed by the function getvect(# of interrupt). 2. The installation of interrupts is managed by the setvect(# of interrupt, interrupt handler). This causes a replacement of the corresponding IDT entry by the start address (segment and offset) of the replacing handler. 3. The original interrupt routine of the operating system has to be restored before the program terminates. This avoids conflicts of interrupt handlers and provides a stable operation. 4. The interrupt handler must be terminated with a reset of that PIC request line, at which the interrupt request came in. This is implemented by an automatic end of interrupt -command (outportb(0x20, 0x20)). Items 1., 2. and 3. must be done only once immediately at the beginning respectively at the end of the main program. The realization of interrupt handlers in Pascal is similar, but it should be referred to the programming manual for the explicit implementation. 3.3. Sampling strategy Methods, which base on a continuous comparison of the real quantity of a state variable with its reference (e.g quasianalogous digital control), are generally inappropriate for systems described in this paper. Interrupt driven operations, e.g. methods basing on a predictive computation of switching events, are more suitable. For a first test of the proposed computer topology, the asymmetric regular-sampling method with on-line computation of switching events was used. It provides both easy programming and the use of results of former investigations. With asymmetric sampling the pulse period TP is divided into two sampling sections with a duration of TP/2 each. Within one sampling section the integral of the modulated output voltage uout should be equalized to the integral of the reference voltage uref. That means

For that purpose, the continuous course of the reference voltage uref may be replaced by a constant step value u*(k) within each sampling section k representing the average value in this period. This leads to a linear relation between the switching instant tS and the step voltage u*(t). The switching instant tS for one phase within a half-period k is

tS

Fig. 5 shows the principle of this method for a single phase. In a 3-phase-system, there are three switching events tSa, tSb, tSc,

Figure 5: Principle of asymmetric regular-sampling for one phase which have to be calculated and queued up in chronologous order within every sampling section. The Programmable Interval Timer (PIT) can only recognize time intervals. Therefore, the chronologous order of the firing times must be converted into a stack of intervals of tS,i (i = 0, 1, 2). Before the last interrupt of a half-period occurs, the first switching instant of the following half-period k+1 must be known, because that instant defines the next PIT interval. Due to this demand, the complete succeeding half-period must be computed. This results in a distribution of computation published in [11]. Within a succeeding half-period k+1, the periods between two switching instants are computed by

tS, k

1, i
1, i

tS, k

1, i 1, i

Tp 2

tS, k, 2 i
0;
1, i 1

tS, k

tS, k

tS, k

uref (t) dt

tk tk

tk

tk

uout (t) dt 

T u (k) , k  0 (1) 2

whereas tS,k,2 is the last switching instant of the current halfperiod. The corresponding state modifications of the switching events

TP

u (k) , UD

k  0

(2)

k  0 (3)

i
1, 2; k  0 (4)

are determined simultaneously. A timer termination causes an interrupt, which manages the output of the new inverter state and the loading of the next time interval. The interrupt handles only those routines, which are needed for the pulse forming itself. All other calculations are performed by the main program outside the interrupt-routine.

4. Results
4.1. System specification The system consists of a Pentium 166 MHz processor mounted on a ASUS P/I-P55TP4N motherboard equipped with 512 kB cache RAM and a memory of 32 MB RAM. Of course, less memory is considerable for mere inverter operation, but much memory is useful for simulations. Apart regular plug-in cards such as graphic adapter - a commercial multi-I/O-card (CIODAS 1600, ComputerBoards Inc.) and an additional timer-card (CIO-DIO 24/CTR3, ComputerBoards Inc.), which is clocked with 10 MHz, are inserted. The 3-phase voltage source inverter works at 500V dc voltage and is rated for 70A ac output. It is constructed using commercial half bridge IGBT modules (SKM 145 GB 123 D), which are driven by commercial drivers (SKHI 22). 4.2. PWM operation The limiting criteria of the system with respect to the pulse frequency are the amount of on-line computation inside and outside the interrupt routine as well as the time delay and the time-to-action of the interrupt. Since microprocessor systems have to save their environment in case of interrupts, a short delay time tdel occurs between the timer termination and the switching gate impulse. Generally, this is not a serious problem, because it leads to a general time shifting of

the amount of tdel related to the absolute time of the timer oscillator. It can be assumed, that the time shifting is nearly constant. Therefore, it may be compensated by correcting the timer values. But this is not necessary. Depending on the sampling settings, the timer may be loaded with very small values representing short times tref computed with equations (4) and (5). That means, that the times tref may become shorter than the time-to-action interval tact, which is needed by the processor to handle the complete interrupt. This causes an error interval terr (fig. 6 a)-c)) for the firing signal. Thus, the firing signal cant be put out in the right time. Fig. 7 shows the maximum errors of the used system. This picture was

Figure 7: Switching with maximum error-time terr taken for an output voltage of 0 V. The sampling implies, that all three phases switch simultaneously. But the software is programmed to perform only one switching during one interrupt routine. Consequently, the system works out the three switchings as fast as possible. The curve at the top shows the interrupt signal of the timer. It is set to 1" at the termination of the timer and is reset to 0" by the interrupt-routine described above. The interrupt handling needs additional time after this reset. The three curves uGa, uGb, uGc represent the voltage at the gates of the IGBTs. It can be seen, that the error-time may get up to 17s.

Figure 6: Principle of interrupt processing regarding time-toaction demonstrated at logical firing signals a) t ref = t S > t min b) t ref = t S = t min c) t ref < t S = t min

Special routines are programmed for these cases. Then, two or even more switchings are merged into one interrupt-routine and very short time intervals are performed by dummy routines of known duration. The firing signals at the IGBT gates of the complete three phase voltage system are shown in fig. 8. for one period of the output voltage. The output frequency is 50 Hz with a pulse frequency of

processorsperformance. It is obvious, that there are enough resources left to implement the machine control for pulse frequencies in a range of about 5kHz. In the case of mere inverter control, an operation with pulse frequencies up to 10 kHz should be possible. But that means on the other hand, that inverter control operation can be realized even with less powerful processors, such as a 486 is. 486-systems could be a cheap solution for teaching efforts in the field of electric drives. For the exact limits of microprocessor systems, precise measurements of the processor load have to be done. In order to improve the range of pulse frequencies, other sampling methods could be used as well as special routines within the sampling method. Besides, higher pulse frequencies may be achieved using advanced interrupt programming. [1] [2] [3] [4] [5] [6] Intel Corporation, 82C54 CHMOS programmable interval timer , data sheet; September 1993 H.-P. Messmer, PC-Hardwarebuch, New York; AddisonWesley, 3rd edition 1995, pp. 649 H.-P. Messmer, PC-Hardwarebuch, New York; AddisonWesley, 3rd edition 1995, pp. 625 R. Jigour, Using the 8259A programmable interupt controller, application note; Intel Corporation, 1979 H.-P. Messmer, PC-Hardwarebuch, New York; AddisonWessley, 3rd edition 1995, pp. 625 Intel Corporation, 82C55A CHMOS progammable peripheral interface, data sheet; September 1987 Philips Semiconductor, Selction Guide for the 80C51 Microcontroller Family; Philips Electronics North America Corporation, 1995 Texas Instruments, TMS320C2xx Fixed-point Digital Signal Processors, product bulettin; 1996 S. Fedtke, 80286/80386/i486 effizient programmiert: ATBetriebssysteme, Braunschweig; Vieweg-Verlag, 1991, pp.471/472 Intel Corporation, Pentium Processor Family Developers Manual, Mt. Prosect (IL); Intel Corporation, 1996, ch.1415 M.E. Fraser, C.D. Manning, A proposed predictive average current controller for four-wire boost rectifiers, presented at the IEE Conference on Power electronics and variable speed drives, September 23-25, 1996, p. 147

Figure 8: Gate voltages uGa(t), u Gb(t), u Gc(t) of a 3-phase inverter [7] with pulse control at 50 Hz fundamental frequency 5 kHz. In the area of minimum or maximum output voltage, the gate signals get the whole amplitude, but the used digital oscilloscope does only incorrectly reproduce the real curves. [8] [9]

5. Conclusion
Fig. 9 shows the expenditure of time of interrupt processing during three sampling sections. It can be easily seen, that the interrupt keeps only a small amount (about 20%) of the

[10]

[11]

Figure 9: Distribution of interrupts in an interval of 500 s