Lecture 9

Integer Binary Arithmetic

4.1

Signing The Result of Unsigned Multiplication and Division

The algorithms well see ahead compute the unsigned product or quotient of two operands. To do signed multiplication and division, we can record the signs of the operands, do the unsigned operation and then correct the sign of the result. SA=Sign(A)
operand 1

SB=Sign(B)
operand 2

SC=Sign(C)
result

+ (0) + (0) - (1) - (1)

+ (0) - (1) + (0) - (1)

+ (0) - (1) - (1) + (0)

XOR SA,SB 0 1 1 0

4.2

Multiplication: In general, if the multiplicand has n bits and the multiplier has m bits, the product will have (n+m) bits. Note whats going on: we go through each bit in the multiplier and performing a sequence of left-shifts and additions. This is an indication that to implement multiplication in hardware, one needs a shift-register and an adder. What about the signs of the operands and the sign of the result?

4.3

Start

Multiplier0 = 1

1. Test Multiplier0

Multiplier0 = 0

An Algorithm for Multiplication

Both operands are 32-bits long. What is the size of the product?

1a. Add multiplicand to product and place the result in Product register

2. Shift the Multiplicand register left 1 bit

3. Shift the Multiplier register right 1 bit

How many registers are needed to implement this in hardware? In general, how many repetitions are needed by this algorithm?
4.4

32nd repetition?

No: < 32 repetitions

Yes: 32 repetitions Done

A Simpler (?) Flowchart for the Basic Multiplication Algorithm

start 1 C=C+A A<<1 B>>1 reps? yes done no testB0 0

4.5

Start

Multiplier0 = 1

1. Test Multiplier0

Multiplier0 = 0

Another Algorithm for Multiplication

1a. Add multiplicand to the left half of the product and place the result in the left half of the Product register

2. Shift the Product register right 1 bit

3. Shift the Multiplier register right 1 bit

32nd repetition?

No: < 32 repetitions

Yes: 32 repetitions Done

4.6

The Multiplication Hardware for the Second Multiplication Algorithm

Multiplicand 32 bits

32-bit ALU

Multiplier Shift right 32 bits

Product 64 bits

Shift right Write

Control test

4.7

Operations on 2s Complement
Division: Trivial when multiplier is a power of 2 (use a shift-register to do right shifts). Otherwise, we have to define an algorithm, but first, lets think a bit. Quotient: How many times does the divisor fit into the dividend? Remainder: After a multiple of the divisor has been subtracted from the dividend, whats left?
4.8

Start

Division:
1001 1000 1001010 -1000 1010 -1000 10

1. Subtract the Divisor register from the Remainder register and place the result in the Remainder register

> Remainder 0

Test Remainder

Remainder < 0

2a. Shift the Quotient register to the left, setting the new rightmost bit to 1

2b. Restore the original value by adding the Divisor register to the Remainder register and place the sum in the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0

We do subtractions and shifts

3. Shift the Divisor register right 1 bit

Divisor: 2n bits Dividend: 2n bits Quotient: n bits Remainder: 2n bits

33rd repetition?

No: < 33 repetitions

Yes: 33 repetitions

4.9
Done

A Simpler (?) Flowchart for the Basic Division Algorithm

1001 1000 1001010 -1000 1010 -1000 10
2n bits D = divisor 0000 R = 0000 dividend Q = 0000 n bits

start R=R-D yes

R2 n 1 = 0

no R=R+D Q<<1(0)

Q<<1(1) (0)D>>1 n+1 reps? yes done no

4.10

10

Iteration
Initialize R=R-D

Step

Quotient
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 0001 0011 0011

Divisor
0010 0000 0010 0000 0010 0000 0001 0000 0001 0000 0001 0000 0000 1000 0000 1000 0000 1000 0000 0100 0000 0100 0000 0100 0000 0010 0000 0010 0000 0010 0000 0001

Remainder
0000 0111 1110 0111 0000 0111 0000 0111 1111 0111 0000 0111 0000 0111 1111 1111 0000 0111 0000 0111 0000 0011 0000 0011 0000 0011 0000 0001 0000 0001 0000 0001
4.11

R0=1: +D,Q<<1,Q0=0 D>>1 R=R-D R0=1: +D,Q<<1,Q0=0 D>>1 R=R-D R0=1: +D,Q<<1,Q0=0 D>>1 R=R-D R0=0: Q<<1,Q0=1 D>>1 R=R-D R0=0: Q<<1,Q0=1 D>>1

7 2
n=4

11

The Division Hardware

Divisor Shift right 64 bits

64-bit ALU

Quotient Shift left 32 bits

Remainder 64 bits

Write

Control test

4.12

12

Signing The Remainder

Dividend = Quotient Divisor + Remainder

7 = (3 2) + (1) 2

7 = (4 2) + ( +1) 2

Sign(Remainder) = Sign( Dividend )

Sign( Dividend ) = Sign( Divisor )

To avoid such confusion, we postulate:

Sign( Dividend ) Sign( Divisor ) Sign(Remainder ) = Sign( Dividend ) Quotient = Quotient 4.13

Sign(Remainder ) = Sign( Dividend ) Quotient = Quotient

13

Interlude
Question: Given a positive n-bit number A, how can one compute the twos complement representation of (-A) with the hardware that you know? subtraction 0 -A A

4.14

14

Binvert

Operation CarryIn

0 1 Result

A Few More Details about the ALU

Remember that in 2s complement:

0 1

Less

a.

CarryOut

c = a b = a + b +1

To make c = a + b
Binvert Operation CarryIn a 0 1 Result b 0 1 Less 3 Set Overflow detection b. 2

OP=10 CarryIn=0 Binvert=0

Bnegate=0

To make c = a b
OP=10 CarryIn=1 Binvert=1 Bnegate=1
4.15

Overflow

15

Binvert

CarryIn

Operation

a0 b0

CarryIn ALU0 Less CarryOut

Result0

a1 b1 0

CarryIn ALU1 Less CarryOut

Result1

a2 b2 0

CarryIn ALU2 Less CarryOut

Result2

CarryIn a31 b31 0 CarryIn ALU31 Less Result31 Overflow

Set

4.16

16

Bnegate

Operation

a0 b0

CarryIn Result0 ALU0 Less CarryOut

a1 b1 0

CarryIn Result1 ALU1 Less CarryOut

Zero

a2 b2 0

CarryIn Result2 ALU2 Less CarryOut

ALU operation a ALU b Zero Result Overflow

a31 b31 0

CarryIn ALU31 Less

Result31 Set Overflow

CarryOut

4.17

17