ASSIGNMENT NO: 15 PROBLEM STATEMENT: Implement Combinational Circuits(Using VHDL) THEORY: Adder,Mux

VHDL (VHSIC Hardware Description Language) is a description language for electronic digital systems. The development of this language was driven out of the need, to create a standard language for the documentation of the structure and function of integrated circuits (ICs). The development of VHDL was initiated at the begin of the eighties out of the united states Government's VHSIC (Very High Speed Integrated Circuit)-Project of the American defense Ministry (Department of Defense, DoD). In December 1987 it was standardized by the IEEE (Institute of Electrical and Electronic Engineers) as IEEE 1076-1987 Norm. Since IEEE-Standards are continuously being developed new standardization follows every five year. The latest IEEE 1076-1993 standard was completed in 1993. Since begin of the nineties, VHDL gains worldwide an increasing significance in the electronic development. The language serves meanwhile, in the design and verification of complex digital circuits and systems, not only the purpose of documentation, but also increasingly the structuring, specification, modeling, simulation and synthesis in the development of digital hardware. There is nowadays a large number of VHDL Tools which work on various design levels for which VHDL serves as a data exchange format. Hence graphic editors (schematic editors) are being used for the development of wiring diagram that visualize the structural description of a design on the logic level. A VHDL code generator which is integrated in the editor can generate therefrom a VHDL description for the design. Hence a component net list on the circuit level can be generated from the synthesis able VHDL code of this description. VHDL simulators are being used for the verification of separated development steps or the whole design. Those tools allow the detection and removal of design errors in an earlier stage of the development phase. Even under use of VHDL tools a manual adjustment or optimization of the VHDL code must be frequently tackled. In this case detailed knowledge of the VHDL language is absolutely necessary.

CONCLUSION: Adder,MUX using VHDL has been studied.

ASSIGNMENT NO: 16 PROBLEM STATEMENT: Implement Sequential Circuits (Using VHDL) - Asynchronous, Synchronous Counter

THEORY:

VHDL (VHSIC Hardware Description Language) is a description language for electronic digital systems. The development of this language was driven out of the need, to create a standard language for the documentation of the structure and function of integrated circuits (ICs). The development of VHDL was initiated at the begin of the eighties out of the united states Government's VHSIC (Very High Speed Integrated Circuit)-Project of the American defense Ministry (Department of Defense, DoD). In December 1987 it was standardized by the IEEE (Institute of Electrical and Electronic Engineers) as IEEE 1076-1987 Norm. Since IEEE-Standards are continuously being developed new standardization follows every five year. The latest IEEE 1076-1993 standard was completed in 1993. Since begin of the nineties, VHDL gains worldwide an increasing significance in the electronic development. The language serves meanwhile, in the design and verification of complex digital circuits and systems, not only the purpose of documentation, but also increasingly the structuring, specification, modeling, simulation and synthesis in the development of digital hardware. There is nowadays a large number of VHDL Tools which work on various design levels for which VHDL serves as a data exchange format. Hence graphic editors (schematic editors) are being used for the development of wiring diagram that visualize the structural description of a design on the logic level. A VHDL code generator which is integrated in the editor can generate therefrom a VHDL description for the design. Hence a component net list on the circuit level can be generated from the synthesis able VHDL code of this description. VHDL simulators are being used for the verification of separated development steps or the whole design. Those tools allow the detection and removal of design errors in an earlier stage of the development phase. Even under use of VHDL tools a manual adjustment or optimization of the VHDL code must be frequently tackled. In this case detailed knowledge of the VHDL language is absolutely necessary.

CONCLUSION: Asynchronous, Synchronous Counter using VHDL has been studied.

ASSIGNMENT NO: 17 PROBLEM STATEMENT: I Implement Basic gates using VHDL THEORY:

VHDL (VHSIC Hardware Description Language) is a description language for electronic digital systems. The development of this language was driven out of the need, to create a standard language for the documentation of the structure and function of integrated circuits (ICs). The development of VHDL was initiated at the begin of the eighties out of the united states Government's VHSIC (Very High Speed Integrated Circuit)-Project of the American defense Ministry (Department of Defense, DoD). In December 1987 it was standardized by the IEEE (Institute of Electrical and Electronic Engineers) as IEEE 1076-1987 Norm. Since IEEE-Standards are continuously being developed new standardization follows every five year. The latest IEEE 1076-1993 standard was completed in 1993. Since begin of the nineties, VHDL gains worldwide an increasing significance in the electronic development. The language serves meanwhile, in the design and verification of complex digital circuits and systems, not only the purpose of documentation, but also increasingly the structuring, specification, modeling, simulation and synthesis in the development of digital hardware. There is nowadays a large number of VHDL Tools which work on various design levels for which VHDL serves as a data exchange format. Hence graphic editors (schematic editors) are being used for the development of wiring diagram that visualize the structural description of a design on the logic level. A VHDL code generator which is integrated in the editor can generate therefrom a VHDL description for the design. Hence a component net list on the circuit level can be generated from the synthesis able VHDL code of this description. VHDL simulators are being used for the verification of separated development steps or the whole design. Those tools allow the detection and removal of design errors in an earlier stage of the development phase. Even under use of VHDL tools a manual adjustment or optimization of the VHDL code must be frequently tackled. In this case detailed knowledge of the VHDL language is absolutely necessary.

CONCLUSION: Basic gates using VHDL has been studied.

INDEX

SR. NO.

TITLE OF THE EXPERIMENT

01 02 03 04 05 06 07 08 09

10 11 12 13 14 15 16 17 18 19

Code converters, e.g. Excess-3 to BCD and vice versa. Multiplexers: Application like Realization of Boolean expression using Multiplexer Design, Built and test 4-bit BCD adder by using 4-bit binary IC-7483 Parity Generator and Parity Detector Design a ROM using DEMUX IC 74138 and store the data. Design a 3-bit asynchronous counter using MS J-K flip-flop (ic7476). Build and practically test your circuit. Design, build and practically test 2-bit synchronous UP-DOWN counter using J-K flip-flop. Design, build and practically test sequential circuit, which generate the following sequence: 0-1-0-0-1 Design & Implement Sequence Generator for the given sequence by using J-K flip-flops (IC 7476). Avoid the lockout condition & Draw Bush diagrams required to bring the counter from invalid state to Valid state. -1-3-5-7Design and implement mod-10 and mod 100 by using decade counter (7490). Design 4 bit Pseudo random sequence generator using shift register IC 74194. Build and practically test your circuit. Design & Implement 4-Bit Barrel Shifter to perform Shift &Rotation operation to left & right Design, built & test Sequential circuit, which detect the following Sequence For both Mealy & Moore circuit -1-1-0Design an ASM chart and ckt. for the given waveforms Combinational Circuits(Using VHDL) - Adder,Mux Sequential Circuits (Using VHDL) - Asynchronous, Synchronous Counter Basic gates using VHDL Annex. A: Distribution List Annex B: Revision Record