VINAYAKA MISSION UNIVERSITY V.M.K.V ENGINEERING COLLEGE, SALEM 636308.

. DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION VLSI DESIGN (VII-SEMESTER) UNIT - 1

PART A 1. Draw the MOS model of transistor. 2. Draw the NMOS transistor structure. 3. Draw the circuit symbols for PMOS transistor. 4. What is threshold voltage? 5. List out the different of CMOS technology. 6. What is body effect? 7. List out the some Advantage of SOI process. 8. What are the limitation of SOI process? 9. Define saturation region. 10. Draw the CMOS switch. 11. Define Threshold voltage. 12. Define body effect or substrate bias effect. 13. Give the different modes of operation of MOS transistor 14. What are the different regions of operation of a MOS transistor? 15. Give the expressions for drain current for different modes of operation of MOS transistor. 16. Plot the current-voltage characteristics of a NMOS transistor. 17. Define accumulation mode. 18. What are the secondary effects of MOS transistor? 19. What is CMOS latch up? How it can be prevented? 20. What are the different fabrication processes available to CMOS technology? 21. What is based on VLSI design? 22. Mention MOS transistor characteristics. 23. Write the half adder program in verilog module HA (s,c,a,b) 24. What are the common materials used as mask? 25. Given block diagram. Use behavioral model

PART B 1. 2. 3. 4. Explain the NMOS enhancement transistor with neat diagram.(12) Explain n-well CMOS fabrication process with necessary diagram. (12) Explain p-well CMOS fabrication process with diagram. (12) Explain the a) current voltage in linear region (6) b) current voltage in saturation region. (6) 5. Explain the high frequency MOSFET model with neat sketch. (12) 6. With a neat sketch. explain about the nature & behavior of capacitance. (12) 7. With a neat sketch explain about SOI process. (12) 8. i)Explain about the CMOS latch up with up neat diagram.(6) ii)Write a note on spice model. (6) 9. Write in detail about the static behaviour of MOS transistor. (12) 10. Write a detailed note on channel length modulation. (12)

UNIT II PART - A 1. Draw the structure of a CMOS inverter. 2. Write the advantage of CMOS inverter. 3. Write the limitation of CMOS inverter. 4. What do you mean by noise margins of CMOS inverter?. 5. Define static dissipation. 6. What is fan in? 7. What is purpose of design rules?. 8. List some advantage of generalized design rule. 9. Draw the static diagram of CMOS inverter. 10. What is meant by stick diagram ? 11. Draw the circuit of a NMOS inverter. 12. Give the expression for pull-up to pull-down ratio ( ZNU ) for an nMOS Zpd inverter driven by another NMOS inverter. 13. Draw the circuit of a CMOS inverter. 15. What are stick diagrams? 16. What are the different color codes used for single poly silicon NMOS technology? 17. What are design rules? 18. What are Lambda ( ) - based design rules? 19. Define a super buffer. 20. What is the difference between module and instance? 21. Mention the four main CMOS technologies. 22. Define threshold voltage

24.

23.What are the Bi CMOS ? State is the buffer? 25. What is the difference between module and instance?

PART B 1. Explain with neat diagram about structure of CMOS inverter. (12) 2. Write a detailed note on CMOS inverter dc transfer characteristics for various region operations i) (Region A (6) ii) Region B (6) 3. Explain with neat diagram about switching characteristics of CMOS inverter and its estimate (12) 4. Draw & Explain the stick layout using CMOS design. (12) 5. Implement the following function using CMOS logic gate and Explain the circuit i) 2 Input NAND gate (6) ii)2 Input NOR gate (6) 6. Write a detailed CMOS inverter note on dc transfer characteristics for various regions of operations Region E (12) 7. Implement a transmission gate using CMOS device. Explain the circuit. (12) 8. Draw the layout & stick diagrams of CMOS static latches & CMOS dynamic latches and explain it. (12) 9. With a neat sketch explain about lambda based design rule. (12) 10. Write a detailed note on CMOS inverter dc transfer characteristics for various regions of operations (a)Region C (6) (b)Region D (6)

UNIT III PART A 1) Write the static properties of complementary CMOS gates. 2) What is propagation delay of complementary CMOS gates.? 3) Draw the combinational logic circuit. 4) Write the of properties dynamic logic gate. 5) Draw the basic dynamic logic circuit. ______ 6) Implement the following logic function in CMOS h=AB+ CD. 7) Explain about data paths? 8) State that adder? 9) Define Static memory. 10) Define dynamic memory. 11) What are the static properties of complementary CMOS Gates? 12 Draw the equivalent RC model for a two-input NAND gate. 13) What are the major limitations associated with complementary CMOS gate? 14) What is meant by ratio logic? 15) What is true single phase clocked register? 16) Define a tally circuit. 17) Give the NAND-1 1 ' $ 18) Draw the CMOS implementation of 4-to-1 MUX using transmission gates . 19 Draw the CMOS implementation of 8-to-1 MUX using transmission gates 20. Define mobility variation 21. What are the types of gate delays ? 22. What are the types of gate delays ? In real circuits logic gates have delays associated b with them 23. Mention the characteristics of 22V10 24. State the VLSI design flow with neat sketches 25. State channel length modulation

PART B 1) Draw & explain i) Pass-Transistor logic ii) Differential pass transistor logic 2) Write a detailed note i)charge sharing ii)Capacitive coupling iii)clock feed through. 3) Write a detailed note i)Implement the following complex logic function in CMOS G[A,B,C]=A.B+C ii)write the CMOS implementation procedure. . 4) Write a detailed note i)Implement the following logic function in CMOS F=( A+B).C ii)write the CMOS implementation procedure.(6) 5) With the help of neat diagram explain about Array multiplier. 6) With the help of neat diagram explain about Tree multiplier. (6) (6) (6) (2) (4) (6) (6) (6) (12) (12)

7) Describe about complementary static CMOS implementation of full adder with neat sketch. (12) 8) Explain in detail about Positive Edge-Triggered register based on Master Slave Configuration with neat diagram. (12) 9) With the help of neat circuit explain about charge leakage. 10) Discuss in detail about cascading dynamic gates (12) (12)

UNIT -IV PART A 1. What is VHDL ? 2. Write the features of VHDL. 3. What do you mean by Verilog? 4. What is meant by VHDL LIBRARY? 5. What is meant by VHDL PACKAGE? 6. Write the features of sequential statement. 7. What do you mean by concurrent statement? 8. What are three basic forms of wait statement? 9. How selected signal assignment is done using a case statement. 10. Define entity. 11. Give the basic nMOS PLA structure. 12. What do you mean by CMOS PLA.? 13. Define finite state machine. 14. What are the importance of the PLA/FSM in VLSI? 15. Give the structure of a CPLD. 16. Give the CPLD packages available. 17. Give the structure of MAX 7000 CPLD. 18. What is meant by FPGA? 19. Give the general structure of FPGA. 20. What are the different commercial FPGA products? 21. What is meant by CPLD 22.Compare FPGA & CPLD 23. What are the ways applicable to program the PAL (programmable array logic)? 24. What are the two types of stuck at faults in which gate is applicable? 25.Write short notes on body effect.

PART B 1) With the help of block diagram explain the program structure of VHDL. 2) Explain various architectural bodies used inVHDL. 3) Write a short note on function & procedure supported by VHDL. 4) i) Explain Process statement with example ii) Explain Configuration with example (12) (12) (12) (6). (6)

5) i)Write a VHDL source to do for 4bit adder ii) Write the VHDL code for implementing a AND gate 6) i) Explain signal VS Variable with an example. ii) Write the VHDL code for implementing a OR gate 7) i)Explain with example the different forms of wait statement. 8) i) Write a VHDL code that represent D-FLIP FLOP ii)Write a VHDL code that represent D-LATCH 9) i)Write a VHDL code that represent a ALU ii)Write a VHDL code that represent a Multiplier 10) i) Write a VHDL code that represent Register ii)Write a VHDL code that represent Shift Register

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UNIT V PART-A 1.Define PLD 2.What are the four types of devices that are classified as PLDS? 3.What are Interconnection wires? 4.What are CPLD? 5.What are FPGAS? 6.What is meant by Pass Transistor switch? 7.List some objectives of Global Routing. 8.What do you mean by Phantom? 9.What is meant by Sequential Routing? 10.Draw the diagram of pass transistor switches in FPGAS. 11. What are the different commercial FPGA products? 12. What are the different types of modeling VHDL? 13. What are the different types of modeling VHDL? 14. What is variable class ,give example for variable 15. Name two subprograms and give the difference between these two. 16. Name two subprograms and give the difference between these two. 17. write the VHDL coding for a sequential statement (d-flipflop ) 18. What are the different kinds of The test bench 19. What is Moore FSM 20. Write the testbench for and gate 21. Mention the types of ASIC

22.What are the two main types of verilog HDL? 23.List out the classification of operators in verilog HDL. 24. List out the classification of operators in verilog HDL. 25. State that TAP

PART-B 1.Discuss about CPLD structure in detail with the help of a neat diagram. 2.Explain in detail the CPLD packaging and programming. 3.With the help of a neat diagram Explain about i)Parallel Expanders ii)Max 7000 CPLD 4..Discuss in detail about FPGA Packaging &Programming. 5.Explain the structure of FPGA & implementation in FPGAs. 6.With the help of a neat diagram Explain the ASIC design flow. 7.Discuss in detail the i)global routing problem for a cell based ASIC ii)Finding paths in Global routing (6) 8.Explain with a neat diagram about i)global routing using a gate array ii)Gate array inverter form 9.Discuss in detail about Routing Graphs. 10.With the help of a neat diagram explain the Area-routing Algorithm.

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