Colinge Cork

The SOI MOSFET: from Single Gate to Multigate
Jean-Pierre Colinge Silicon Research Group Tyndall National Institute, Cork, Ireland
EUROSOI Tutorial Cork, 23 January 2008
Moores law
10
12
Number of stars in our galaxy
Transistors per chip
DRAM
10
10
64Gb Flash
Microprocessor
10
8
1995
2000
2005
2010
2015
2020
Year
2
EUROSOI 2008 Short Course
January 23, 2008, Cork, Ireland
Electrostatic Integrity (EI)

Voltage-Doping Transformation
SCE 0 .64
H Si H ox
x 2 t ox t dep H j V bi { 0 .64 Si EI V bi 1 2 H ox Lel Lel Lel
DIBL
x 2 t t dep H H j 0 .80 Si 1 2 ox V DS { 0 .80 Si EI V DS Lel Lel Lel H ox H ox
VTH
VTH f SCE DIBL
Bulk
xj tdep
FD SOI
tSi tBOX
DG
tSi
EI
x 2 tox tdep j 1 2 Lel Lel Lel
EI
2 tSi tox tSi Ot BOX 1 L2 L Lel el el
EI
2 1 tSi / 4 tox tSi / 2 1 L2 L L 2 el el el
Electrostatic Integrity in A: bulk, B: fully depleted SOI, and C: double-gate MOSFETs

300
DIBL (mV)
Bulk
100
FDSOI
30
DG
10 10 30 100 300 1000
Gate length (nm)

Typical drain-induced barrier lowering in bulk, fully depleted SOI (FDSOI) and double-gate (DG) MOSFETs calculated by MASTAR
10

40
Gale length (nm)
35
LO HP P
Bulk FDSOI DG
TP LS
25 20 15 10
FDSOI MOSFET limit
2008
2010
2012
2014
MO Bulk S lim FET it
30
2016
2018
2020
Year
Evolution of gate length predicted by the 2005 ITRS for high-performance (HP), low operating power (LOP), and low standby power (LSTP) digital circuits
Electrostatic Integrity: references
1. 2.
3. 4. 5.
6.
7.
T. Skotnicki, G. Merckel, T. Pedron: The voltage-doping transformation: a new approach to the modeling of MOSFET short-channel effects. IEEE Electron Device Letters 9, 109 (1988) T. Skotnicki : Heading for decananometer CMOS - is navigation among icebergs still a viable strategy? Proceedings of the 30th European Solid-State Device Research Conference. Frontier Group, Gif-sur-Yvette, France, 19 (2000) T. Skotnicki: Ultimate scaling of SOI MOSFETs. MIGAS Short Course, Villard de Lans, France (2004) T. Skotnicki, C. Denat, P. Senn, G. Merckel, B. Hennion: A new analog/digital CAD model for subhalfmicron MOSFETs. Technical Digest of the International Electron Devices Meeting (IEDM), 165 (1994) T. Skotnicki, F. Boeuf, R. Cerutti, S. Monfray, C. Fenouillet-Beranger, M. Muller, A. Pouydebasque: New materials and device architectures for the end-of-roadmap CMOS nodes. Materials Science & Engineering B (Solid-State Materials for Advanced Technology) 124-125, 3 (2005) T. Skotnicki, J.A. Hutchby, Tsu-Jae King, H.-S.P. Wong, F. Boeuf: The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance. IEEE Circuits and Devices Magazine 21-1, 16 (2005) T. Skotnicki and F. Boeuf: CMOS Technology Roadmap Approaching Up-hill Specials, Proceedings of the 9th Intl. Symp. On Silicon Materials Science and Technology, ECS Volume 2002-2, 720, 2002
11
Multi-Gate MOSFET Family Tree

SOS MOSFET
Partially Depleted SOI MOSFET
Commercial production
AMD, IBM, Freescale, Sony/Toshiba OKI, EM Microelectronic
Single gate
VCBM, DTMOS, MTCMOS Fully Depleted SOI MOSFET XMOS Double-gate GAA MOSFET DELTA
Commercial production
Double gate Triple gate Triple+ gate

Surround gate
MFXMOS SON MOSFET MIGFET FinFET Quantum-wire MOSFET Trigate MOSFET
3-Gate MOSFET :-Gate MOSFET )-Gate

MBCFET/TSNWFET
CYNTHIA 1982 1984 1986 1988 1990 1992
Surround-gate transistor
Nano-Beam Stacked Channels MOSFET
Year:
1994
1996 1998
2000 2002 2004 2006 2008

Evolution of Transistors
Gate-all-Around Gate-all-Around
3 Gates 2 Gates
Gate Source
1 Gate
Gate Source BOX Drain
Drain
ID
Buried oxide
Polysilicon Gate
Silicon Fin
Gate
Gate
20 nm
Buried Oxide
Gate Source Buried oxide Drain
Back gate (substrate)
Source
Gate
Drain
12
Double-Gate Transistors
IMEC, 1990
SON MOSFET Double-gate GAA MOSFET DELTA
a o ea
MIGFET FinFET
Stac ed C a es OS
1990
1992
1994
1996 1998
Gate
2000 2002 2004 2006

Drain
Source
Hitachi, UC Berkeley, Nippon Steel, NKK, 1998
Hitachi, 1990
Triple-Gate Transistors
Drain
Univ. Louvain, 1995

Quantum-wire MOSFET Trigate MOSFET 3-Gate MOSFET :-Gate MOSFET
Pitch Source W
Intel, 2002
1994
1996 1998
2000 2002 2004 2006
)-gate MOSFET
TSMC, 2002
10
13
Triple+-Gate Transistor: 3 gate
56.5 nm
1.7 nm
0.2 m
11.1 nm 5.7 nm
4.2 nm
50 nm
20 nm
Photo: Courtesy Infineon and Texas Instruments, Inc.

Device Research Conference, 2006
11
Nanowire MOSFET
"High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices", Singh, N.; Agarwal, A.; Bera, L.K.; Liow, T.Y.; Yang, R.; Rustagi, S.C.; Tung, C.H.; Kumar, R.; Lo, G.Q.; Balasubramanian, N.; Kwong, D.-L., IEEE Electron Device Letters, Vol. 27, no. 5, pp. 383- 386, 2006
12
14
Multi-Gate MOSFET Structures

Double gate
Gate
IMEC
GAA, SON
M IG F E T
FinF E T
TI
INTEL
Triple gate
T rigate F E T
3 -gate F E T
: -gate F E T
Surrounding gate
Freescale
U. Singapore
Q uadruple gate FE T
C ylindrical FE T
M ulti-bridg e/stacked na no w ire F E T
LETI
Gate
tsi
13
Multi-Gate MOSFET Structures
Gate
Gate
Hard Mask
Gate
Si BOX
FOX Si
FOX
FOX Si Si
FOX
A: Inverted T channel FET; B: Bulk FinFET; C: Multi-channel Field Effect Transistor

14
15
Electrostatic Control of Channel

x y tsi z Ez Source wsi Ex Ey Ey Ex Ez L
d 2)( x, y , z ) d 2)( x, y , z ) d 2)( x, y , z ) dx 2 dy 2 dz 2
Drain
Poisson:
U ( x, y , z ) H si
Or, in other words:
dE x ( x , y , z ) dE y ( x , y , z ) dE z ( x , y , z ) dx dy dz
15
Natural Length, O
x y tsi z Ez Source wsi Ex Ey Ey Ex Ez L Drain
Single gate Double gate Quadruple gate (square channel cross section) Surrounding gate (circular channel cross section)
OR
O1
H si t t H ox si ox
si t t 2Hox si ox
O2
O4 #
H si
4H ox
t si t ox
2 H ox t si
2t 2 2H si t si ln 1 ox t si 16 H ox
The concept of Natural Length is very similar to that of Electrostatic Integrity

16
16
Electrostatic Control of Channel

x y tsi z Ez Source wsi Ex Ey Ey Ex Ez L Drain
Electrosta tic Control v
n H ox
H si
1 t si tox
n = number of gates; tsi is assumed equal to Wsi n = 3 for trigate and n S for 3-gate (!!!)
A decrease of tsi can be substituted for a decrease of tox or an increase of Hox

17
Natural Length: references
1. 2. 3. 4. 5.
K.K. Young: Analysis of conduction in fully depleted SOI MOSFETs. IEEE Transactions on Electron Devices 36-3, 504 (1989) R.H. Yan, A. Ourmazd, and K.F. Lee: Scaling the Si MOSFET: from bulk to SOI to bulk. IEEE Transactions on Electron Devices 39-7, 1704 (1992) C.P. Auth, J.D. Plummer: Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's. IEEE Electron Device Letters 18-2, 74 (1997) Chi-Woo Lee, Se-Re-Na Yun, Chong-Gun Yu, Jong-Tae Park, J.P. Colinge: Device design guidelines for nano-scale MuGFETs. Solid-State Electronics 51-3, 505 (2007) Q. Chen, E.M. Harrell II, J.D. Meindl: A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs. IEEE Transactions on Electron Devices 50-7, 1631 (2003)
18
17
Nanowires Hold Promise for Future CMOS
David Lammers, News Editor -- Semiconductor International, 10/8/2007
Multiple nanowires in multi-gate devices could increase the drive current of future CMOS devices.
A roadmap from Japan's technical community sees silicon nanowires extending the reach of multi-gate devices.
19
Current Drive
Gate Gate Pitch W Wsi
A
L
B
L
A: Single-gate, planar MOSFET layout; B: Multi-fin multigate FET layout
20
18
Current Drive
Gate W si tsi Fin BOX
3 3
Pitch
Fin
Fin
Fin
ID
I Do
A
2 .5
T P topWsi 2 P side t si Ptop P

T rig a te , (1 0 0 ) s id e w a lls T rig a te (1 1 0 ) s id e w a lls
tsi = 5 0 n m
T rig a te , (1 0 0 ) s id e w a lls T rig a te , (1 1 0 ) s id e w a lls F in F E T , (1 0 0 ) s id e w a lls
2 .5
Current ID/IDo
Current ID/IDo
1 .5 1
1 .5 1
F in F E T (1 0 0 ) s id e w a lls F in F E T , (1 1 0 ) s id e w a lls
50 100
0 .5
0 .5
F in F E T , (1 1 0 ) s id e w a lls
0 50 100 150 200 0
tsi = 1 0 0 n m
150 200
P itc h (n m )
P itc h (n m )
Normalized current drive of a 50nm-thick FinFET and triple-gate MOSFET vs. pitch. Wsi=pitch/2; The (100)-interface electron mobility is 300 cm2/Vs and the (110)-interface mobility is 150 cm2/Vs. Left: tsi=50nm; Right: tsi=100nm
21
Volume Inversion
Electron concentration
Hard Mask
W si=5nm t si=15nm t ox =2nm N a =5x10 15 cm -3 V G =V TH
Hard M ask
W si=5nm t si=15nm t ox =2nm N a =5x10 15 cm -3 V G =V TH +0.7V
A
BOX
W si=t si=5nm t ox =2nm N a =5x10 15 cm -3 V G =V TH
B
BOX
W si=t si=5nm t ox =2nm N a =5x10 15 cm -3 V G =V TH +0.7V
C
BOX
W si=t si=5nm t ox =2nm N a =5x10 15 cm -3 V G =V TH
D
BOX
W si=t si=5nm t ox =2nm N a =5x10 15 cm -3 V G =V TH +0.7V
Electron concentration profile in a FinFET (A,B), a trigate FET (C,D) and a gate-allaround device (E,F) at threshold (A,C,E) and above threshold (B,D,F). The vertical scale (electron concentration) is different for each plot.
F
22
19
Volume Inversion
tsi = 5nm 10nm 20nm 15nm
Mobility
20
5 10 Depth in silicon
15
10 20 30 40 50 Silicon film thickness (nm)

Mobility vs. silicon film thickness in a double-gate transistor.
Electron concentration profile in double-gate MOSFETs with different silicon film thickness.
23
Threshold Voltage
0.56
Threshold voltage (V)
0.54 0.52 0.5 0.48 0.46 0.44
) MS 0 tox 1.2 nm
S 2 !2 kT 2 Cox k T ln 2 2 q q ni t si 2 q m * t si
kT 2 Cox k T ln q q 2 ni t si
0 2 4 6 8 10 12 14 16 18 20
Silicon film thickness (nm)

T. Poiroux, M. Vinet, O. Faynot, J. Widiez, J. Lolivier, T. Ernst, B. Previtali, S. Deleonibus: Multiple gate devices: advantages and challenges. Microelectronic Engineering 80, 378 (2005) EUROSOI Tutorial Cork, 23 January 2008
24
20
10
-6
10
-7
W = tsi = 20 nm 10 nm
Drain current (A)
10
-8
10
-9
5 nm 3 nm 2 nm
.. Schrodinger P Poisson P+S
10
-10
10
-11
10
-12
-0.1
0.1
0.2
0.3
0.4
0.5
0.6
Gate voltage (V)

Drain current vs. gate voltage in trigate MOSFETs with different cross sections. Devices are simulated using either Poisson's equation only (P) or a Poisson+Schrdinger solver (P+S). VDS = 50 mV, tox = 2 nm, Na = 5x1017 cm-3.
25
Wsi=tsi=20 nm / )MS=0V / VG= 0.0V / VG2=0V / Na=5x1017 cm-3
tsi Wsi
Electron concentration (Poisson) Electron concentration (Poisson+Schrdinger )
26
21
Wsi=tsi=20 nm / )MS=0V / VG= 1.5V / VG2=0V / Na=5x1017 cm-3
tsi Wsi
Electron concentration (Poisson) Electron concentration (Poisson+Schrdinger )
27
Wsi=tsi= 5 nm / )MS=0V / VG=0.0V / VG2=0V / Na=5x1017 cm-3
tsi
Electron concentration (Poisson)
Wsi
Electron concentration (Poisson+Schrdinger )
28
22
Wsi=tsi= 5 nm / )MS=0V / VG=1.5V / VG2=0V / Na=5x1017 cm-3
tsi
Electron concentration (Poisson)
Wsi
Electron concentration (Poisson+Schrdinger )
29
3D Simulation: Quantum
Section: 5 nm x 5 nm, VG>VTH
30
23
1D/2D Density of States

-0.6 -0.62 -0.64 -0.66 -0.68 -0.7 -0.72 -0.74 -0.76 1D 3D 0 1 2 3 4 5 x 10 6
21
-0.6 -0.62 -0.64 -0.66 -0.68 -0.7 -0.72 -0.74 -0.76
1D 3D 0 0.5 1 1.5 2 2.5 3 3.5 x 10 4

21
Density of sates vs. energy above Eco for a 1D system (A) and a 2D system (B)
31
Quantum effect: Inter-subband scattering

Polysilicon Gate Silicon Fin W
20 nm
At low temperature
4 x 10
-7
tsi
3.5
T=4.4K, VDS =0.2mV T=8K, VDS =0.2mV T=5K, VD S =50mV

(x 0.004)
Current (A)
3 2.5 2 1.5 1 0.5 T=150K, VD S =0.2mV
Buried Oxide
-0.558 -0.5582
Energy above Eco (eV)
-0.5584 -0.5586 -0.5588 -0.559 -0.5592 -0.5594 -0.5596
150 PeV
-0.5598 -0.56 0 1 2 3 4 x 10 5
20
T=28K, VDS =0.2mV 0 0.1 0.2 0.3

Density of states (cm-3 eV-1)
Gate Voltage (V)

32
24
Quantum effect: Inter-subband scattering

At room temperature !
56.5 nm
20
1.7 nm 11.1 nm 5.7 nm
x 10
-8
15
4.2 nm
Drain conductance (S)
VDS=0.1mV VDS=0.2mV VDS=0.4mV VDS=0.5mV VDS=1.0mV VDS=5.0mV
10
-0.75
Energy above ECo (eV)
-0.755
-0.76
1 meV
-0.765
0
5 meV
-0.77
-5
-0.775 0 2 4 6 8 10 x 10
20
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Density of states
(cm-3
eV-1)
Gate voltage (V)

33
CONTENT: The SOI MOSFET: From Single Gate to Multigate Multigate MOSFET Technology BSIM-CMG: A Compact Model for MultiGate Transistors Physics of the Multigate MOS System Mobility in Multigate MOSFETs Radiation Effects in Advanced Single- and Multi-Gate SOI MOSFETs Multi-Gate MOSFET Circuit Design.
34
25

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The SOI MOSFET: from Single Gate to Multigate

EUROSOI Tutorial Cork, 23 January 2008

Number of stars in our galaxy

Transistors per chip

EUROSOI 2008 Short Course

January 23, 2008, Cork, Ireland

Electrostatic Integrity (EI)

x 2 t ox t dep H j V bi { 0 .64 Si EI V bi 1  2 H ox Lel Lel Lel

x 2 t t dep H H j 0 .80 Si 1  2 ox V DS { 0 .80 Si EI V DS Lel Lel Lel H ox H ox

VTH f  SCE  DIBL

x 2 tox tdep j 1  2 Lel Lel Lel

2 tSi tox tSi  Ot BOX 1  L2 L Lel el el

2 1 tSi / 4 tox tSi / 2 1  L2 L L 2 el el el

Electrostatic Integrity in A: bulk, B: fully depleted SOI, and C: double-gate MOSFETs

Electrostatic Integrity (EI)

Gate length (nm)

EUROSOI 2008 Short Course

January 23, 2008, Cork, Ireland

Electrostatic Integrity (EI)

Gale length (nm)

FDSOI MOSFET limit

MO Bulk S lim FET it

Electrostatic Integrity: references

EUROSOI Tutorial Cork, 23 January 2008

EUROSOI 2008 Short Course

January 23, 2008, Cork, Ireland

Multi-Gate MOSFET Family Tree

Partially Depleted SOI MOSFET

Double gate Triple gate Triple+ gate

MFXMOS SON MOSFET MIGFET FinFET Quantum-wire MOSFET Trigate MOSFET

3-Gate MOSFET :-Gate MOSFET )-Gate

CYNTHIA 1982 1984 1986 1988 1990 1992

2000 2002 2004 2006 2008

Gate Source Buried oxide Drain

Back gate (substrate)

EUROSOI 2008 Short Course

January 23, 2008, Cork, Ireland

2000 2002 2004 2006

Hitachi, UC Berkeley, Nippon Steel, NKK, 1998

Univ. Louvain, 1995

2000 2002 2004 2006

EUROSOI Tutorial Cork, 23 January 2008

EUROSOI 2008 Short Course

January 23, 2008, Cork, Ireland

Triple+-Gate Transistor: 3 gate

Photo: Courtesy Infineon and Texas Instruments, Inc.

EUROSOI Tutorial Cork, 23 January 2008

EUROSOI 2008 Short Course

January 23, 2008, Cork, Ireland

Multi-Gate MOSFET Structures

M ulti-bridg e/stacked na no w ire F E T

Multi-Gate MOSFET Structures

A: Inverted T channel FET; B: Bulk FinFET; C: Multi-channel Field Effect Transistor

EUROSOI 2008 Short Course

January 23, 2008, Cork, Ireland

Electrostatic Control of Channel

Or, in other words:

EUROSOI Tutorial Cork, 23 January 2008

The concept of Natural Length is very similar to that of Electrostatic Integrity

EUROSOI 2008 Short Course

January 23, 2008, Cork, Ireland

Electrostatic Control of Channel

Electrosta tic Control v

x 2 t ox t dep H j V bi { 0 .64 Si EI V bi 1 2 H ox Lel Lel Lel

x 2 t t dep H H j 0 .80 Si 1 2 ox V DS { 0 .80 Si EI V DS Lel Lel Lel H ox H ox

VTH f SCE DIBL

x 2 tox tdep j 1 2 Lel Lel Lel

2 tSi tox tSi Ot BOX 1 L2 L Lel el el

2 1 tSi / 4 tox tSi / 2 1 L2 L L 2 el el el

T P topWsi 2 P side t si Ptop P