International Journal of Computational Intelligence and Information Security, September 2011 Vol. 2, No.

Performance Evaluation of a Router for FPGA Based Crossbar NoC (Network-on-Chip) Architecture
Akhilesh Kumar1 Jyoti Athiya2 and Sanjay Kumar3
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Department of E&C Engineering, NIT Jamshedpur, Jharkhand, India headeced@gmail.com 2 Department of E&C Engineering, NIT Jamshedpur, Jharkhand, India jyoti.athiya@gmail.com 3 Department of C&S Engineering, NIT Jamshedpur, Jharkhand, India sanjay.cse@nitjsr.ac.in Abstract

With the development of IC Design technology and increasing number of element of into a single chip, so that increasing processing power requirement more and more small chip are being integrated into one single chip. This new technology is known as System-on-Chip (SoC), in this chip a billion transistors are expected to be integrated in a single chip. Network-On-Chip (NoC) has been as a new paradigm in the next generation communication architecture that can reducing area also reduce the power consumption. In this paper we implemented a 3*3 mesh based Network-On-chip (NoC) architecture which contain crossbar parallel Router. Our technique invokes an existing parallel router to generate mesh based matrix which can support five simultaneous routing requests at the same time. Crossbar router is used XY Routing algorithm. In comparison to an existing approach, our designing result in lower total power consumption and smaller area. We are using Xilinx9.2i tool for synthesis and ModelSim SE 6.3f for simulation. We characterize the 3*3 mesh based NoC crossbar router for area, power and Performance parameter. Keywords: Network-On-Chip (NoC), System-On-Chip (SoC), Crossbar Router, FPGA, Xilinx9.2i, ModelSim SE 6.3f.

1. Introduction
The popularity of the internet has caused the traffic on the internet to grow drastically every year; similarly power and performance is two essential features which are corresponded with each other, produce main concerns in designing and implementation. Now a days Very Large Scale Integration ICs such as System-OnChip (SoC) may contain different components like that embedded processor, memory, digital and analog ICs. Mainly Bus is used for interconnecting the processing element of SoC, but increasing number of element into a single silicon chip, So that the bus creates the bottleneck. To overcome these problem by the Network-On-Chip (NoC) topology. The new Crossbar Router Architecture has been proposed, it is based on 3*3 mesh interconnection and apply routing algorithm. It adopts a store and forward approach for arbitration. In this paper Network-On-Chip (NoC) can be described by its topology and by strategies used for routing, switching, and arbitration and buffering. Switching is the mechanism that gets data from an input channel of a router and places it on an output channel, while arbitration is responsible to arrange the use of channel and buffers for the message. Router is a central component of any NoC, which can support five parallel connections simultaneously. The Router uses Store and Forward flow control and XY deterministic routing. XY routing algorithm based on Finite State Machine (FSM) to optimize size, this perform simple logical OR of the Select/Gnt lines, which reduces the number of slices. Power consumption and reduce area are the main performance parameter. This paper is organized as following section: The proposed Crossbar Router architecture is given in Section 2. In Section 3 we present the implementation of Router. Section 4 show synthesis result of Crossbar NoC Router. Simulation result of NoC Router is present in Section 5. Section 6 concludes the paper. Routing algorithm design as shown in figure.1

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Figure1: Router Architecture

2. Crossbar NoC Architecture

A Router has a set of parts namely Local(L), North(N), East(E), South(S), West(W), to communicate with the local logical element and neighboring router. It receives the incoming packets from input channels and forwards them to the appropriate output channel. Input channel is made by FIFO or FSM controller with XY Routing algorithm. Output channel is made by FIFO or FSM controller with Round Robin Arbiter. FIFO is presents at both channels to store the packets temporarily. Central logic will be used for Routing decision and arbitration decision. In this work, we design a NoC based Crossbar Parallel Router, which reduces the area and also power consumption. For this work we choose one method of buffing called store and forward. The Router switches a set of intercommunication parts. The crosspoint matrix is very important component whose controlled are maintained by the output channel. Inside the router, Gnt/Ack signals used to access the FIFO without any external signals.

3. Implementation of the Router

The proposed router of has three main blocks, namely the Input channel, Crosspoint Matrix and Output Channels.

3.1. Input Channel

There is one input channel at each port, each running its own control logic. Each Input channel has a FIFO and a control logic which has been implemented as a FSM. The input channel accepts request from other neighbouring router. FIFO of depth 16 and data width of 8 bits.

3.2. Crosspoint Matrix

It is set of multiplexer and demultiplexer, which provide interconnection between the 5 input and 5 output channels. Crossbar router made by interconnection of OR and AND gate. Crossbar architecture shown in figure 3.1.

Figure 3.1: Crossbar Router Architecture

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Figure 3.2: Cross point in the Crossbar Router

Figure 3.3: Logical sum of input_fp bits ANDs with cntrl bits

3.3. Output Channel

There is one output channel at each port, which has an 8 bit FIFO of depth 16 and a control logic similarly implemented with FSM which takes the decision of arbitration. The output channel gets requests from the different input channels and grants one using Round Robin Arbiter (RRA) and sets the control bits lines of crosspoint matrix.

3.4. XY Routing
In XY Routing, a packet forward horizontally till the column is reached and is then forward vertically to the destination Router. It is depend on FIFO Full and FIFO empty condition. When FIFO is filling, X-coordinate of destination router (represent by Hx) is compared with the locally stored X-coordinate (represent by X) of the router. After that it decides the horizontal displacement. If Hx>X then the packet forward to the East port and if Hx<X then packet forward to the West port. If Hx=X then we goes to Y-coordinate in which the Hy>Y then packet forward to the North port and if Hy<Y then the packet forward to the South port. When Hy=Y then the packet forward to the local port.

3.5. Round-Robin Arbiter (RRA)

Round Robin Arbiter is implemented as FSM at each output channel. RRA arbitrates decides which input channel access to that of output channel when many channels are requesting the same output. It is used fixed priority scheme, Priority scheme based on clockwise fashion i.e. if the last input port serviced was West, then

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during next services, the priority will be in the order of East, South, North, Local and West. In this scheme there is no waste of clock cycles because grant is issued only if there is a request from corresponding input channel. Since every input channel has its own XY Routing FSM and output channel has its own RRA FSM.

4. Synthesis Result
Synthesis result of NoC based crossbar Router as shown in table 1. This table show the synthesis result of the NoC Router which is written in VHDL hardware language on FPGA (VirtexII-pro). In this table we can see the component which is used in synthesis procedure and also gives the area in the form of number of gates. Pin Diagram or RTL view shown in figure4.1 and 4.2.

Figure 4.1: Pin Diagram of Crossbar Router

Figure 4.2: RTL View of Crossbar Router

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Table 1 - Total statistical information of synthesis on FPGA - Xilinx

Component Number of Slices Number of Slice Flip Flops Number of 4 input LUTs: Number used as logic: Number used as RAMs: Number of IOs: Number of bonded IOBs: IOB Flip Flops: Number of GCLKs:

Area (number of gates) 771 out of 14336 895 out of 28672 899 out of 28672 819 80 101 101 out of 10 1 out of 16 6% 684 14% 5% 3% 3%

5. Simulation Result
We use the ModelSim SE 6.3f for simulation and Xilinx9.2i for synthesis. The test bench is written to test the Crossbar Router architecture which enters data from input channel to routing and saves the output channel. Figures show the simulation result of crossbar router.

Figure 4.1: Simulation Result of XY Router

Figure 4.2: Simulation Result of NoC Router

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Figure 4.3: Simulation Result of Input Channel

Figure 4.4: Simulation Result of Output Channel

Figure 4.5: Simulation Result of NoC Router

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6. Conclusion
We present a Crossbar parallel Router Architecture for implementation Network-On-chip on FPGA. We optimize the area and power consumption. The operating frequency and data arrival time are 172.712MHz or 5.79 ns. The total memory usage in my designing is 210592 Kilobytes. We obtain the area and power values of the design implemented on Xilinx XC2V3000.

References
[1] L. Benini and G. De Micheli. Network on Chip: A New SOC Paradigm. In IEEE Computer, pages 70-78, Jan. 2002. [2] Sankalp Kallakuri, Doboli, Alex; Doboli, Simona, Proceedings of the International conference on VLSI, p.216-265 (2003). [3] Francesco poletti, Davide Bertozzi, Luca Benini, Alessandro Bogliolo, Design automation for embedded systems, 8, p. 189(2003). [4] Nikolay Kavaldjiev and Gerard J.M. Smit. A survey of efficient on-chip communication for SoC. In PROGRESS 2003 Embedded Systems Symposium, October 2003. [5] Nikolay Kavaldjiev and Gerard J.M. Smit. An energy-efficient Network-on-chip for a heterogeneous tiled reconfigurable System-on-chip. In EUROMICRO Symposium on Digital System Design, pages 492-498, September 2004. [6] Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy Tesylar, Daxia GeChristos Kozyrakis and Kunle Olukotun, of the Fifteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, p.18 (2007). Authors

Ms. Jyoti Athiya received B.E. Degree from R.G.P.V. University, Madhya Pradesh, India in 2007 and M.Tech degree from S.G.S.I.T.S., Indore, Madhya Pradesh India in 2010. She is now working as Assistant Professor in Department of Electronics and Communication Engineering at N.I.T. Jamshedpur, Jharkhand, India. Her interested field of research is FPGA based digital circuit design.

Prof. Akhilesh Kumar received B.Tech degree from Bhagalpur university, Bihar, India in 1986 and M.Tech degree from Ranchi, Bihar, India in 1993. He has been working in teaching and research profession since 1989. He is now working as H.O.D. in Department of Electronics and Communication Engineering at N.I.T. Jamshedpur, Jharkhand, India. His interested field of research digital circuit design.

Prof. Sanjay Kumar received B.Tech degree from Mysore university, India in 1993. He has been working in teaching and research profession since march 1996. He is now working as Assistant Professor in Department of Computer Science and Engineering at N.I.T. Jamshedpur, Jharkhand, India. At present he is pursuing his Ph.D in the field of mobile computing.

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