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The TL431, A, B integrated circuits are threeterminal programmable shunt regulator diodes. These monolithic IC voltage references operate as a low temperature coefficient zener which is programmable from Vref to 36 V with two external resistors. These devices exhibit a wide operating current range of 1.0 mA to 100 mA with a typical dynamic impedance of 0.22 W. The characteristics of these references make them excellent replacements for zener diodes in many applications such as digital voltmeters, power supplies, and op amp circuitry. The 2.5 V reference makes it convenient to obtain a stable reference from 5.0 V logic supplies, and since the TL431, A, B operates as a shunt regulator, it can be used as either a positive or negative voltage reference.
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TO92 (TO226) LP SUFFIX CASE 29 Pin 1. Reference 2. Anode 3. Cathode
8 1
Programmable Output Voltage to 36 V Voltage Reference Tolerance: 0.4%, Typ @ 25C (TL431B) Low Dynamic Output Impedance, 0.22 W Typical Sink Current Capability of 1.0 mA to 100 mA Equivalent FullRange Temperature Coefficient of 50 ppm/C Typical Temperature Compensated for Operation over Full Rated Operating Temperature Range Low Output Noise Voltage These are PbFree and HalideFree Devices
8 1
8 1
8 7 6 5
This is an internally modified SOIC8 package. Pins 2, 3, 6 and 7 are electrically common to the die attach flag. This internal lead frame modification increases power dissipation capability when appropriately mounted on a printed circuit board. This modified package conforms to all external dimensions of the standard SOIC8 package.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet.
3.28 k 20 pF 7.2 k
150 4.0 k 10 k
+ 2.5 Vref
MAXIMUM RATINGS (Full operating ambient temperature range applies, unless otherwise noted.)
Rating Cathode to Anode Voltage Cathode Current Range, Continuous Reference Input Current Range, Continuous Operating Junction Temperature Operating Ambient Temperature Range TL431I, TL431AI, TL431BI TL431C, TL431AC, TL431BC NCV431AI, NCV431B, TL431BV Storage Temperature Range Total Power Dissipation @ TA = 25C Derate above 25C Ambient Temperature D, LP Suffix Plastic Package P Suffix Plastic Package DM Suffix Plastic Package Total Power Dissipation @ TC = 25C Derate above 25C Case Temperature D, LP Suffix Plastic Package P Suffix Plastic Package ESD Rating Symbol VKA IK Iref TJ TA Value 37 100 to +150 0.05 to +10 150 40 to +85 0 to +70 40 to +125 65 to +150 C W 0.70 1.10 0.52 PD 1.5 3.0 HBM MM >2000 >200 V W Unit V mA mA C C
Tstg PD
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Symbol VKA IK
Max 36 100
Unit V mA
THERMAL CHARACTERISTICS
Characteristic Thermal Resistance, JunctiontoAmbient Thermal Resistance, JunctiontoCase Symbol RqJA RqJC D, LP Suffix Package 178 83 P Suffix Package 114 41 DM Suffix Package 240 Unit C/W C/W
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DV
mV/V
Iref DIref 1.8 0.8 4.0 6.5 2.5 1.8 0.4 4.0 5.2 1.2
mA
mA
0.5 20 0.22
0.5 20 0.22
mA nA W
= 40C for TL431AIP TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431AIDM, TL431IDM, TL431BIDM; = 0C for TL431ACP, TL431ACLP, TL431CP, TL431CLP, TL431CD, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM, TL431BCDM Thigh = +85C for TL431AIP, TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431IDM, TL431AIDM, TL431BIDM = +70C for TL431ACP, TL431ACLP, TL431CP, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM, TL431BCDM 2. The deviation parameter DVref is defined as the difference between the maximum and minimum values obtained over the full operating ambient temperature range that applies.
Vref max DVref = Vref max -Vref min DTA = T2 - T1
Vref min T1 T2
Ambient Temperature
The average temperature coefficient of the reference input voltage, aVref is defined as:
ppm V + ref _C
X 10 6 +
D T A (V ref @ 25_C)
D V ref x 10 6
aVref can be positive or negative depending on whether Vref Min or Vref Max occurs at the lower ambient temperature. (Refer to Figure 6.) Example : DV V ref + 8.0 mV and slope is positive, aV DV ref + 0.008 x 106 + 45.8 ppm _C 70 (2.495)
KA 3. The dynamic impedance ZKA is defined as: |Z KA| + . When the device is programmed with two external resistors, R1 and R2, D IK
(refer to Figure 2) the total dynamic impedance of the circuit is defined as: |Z KA | [ |Z KA| 1 ) R1 R2
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TL431AI / NCV431AI Characteristic Reference Input Voltage (Figure 1) VKA = Vref, IK = 10 mA TA = 25C TA = Tlow to Thigh Reference Input Voltage Deviation Over Temperature Range (Figure 1, Notes 4, 5) VKA= Vref, IK = 10 mA Ratio of Change in Reference Input Voltage to Change in Cathode to Anode Voltage IK = 10 mA (Figure 2), DVKA = 10 V to Vref DVKA = 36 V to 10 V Reference Input Current (Figure 2) IK = 10 mA, R1 = 10 k, R2 = TA = 25C TA = Tlow to Thigh (Note 4) Reference Input Current Deviation Over Temperature Range (Figure 2, Note 4) IK = 10 mA, R1 = 10 k, R2 = Minimum Cathode Current For Regulation VKA = Vref (Figure 1) OffState Cathode Current (Figure 3) VKA = 36 V, Vref = 0 V Dynamic Impedance (Figure 1, Note 6) VKA = Vref, DIK = 1.0 mA to 100 mA f 1.0 kHz 4. Tlow Symbol Vref Min Typ Max Min
TL431AC Typ
DV
DV ref KA 1.4 1.0 2.7 2.0 1.4 1.0 2.7 2.0 1.4 1.0 2.7 2.0
mV/V
Iref DIref 1.8 0.8 4.0 6.5 2.5 1.8 0.4 4.0 5.2 1.2 1.1 0.8 2.0 4.0 2.5
mA
mA
0.5 20 0.22
0.5 20 0.22
mA nA W
= 40C for TL431AIP TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431BV, TL431AIDM, TL431IDM, TL431BIDM, NCV431AIDMR2, NCV431AIDR2 = 0C for TL431ACP, TL431ACLP, TL431CP, TL431CLP, TL431CD, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM, TL431BCDM Thigh = +85C for TL431AIP, TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431IDM, TL431AIDM, TL431BIDM = +70C for TL431ACP, TL431ACLP, TL431CP, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM, TL431BCDM = +125C TL431BV, NCV431AIDMR2, NCV431AIDR2, NCV431BVDMR2G 5. The deviation parameter DVref is defined as the difference between the maximum and minimum values obtained over the full operating ambient temperature range that applies.
Vref max DVref = Vref max -Vref min DTA = T2 - T1
Vref min T1 T2
Ambient Temperature
The average temperature coefficient of the reference input voltage, aVref is defined as:
ppm V + ref _C
X 10 6 +
D T A (V ref @ 25_C)
D V ref x 10 6
aVref can be positive or negative depending on whether Vref Min or Vref Max occurs at the lower ambient temperature. (Refer to Figure 6.) Example : DV V ref + 8.0 mV and slope is positive, aV DV ref + 0.008 x 106 + 45.8 ppm _C 70 (2.495)
KA 6. The dynamic impedance ZKA is defined as |Z KA| + When the device is programmed with two external resistors, R1 and R2, (refer D IK
to Figure 2) the total dynamic impedance of the circuit is defined as: |Z KA | [ |Z KA| 1 ) R1 R2 7. NCV431AIDMR2, NCV431AIDR2, NCV431BVDMR2G Tlow = 40C, Thigh = +125C. Guaranteed by design. NCV prefix is for automotive and other applications requiring site and change control.
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Vref
R2 Vref
KA
+V
ref
1 ) R1 ) I S R1 ref R2
150 IK , CATHODE CURRENT (mA) IK , CATHODE CURRENT ( A) 100 50 0 -50 -100 -2.0 VKA = Vref TA = 25C Input IK VKA
800 600 Input 400 200 0 VKA = Vref TA = 25C VKA IK IMin
-1.0
1.0
2.0
3.0
-200 -1.0
2.0
3.0
Input Vref
2600
3.0 2.5 2.0 1.5 IK = 10 mA 1.0 0.5 0 -55 -25 0 25 50 75 100 125 Input 10k Iref IK VKA
2400 -55
-25
25
50
75
100
125
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5
-16
Input R1 IK Vref
VKA
Input
VKA
-24
R2
-32
10
20
30
40
-25
25
50
75
100
125
100 |ZKA|, DYNAMIC IMPEDANCE ( ) Output IK + GND |ZKA|, DYNAMIC IMPEDANCE ( ) 1.0 k 50 10 TA = 25C D IK = 1.0 mA to 100 mA
0.320 0.300 0.280 0.260 0.240 0.220 0.200 -55 -25 0 25 50 75 100 125 VKA = Vref D IK = 1.0 mA to 100 mA f 1.0 kHz Output 1.0 k IK 50 + GND
1.0
0.1 1.0 k
10 k
1.0 M
10 M
60 50 40 30 20 10 0 -10 1.0 k 10 k 100 k f, FREQUENCY (MHz) 1.0 M 10 M IK = 10 mA TA = 25C 9.0 mF 15 k 8.25 k GND IK Output NOISE VOLTAGE (nV/ Hz) 230
80
60
40 Input 20
0 10
100
10 k
100 k
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TA = 25C
10 nF
100 nF
150 IK V+ CL V+
150 IK 10 k CL
Figure 17. Test Circuit For Curves B, C, And D of Stability Boundary Conditions
TYPICAL APPLICATIONS
V+ R1
Vout
V+ R1
Vout
V out +
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V out + V out(min)
V+
RCL
Iout
V+
Isink
I V I out + ref R CL
Sink
V + ref R S
RS
V+ R1
Vout
V+ R1
Vout
out(trip)
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Vout Vin R2 R4 Vth = Vref Vin < Vref > Vref Vout V+ 2.0 V
L.E.D. indicator is `on' when V+ is between the upper and lower limits. Lower Limit + Upper Limit + 1 ) R1 V R2 ref 1 ) R3 V R4 ref
38 V 330
5.0 k 1%
50 k 1% 10 kW V
500 k 1%
5.0 M 1%
+ 360 k 1.0 mF
470 mF
1.0 kW V RX
* 0.05 mF Tone 25 k
Volume 47 k
56 k
10 k
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Vin = 10 V to 20 V 1.0 k
150 mH @ 2.0 A TIP115 Vout = 5.0 V Iout = 1.0 A 4.7 k MPSA20 2200 mF 4.7 k 0.1 mF 2.2 k 10 51 k 4.7 k 1N5823 0.01mF 100 k 470 mF +
Test Line Regulation Load Regulation Output Ripple Output Ripple Efficiency
Conditions Vin = 10 V to 20 V, Io = 1.0 A Vin = 15 V, Io = 0 A to 1.0 A Vin = 10 V, Io = 1.0 A Vin = 20 V, Io = 1.0 A Vin = 15 V, Io = 1.0 A
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Z1 +
2p R
Example 1:
The resulting transfer function Bode plot is shown in Figure 32. The asymptotic plot may be expressed as the following equation:
1) Av + 615 1) jf 500 kHz 1) jf 60 kHz
Go = 1.25 (Vcp2) mmhos. Resistor and capacitor typical values are shown on the model. Process tolerances are 20% for resistors, 10% for capacitors, and 40% for transconductances. An examination of the device model reveals the location of circuit poles and zeroes:
P1 + 2p R 1 GM C + 1 + 7.96 kHz 2p * 1.0 M * 20 pF
jf 8.0 kHz
The Bode plot shows a unity gain crossover frequency of approximately 600 kHz. The phase margin, calculated from the equation, would be 55.9 degrees. This model matches the OpenLoop Bode Plot of Figure 12. The total loop would have a unity gain frequency of about 300 kHz with a phase margin of about 44 degrees.
P1
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RL
Vref
1.78 V
RGM 1.0 M
Anode
Note that the transfer function now has an extra pole formed by the load capacitance and load resistance. Note that the crossover frequency in this case is about 250 kHz, having a phase margin of about 46 degrees. Therefore, instability of this circuit is likely.
Example 2. IC = 7.5 mA, RL = 2.2 kW, CL = 0.01 mF. Cathode tied to reference input pin. An examination of the data sheet stability boundary curve (Figure 15) shows that this value of load capacitance and cathode current is on the boundary. Define the transfer gain. The DC gain is:
G+G R GoR + M GM L (2.323)(1.0 M)(1.25 m)(2200) + 6389 + 76 dB
The resulting open loop Bode plot is shown in Figure 33. The asymptotic plot may be expressed as the following equation:
1) Av + 615 1) jf 8.0 kHz jf 500 kHz jf 60 kHz 1) jf 7.2 kHz
With three poles, this system is unstable. The only hope for stabilizing this circuit is to add a zero. However, that can only be done by adding a series resistance to the output capacitance, which will reduce its effectiveness as a noise filter. Therefore, practically, in reference voltage applications, the best solution appears to be to use a smaller value of capacitance in low noise applications or a very large value to provide noise filtering and a dominant pole rolloff of the system.
1)
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SOIC8 (PbFree)
Micro8 (PbFree)
PDIP8 (PbFree)
SOIC8 (PbFree)
Micro8 (PbFree)
PDIP8 (PbFree)
TO92 (PbFree)
TO92 (PbFree)
TO92 (PbFree)
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
SOIC8 D SUFFIX CASE 751 8 431xx ALYW G 1 8 TL431 ALYWx G 1 (Exception for the TL431CD and TL431ID only) 1 Micro8 CASE 846A PDIP8 CASE 626 TO92 (TO226) CASE 29
8 xxx AYWG G
xxxx = See Specific Marking Code A = Assembly Location Y, YY = Year WW, W = Work Week G or G = PbFree Package (Note: Microdot may be in either location)
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12
A R P L
SEATING PLANE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS UNCONTROLLED. 4. LEAD DIMENSION IS UNCONTROLLED IN P AND BEYOND DIMENSION K MINIMUM. INCHES MIN MAX 0.175 0.205 0.170 0.210 0.125 0.165 0.016 0.021 0.045 0.055 0.095 0.105 0.015 0.020 0.500 --0.250 --0.080 0.105 --0.100 0.115 --0.135 --MILLIMETERS MIN MAX 4.45 5.20 4.32 5.33 3.18 4.19 0.407 0.533 1.15 1.39 2.42 2.66 0.39 0.50 12.70 --6.35 --2.04 2.66 --2.54 2.93 --3.43 ---
X X H V
1
D G J C N N SECTION XX
DIM A B C D G H J K L N P R V
P T
SEATING PLANE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS UNCONTROLLED. 4. LEAD DIMENSION IS UNCONTROLLED IN P AND BEYOND DIMENSION K MINIMUM. MILLIMETERS MIN MAX 4.45 5.20 4.32 5.33 3.18 4.19 0.40 0.54 2.40 2.80 0.39 0.50 12.70 --2.04 2.66 1.50 4.00 2.93 --3.43 ---
X X V
1
D J C N SECTION XX
DIM A B C D G J K N P R V
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D D1
E
8 5
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. DIMENSION E IS MEASURED WITH THE LEADS RESTRAINED PARALLEL AT WIDTH E2. 4. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A A1 b C D D1 E E1 E2 E3 e L MIN 0.015 0.014 0.008 0.355 0.005 0.300 0.240 INCHES NOM MAX 0.210 0.018 0.022 0.010 0.014 0.365 0.400 0.310 0.325 0.250 0.280 0.300 BSC 0.430 0.100 BSC 0.115 0.130 0.150 MILLIMETERS MIN NOM MAX 5.33 0.38 0.35 0.46 0.56 0.20 0.25 0.36 9.02 9.27 10.02 0.13 7.62 7.87 8.26 6.10 6.35 7.11 7.62 BSC 10.92 2.54 BSC 2.92 3.30 3.81
E1
1 4
NOTE 5
F TOP VIEW
c E2 END VIEW
NOTE 3
e/2
L A1 e
8X
SEATING PLANE
E3 b 0.010
M
SIDE VIEW
C A
END VIEW
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HE
PIN 1 ID
b 8 PL 0.08 (0.003)
T B
SEATING
DIM A A1 b c D E e L HE
A c L
SOLDERING FOOTPRINT*
8X
1.04 0.041
0.38 0.015
8X
3.20 0.126
4.24 0.167
5.28 0.208
6X
0.65 0.0256
SCALE 8:1
mm inches
*For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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B
1
S
4
0.25 (0.010)
Y G
C Z H D 0.25 (0.010)
M SEATING PLANE
X 45 _
0.10 (0.004)
Z Y
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1
mm inches
*For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Micro8 is a trademark of International Rectifier.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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TL431/D