PRELIMINARY TECHNICAL DATA

ADuC842 MicroConverter , 12- Bit ADCs and DACs with Embedded Hi-Speed 62KB FLASH MCU

Preliminary Technical Data

FEATURES PIN COMPATABLE Upgrade to ADuC812/ADuC832 INCREASED PERFORMANCE Single Cycle 16MIPS 8052 core High Speed 400kSPS 12-Bit ADC INCREASED MEMORY 62Kbytes On-Chip Flash/EE Program Memory 4KBytes On-Chip Flash/EE Data Memory In circuit re-programmable Flash/EE, 100 Yr Retention, 100 Kcycles Endurance 2304 Bytes On-Chip Data RAM SMALLER PACKAGE Available in 8mm x 8mm Chip Scale Package Also available in 52 pin PQFP - pin compatable with ADuC812/ADuC831 ANALOG I/O 8-Channel, 400kSPS High Accuracy, 12-Bit ADC On-Chip, 20 ppm/ o C Voltage Reference DMA Controller, High-Speed ADC-to-RAM capture Two 12-Bit Voltage Output DACs Dual Output PWM-SD DACs On-Chip Temperature Monitor Function 8051 Based Core 8051-Compatible Instruction Set (16.7 MHz Max) High performance Single Cycle Core* 32kHz Ext Crystal,On-Chip Programmable-PLL 12 Interrupt Sources, Two Priority Levels Dual Data Pointers, Extended 11-bit Stack Pointer On-Chip Peripherals Time Interval Counter (TIC) UART, I2C and SPI Serial I/O Watchdog Timer (WDT), Power Supply Monitor (PSM) Power Normal: 6mA @ 5 V (Core CLK = 2.098 MHz) Power-Down: 15A @ 3 V Development Tools Low Cost, comprehensive development system incorporating non-intrusive single pin emulation IDE based, assembly and C source debug APPLICATIONS Optical Networking - Laser Power Control Basestation Systems - Power Amplifier Bias Control Precision Instrumentation, Smart Sensors Transient Capture Systems DAS and Communications Systems
MicroConverter is a registered trademark of Analog Devices, Inc. SPI is a registered trademark of Motorola Inc. * 68% of insturctions completed in one or two clock cycles

ADuC842
FUNCTIONAL
ADuC842
12-B T I D AC
BU F
D AC

BLOCK

DIAGRAM

A D C0 A D C1 . . .
MU X
T/H

4 0 0 K SP S 12 -B IT A D C

12-B T I D AC
16-BIT DAC

BU F

D AC

A D C5 A D C6 A D C7
H AR D W AR E C AL IBR A TIO N

16-BIT DAC

P WM 0

MU X
PW M1

16-BIT PW M
16-BIT PWM

TEM P S EN SO R

16 MIP S 8 0 51 -B AS ED MC U WITH AD D IT IO NA L PE RIP H ER AL S 6 2 K BY TES FL A SH /EE PR O GR AM M EMO RY 4 KB YTES FLA SH /E E DA TA MEM O R Y 2 3 04 BY TE S US ER R AM

3 1 6 B IT TIM ER S 1 R E AL TIM E C L O C K
IN TE R N AL BA N DG AP V R EF
OSC

PO W ER S UP PL Y M O N WA TC H DO G TIME R
U A RT , I2 C AN D SPI S ER IA L I/O

4 P AR A L LE L P O R TS

VR E F

X TAL 1

XT AL 2

GENERAL DESCRIPTION

The ADuC842 is a complete smart transducer front-end, integrating a high-performance self calibrating multichannel ADC, dual DAC and an optimized single cycle 16MHz 8-bit MCU(8051 instruction set compatible) on a single chip. The device operates from a 32 kHz crystal with an on-chip PLL generating a high-frequency clock of 16.77MHz. This clock is, in turn, routed through a programmable clock divider from which the MCU core clock operating frequency is generated. The microcontroller is an optimized 8052 core offering up to 16 MIPS peak performance. 62 Kbytes of nonvolatile Flash/EE program memory are provided on-chip. 4 Kbytes of nonvolatile Flash/EE data memory, 256 bytes RAM and 2 KBytes of extended RAM are also integrated on-chip. The ADuC842 also incorporates additional analog functionality with two 12-bit DACs, power supply monitor, and a bandgap reference. On-chip digital peripherals include two 16-bit DACs, dual output 16-bit PWM, watchdog timer, time interval counter, three timers/counters, and three serial I/O ports (SPI, I2C and UART). On the ADuC812 and ADuC832 the I2C and SPI interfaces shared some of the same pins. For backwards compatability this is also the case for the ADuC842. However, there is also the option to allow I2C operate separately on P3.3 and P3.4 while SPI uses the standard pins. On-chip factory firmware supports in-circuit serial download and debug modes (via UART), as well as single-pin emulation mode via the EA pin. A functional block diagram of the ADuC842 is shown above. The part is specified for 3V and 5V operation with a maximum operating frequency of 16.777MHz.

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2002

PRELIMINARY TECHNICAL DATA

(AV ADuC842SPECIFICATIONS1 to 5.5V. V = 2.5 V Internal Reference, Fcore = 16.777 MHz, All specifications T = T
REF A DD

= DVDD = 2.7V to 3.3V or 4.5V

MIN to TMAX, unless otherwise noted.)

Parameter ADC CHANNEL SPECIFICATIONS DC ACCURACY 2,3 Resolution Integral Nonlinearity Differential Nonlinearity Integral Nonlinearity 9 Differential Nonlinearity 9 Code Distrbution CALIBRATED ENDPOINT ERRORS4,5 Offset Error Offset Error Match Gain Error Gain Error Match DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) 6 Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Channel-to-Channel Crosstalk 7 ANALOG INPUT Input Voltage Ranges Leakage Current Input Capacitance TEMPERATURE SENSOR 8 Voltage Output at 25C Voltage TC Accuracy Accuracy DAC CHANNEL SPECIFICATIONS Internal Buffer Enabled DC ACCURACY 10 Resolution Relative Accuracy Differential Nonlinearity 11 Offset Error Gain Error Gain Error Mismatch

VDD = 5 V

VDD = 3 V

Unit

Test Conditions/Comments

fSAMPLE = 147 kHz, 12 1 0.3 0.9 0.25 1.5 +1.5/-0.9 1 2 1 2 85 12 1 0.3 0.9 0.25 1.5 +1.5/-0.9 1 3 1 3 85 Bits LSB LSB LSB LSB LSB LSB LSB max typ max typ max max typ 2.5V Internal Reference 2.5V Internal Reference 1V External Reference 1V External Reference ADC Input is a DC Voltage

LSB max LSB typ LSB max dB typ fIN = 10 kHz Sine Wave fSAMPLE = 147 kHz

71 85 85 80 0 to VREF 1 32 650 2.0 3 1.5

71 85 85 80 0 to VREF 1 32 650 2.0 3 1.5

dB dB dB dB

typ typ typ typ

Volts A max pF typ mV typ mV/C typ C typ C typ

Internal 2.5V VREF External 2.5V V REF DAC Load to AGND RL = 10k, CL = 100 pF

12 3 -1 50 1 1 0.5 0 to VREF 0 to VDD 0.5 50 15 10

12 3 -1 1/2 50 1 1 0.5 0 to VREF 0 to VDD 0.5 50 15 10

Bits LSB typ LSB max 1/2 mV max % max % typ % typ V typ V typ typ A typ s typ nV sec typ

Guaranteed 12-Bit Monotonic LSB typ V REF Range AV DD Range VREF Range % of Full-Scale on DAC1 DAC VREF = 2.5V DAC VREF = VDD

ANALOG OUTPUTS Voltage Range_0 Voltage Range_1 Output Impedance I SINK DAC AC CHARACTERISTICS Voltage Output Settling Time Digital-to-Analog Glitch Energy

Full-Scale Settling Time to Within 1/2 LSB of Final Value 1 LSB Change at Major Carry

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PRELIMINARY TECHNICAL DATA

ADuC842
Parameter DAC CHANNEL SPECIFICATIONS Internal Buffer Disabled DC ACCURACY 10 Resolution Relative Accuracy Differential Nonlinearity 11 Offset Error Gain Error Gain Error Mismatch ANALOG OUTPUTS Voltage Range_0 REFERENCE INPUT/OUTPUT REFERENCE OUPUT 14 Output Voltage (VREF) Accuracy Power Supply Rejection Reference Temperature Coefficient Internal VREF Power-On Time EXTERNAL REFERNCE INPUT 15 Voltage Range (V REF)9 Input Impedance Input Leakage POWER SUPPLY MONITOR (PSM) DVDD Trip Point Selection Range DVDD Power Supply Trip Point Accuracy WATCH DOG TIMER (WDT) Time-out Period
9

VDD = 5 V
12,13

VDD = 3 V

Unit

Test Conditions/Comments

12 3 -1 1/2 10 1 0.5 0 to VREF

12 3 -1 1/2 10 1 0.5 0 to VREF

Bits LSB typ LSB max LSB typ mV max % typ % typ V typ

Guaranteed 12-Bit Monotonic V REF Range VREF Range % of Full-Scale on DAC1 DAC VREF = 2.5V

2.5 2.5 47 20 80 0.1 V DD 20 10

2.5 2.5 57 20 80 0.1 V DD 20 10

V % max dB typ ppm/C typ ms typ V min V max k typ A max

Of VREF measured at the CREF pin

Internal Band Gap Deselected via ADCCON1.6

2.63 4.37

Vmin Vmax

Four Trip Points Selectable in This Range Programmed via TPD10 in PSMCON

3.5 0 2000 0 2000

% max ms min ms max. Nine Time-out Periods Selectable in This Range

FLASH/EE MEMORY RELIABILITY CHARACTERISTICS 16 Endurance17 100,000 Data Retention18 100 DIGITAL INPUTS Input High Voltage (VINH) 2.4 Input Low Voltage (VINL) 0.8 Input Leakage Current (Port 0,1, EA) 10 1 Logic 1 Input Current (All Digital Inputs) 10 1 Logic 0 Input Current (Port 2, 3) 80 40 Logic 1-0 Transition Current (Port 2, 3) 700 400 CRYSTAL OSCILLATOR Logic Inputs, XTAL1 Only VINL, Input Low Voltage VINH, Input High Voltage REV. PrA

100,000 100

Cycles min Years min V min V max A max A typ A A A A A A max typ max typ max typ

VIN = 0 V or VDD VIN = 0 V or VDD VIN = VDD VIN = VDD VIL = 0 V VIL = 2 V VIL = 2 V

1 40 400

0.8 3.5

0.4 2.5 3

V typ V typ

PRELIMINARY TECHNICAL DATA

ADuC842SPECIFICATIONS1
Parameter XTAL1 Input Capacitance XTAL2 Output Capacitance MCU Clock Rate DIGITAL OUTPUTS Output High Voltage (VOH) V DD =5V 18 18 16.777216 2.4 4.0 Output Low Voltage (VOL) ALE, Ports 0 and 2 Port 3 SCLOCK/SDATA V DD =3V 18 18 16.777216 2.4 2.6 Units pF typ pF typ MHz max V min V typ VDD = 4.5 V ISOURCE = 80 VDD = 2.7 V ISOURCE = 20 ISINK ISINK ISINK ISINK = = = = to 5.5 V A to 3.3 V A Test Conditions

0.4 0.2 0.4 0.4

0.4 0.2 0.4 0.4

V max V typ Vmax Vmax

1.6 mA 1.6 mA 4 mA 8 mA

Floating State Leakage Current Floating State Output Capacitance

10 1 10

10 1 10

A max A typ pF typ Core CLK = 16MHz

START UP TIME At Power-On 500 From Idle Mode 100 From Power-Down Mode Wakeup with INT0 Interrupt 150 150 Wakeup with SPI/I2C Interrupt Wakeup with External RESET 150 After External RESET in Normal Mode 3 After WDT Reset in Normal Mode 3 POWER REQUIREMENTS Power Supply Voltages AVDD / DVDD - AGND
19,20

500 100 400 400 400 3 3

ms typ s typ ms ms ms ms ms typ typ typ typ typ

Controlled via WDCON SFR

2.7 3.3 4.5 5.5

V V V V

min. max. min. max.

AVDD / DVDD = 3V nom. AVDD / DVDD = 5V nom.

Power Supply Currents Normal Mode DVDD Current9 AVDD Current9 DVDD Current AVDD Current Power Supply Currents Idle Mode DVDD Current9 AVDD Current9 DVDD Current9 AVDD Current9

12 1.4 25 21 1.4

6 1.4 n/a n/a n/a

mA mA mA mA mA

typ max max typ max

Fcore = 8 MHz (CD=3) Fcore = 16 MHz (CD=0)

5 0.11 11 10 0.11

2.5 0.11 n/a n/a n/a

mA mA mA mA mA

typ typ max typ typ

Fcore = 8 MHz (CD=3) Fcore =16 MHz (CD=0)

Power Supply Currents Power Down Mode 3 AVDD Current DVDD Current 35 25 120 Typical Additional Power Supply Currents PSM Peripheral ADC DAC

For any Core CLK 2.5 15 12 120 uA uA uA uA typ max typ typ osc off osc on AVDD = DVDD = 5V

50 1.5 150 4

uA typ mA typ uA typ REV. PrA

PRELIMINARY TECHNICAL DATA

ADuC842
NOTES 1 Temperature Range -40C to +85C. 2 ADC Linearity is guaranteed during normal MicroConverter Core operation. 3 ADC LSB Size = Vref / 2^12 i.e for Internal Vref=2.5V, 1LSB = 610uV and for External Vref =1V, 1LSB = 244uV. 4 Offset and Gain Error and Offset and Gain Error Match are measured after factory calibration. 5 Based on external ADC system components the user may need to execute a system calibration to remove additional external channel errors and achieve these specifications. 6 SNR calculation includes distortion and noise components. 7 Channel to Channel Crosstalk is measured on adjacent channels. 8 The Temperature Monitor will give a measure of the die temperature directly, air temperature can be inferred from this result. 9 These numbers are not production tested but are guaranteed by Design and/or Characterization data on production release. 10 DAC linearity is calculated using : reduced code range of 48 to 4095, 0 to Vref range. reduced code range of 48 to 3945, 0 to V DD range. DAC Output Load = 10K Ohms and 100 pF. 11 DAC Differential NonLinearity specified on 0 to Vref and 0 to Vdd ranges 12 DAC specification for output impedance in the unbuffered case depends on DAC code 13 DAC specifications for Isink, voltage output settling time and digital-to-analog glitch engergy depend on external buffer implementation in unbuffered mode. 14 Measured with Vref and Cref pins decoupled with 0.1F capacitors to graound. Power-up time for the Internal Reference will be determined by the value of the decoupling capacitor chosen for both the Vref and Cref pins. 15 When using an External Reference device, the internal bandgap reference input can be bypassed by setting the ADCCON1.6 bit. In this mode the Vref and Cref pins need to be shorted together for correct operation. 16 Flash/EE Memory Reliability Characteristics apply to both the Flash/EE program memory and the Flash/EE data memory. 17 Endurance is qualified to 100 Kcycles as per JEDEC Std. 22 method A117 and measured at -40C, +25C, and +85C, typical endurance at 25C is 700 Kcycles. 18 Retention lifetime equivalent at junction temperature (Tj) = 55C as per JEDEC Std. 22 method A117. Retention lifetime based on an activation energy of 0.6eV will derate with junction temperature as shown in Figure 27 in the Flash/EE Memory description section of this data sheet. 19 Power Supply current consumption is measured in Normal, Idle, and Power-Down Modes under the following conditions: Normal Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, Core Executing internal software loop. Idle Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, PCON.0=1, Core Execution suspended in idle mode. Power-Down Mode: Reset = 0.4 V, All Port 0 pins = 0.4 V, All other digital I/O and Port 1 pins are open circuit, Core Clk changed via CD bits in PLLCON, PCON.0=1, Core Execution suspended inpower-down mode, OSC turned ON or OFF via OSC_PD bit (PLLCON.7) in PLLCON SFR 20 D VDD power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle. Specifications subject to change without notice.

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PRELIMINARY TECHNICAL DATA

ADuC842
ABSOLUTE MAXIMUM RATINGS*
(T A = 25C unless otherwise noted)

AVDD to DV DD . . . . . . . . . . . . . . . . . . 0.3 V to +0.3 V AGND to DGND . . . . . . . . . . . . . . . . . 0.3 V to +0.3 V DVDD to DGND, AVDD to AGND . . . . 0.3 V to +7 V Digital Input Voltage to DGND 0.3 V, DVDD + 0.3 V Digital Output Voltage to DGND 0.3 V, DVDD + 0.3 V VREF to AGND . . . . . . . . . . . . . . . 0.3 V, AVDD + 0.3 V Analog Inputs to AGND . . . . . . . 0.3 V, AVDD + 0.3 V Operating Temperature Range Industrial ADuC842BS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40C to +85C Operating Temperature Range Industrial ADuC842BCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40C to +85C Storage Temperature Range . . . . . . . . 65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150C JA Thermal Impedance (ADuC831BS) . . . . . . . 90C/W JA Thermal Impedance (ADuC831BCP) . . . . . 52C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ORDERING GUIDE

Model ADuC842BS ADuC842BCP

Temperature Range 40C to +85C 40C to +85C

Package Description 52-Lead Plastic Quad Flatpack 56-Lead Chip Scale Package

Package Option S-52 CP-56

CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADuC842 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

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PRELIMINARY TECHNICAL DATA

ADuC842
PIN FUNCTION DESCRIPTIONS

Mnemonic D V DD A V DD C REF V REF

Type Function P P I I/O Digital Positive Supply Voltage, 3 V or 5 V Nominal Analog Positive Supply Voltage, 3 V or 5 V Nominal Decoupling Input for On-Chip Reference. Connect 0.1 F between this pin and AGND. Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the reference source for the analog-to-digital converter. The nominal internal reference voltage is 2.5 V and this appears at the pin. This pin can be overdriven by an external reference. Analog Ground. Ground Reference point for the analog circuitry. Port 1 is an 8-bit Input Port only. Unlike other Ports, Port 1 defaults to Analog Input Mode, to configure any of these Port Pins as a digital input, write a 0 to the port bit. Port 1 pins are multifunction and share the following functionality. Analog Inputs. Eight single-ended analog inputs. Channel selection is via ADCCON2 SFR. Timer 2 Digital Input. Input to Timer/Counter 2. When Enabled, Counter 2 is incremented in response to a 1 to 0 transition of the T2 input. Digital Input. Capture/Reload trigger for Counter 2 and also functions as an Up/Down control input for Counter 2. Slave Select Input for the SPI Interface User Selectable, I2C-Compatible or SPI Data Input/Output Pin Serial Clock Pin for I2C-Compatible or SPI Serial Interface Clock SPI Master Output/Slave Input Data I/O Pin for SPI Interface SPI Master Input/Slave Output Data I/O Pin for SPI Serial Interface Voltage Output from DAC0 Voltage Output from DAC1 Digital Input. A high level on this pin for 24 master clock cycles while the oscillator is running resets the device. Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs Port 3 pins being pulled externally low will source current because of the internal pullup resistors. Port 3 pins also contain various secondary functions which are described below. PWM Clock Input PMW0 Voltage Output. PWM outputs can be configured to use ports 2.6 & 2.7 or 3.4 and 3.3 PMW1 Voltage Ouput. See CFG832 Register for further Information. Receiver Data Input (Asynchronous) or Data Input/Output (Synchronous) of Serial (UART) Port Transmitter Data Output (Asynchronous) or Clock Output (Synchronous) of Serial (UART) Port Interrupt 0, programmable edge or level triggered Interrupt input, which can be programmed to one of two priority levels. This pin can also be used as a gate control input to Timer 0. Interrupt 1, programmable edge or level triggered Interrupt input, which can be programmed to one of two priority levels. This pin can also be used as a gate control input to Timer 1. Timer/Counter 0 Input Timer/Counter 1 Input Active low Convert Start Logic input for the ADC block when the external Convert start function is enabled. A low-to-high transition on this input puts the track/hold into its hold mode and starts conversion. Write Control Signal, Logic Output. Latches the data byte from Port 0 into the external data memory. Read Control Signal, Logic Output. Enables the external data memory to Port 0. Output of the Inverting Oscillator Amplifier Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Digital Ground. Ground reference point for the digital circuitry. Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs Port 2 pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the external 24-bit external data memory space. 7

AGND P1.0P1.7

G I

ADC0ADC7 I T2 I T2EX SS SDATA SCLOCK MOSI MISO DAC0 DAC1 RESET P3.0P3.7 I I I/O I/O I/O I/O O O I I/O

PWMC PWM0 PWM1 RxD TxD INT0 INT1 T0 T1 CONVST WR RD XTAL2 XTAL1 DGND P2.0P2.7 (A8A15) (A16A23)

I O O I/O O I I I I I O O O I G I/O

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PRELIMINARY TECHNICAL DATA

ADuC842
PIN FUNCTION DESCRIPTION (continued)

Mnemonic PSEN

Type Function O Program Store Enable, Logic Output. This output is a control signal that enables the external program memory to the bus during external fetch operations. It is active every six oscillator periods except during external data memory accesses. This pin remains high during internal program execution. PSEN can also be used to enable serial download mode when pulled low through a resistor on power-up or RESET. Address Latch Enable, Logic Output. This output is used to latch the low byte (and page byte for 24-bit address space accesses) of the address into external memory during normal operation. External Access Enable, Logic Input. When held high, this input enables the device to fetch code from internal program memory locations 0000H to 1FFFH. When held low this input enables the device to fetch all instructions from external program memory. This pin should not be left float. Port 0 is an 8-Bit Open Drain Bidirectional I/O port. Port 0 pins that have 1s written to them float and in that state can be used as high impedance inputs. Port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory. In this application it uses strong internal pull-ups when emitting 1s.

ALE EA

O I

P0.7P0.0

I/O

TERMINOLOGY
ADC SPECIFICATIONS Integral Nonlinearity

This is the maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 LSB below the first code transition and full scale, a point 1/2 LSB above the last code transition.
Differential Nonlinearity

amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise +distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02N + 1.76) dB Thus for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion

This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.
Offset Error

Total Harmonic Distortion is the ratio of the rms sum of the harmonics to the fundamental.
DAC SPECIFICATIONS Relative Accuracy

This is the deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, i.e., +1/2 LSB.
Gain Error

This is the deviation of the last code transition from the ideal AIN voltage (Full Scale 1.5 LSB) after the offset error has been adjusted out.
Signal to (Noise + Distortion) Ratio

Relative accuracy or endpoint linearity is a the maximum deviation from a straight line through the endpoints of the DAC transfer measured after adjusting for zero error and ror.
Voltage Output Settling Time

measure of passing function. It is full-scale er-

This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms

This is the amount of time it takes for the output to settle to a specified level for a full-scale input change.
Digital-to-Analog Glitch Impulse

This is the amount of charge injected into the analog output when the inputs change state. It is specified as the area of the glitch in nV sec.

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PRELIMINARY TECHNICAL DATA

ADuC842
PIN CONFIGURATION
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ADuC842
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12-BIT VOLTAGE OUTPUT DAC DAC CONTROL 12-BIT VOLTAGE OUTPUT DAC
16-BIT DAC

DAC0

ADC CONTROL AND CALIBRATION

DAC1

 $'& $'&

PWM CONTROL

4% DAC
16-BIT PW M 16-BIT PW M

16-BIT

PWM0 MUX PWM1

TEMP SENSOR BANDGAP REFERENCE

95()

62 KBYTES PROGRAM FLASH/EE INCLUDING USER DOWNLOAD MODE 4 KBYTES DATA FLASH/EE 2 KBytes USER XRAM
%8)

256 Bytes USER RAM

T0 16-BIT COUNTER TIMERS T1 T2 T2EX

16MIPS 8052
MCU CORE

WATCHDOG TIMER POWER SUPPLY MONITOR

2 X DATA POINTERS 11-BIT STACK POINTER DOWNLOADER DEBUGGER

&5()

PROG. CLOCK DIVIDER TIME INTERVAL COUNTER (WAKEUP CCT)

,17 ,17

SINGLE-PIN EMULATOR

PLL SYNCHRONOUS SERIAL INTERFACE (SPI OR I2C )

325

ASYNCHRONOUS SERIAL PORT (UART)

UART TIMER

OSC

SCLOCK

RESET

Figure 1 ADuC842 Block Diagram (Shaded areas are features not present on the ADuC812)

REV. PrA

SDATA/MOSI

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DGND

DGND

DGND

AGND

XTAL1

MISO

RXD

TXD

AVDD

DVDD

DVDD

DVDD

ALE

XTAL2

6 6

PRELIMINARY TECHNICAL DATA

ADuC842
INTRODUCTION

The ADuC842 is a 16MIPs 8052 core upgrade to the ADuC832. It has all the same features as the ADuC832 but the standard 12-cycle 8052 core has been replaced with a 16MIPs single cycle core. Since the ADuC842 and ADuC832 share the same feature set only the differneces bettween the two chips are documented here. For full documentation on the ADuC832 please consult the datasheet available at http://www.analog.com/microconverter 8052 Instruction Set The following pages document the number of clock cycles required for each instruction. Most instructions are executed in one or two clock cycles resulting in a 16MIPs peak peformance when operating at PLLCON = 00H. Timer Operation Timers on a standard 8052 increment by one with each machine cycle. On the ADuC842 one machine cycle is equal to one clock cycle hence the timers will increment at the same rate as the core clock. ALE The output on the ALE pin on the ADuC832 was a clock at 1/6th of the core operating frequency. On the ADuC842 the ALE pin operates as follows. For a single machine cycle instruction: ALE is high for the first half of the machine cycle and low for the second half. The ALE output is at the core operating frequency. For a two or more machine cycle instruction: ALE is high for the first half of the first machine cycle and then low for the rest of the machine cycles. External Memory Access There is no support for external program memory access on the ADuC842. When accessing external RAM the EWAIT register may need to be programmed in order to give extra machine cycles to MOVX commands. This is to account for differing external RAM access speeds. Baud Rate Generation There is an addition divide by two in the fractional divider of the ADuC842 this means that any values calculated for T3CON for the ADuC832 need to be incremented by one in order to give the same baud rate on the ADuC842.

10

Rev.PrA

PRELIMINARY TECHNICAL DATA

ADuC842

INSTRUCTION TABLE
Mnemonic Arithmetic ADD A,Rn ADD A,@Ri ADDC A,Rn ADDC A,@Ri ADD A,dir ADD A,#data SUBB A,Rn SUBB A,@Ri SUBB A,dir SUBB A,#data INC A INC Rn INC @Ri INC dir INC DPTR DEC A DEC Rn DEC @Ri DEC dir MUL AB DIV AB DA A Logic ANL A,Rn ANL A,@Ri ANL A,dir ANL A,#data ANL dir,A ANL dir,#data ORL A,Rn ORL A,@Ri ORL A,dir ORL A,#data ORL dir,A ORL dir,#data XRL A,Rn XRL A,@Ri AND register to A AND indirect memory to A AND direct byte to A AND immediate to A AND A to direct byte AND immediate data to direct byte OR register to A OR indirect memory to A OR direct byte to A OR immediate to A OR A to direct byte OR immediate data to direct byte Exclusive-OR register to A Exclusive-OR indirect memory to A 1 1 2 2 2 3 1 1 2 2 2 3 1 2 1 2 2 2 2 3 1 2 2 2 2 3 1 2 Add register to A Add indirect memory to A Add register to A with carry Add indirect memory to A with carry Add direct byte to A Add direct byte to A with carry Subtract register from A with borrow 1 1 1 1 2 2 1 1 2 1 2 2 2 1 2 2 1 1 1 2 2 3 1 1 2 2 9 9 2 Description Bytes Cycles

Subtract indirect memory from A with borrow 1 Subtract direct from A with borrow Subtract immediate from A with borrow Increment A Increment register Increment indirect memory Increment direct byte Increment data pointer Decrement A Decrement Register Decrement indirect memory Decrement direct byte Multiply A by B Divide A by B Decimal Adjust A 2 1 1 1 1 2 1 1 1 1 2 1 1 1

REV. PrA

11

PRELIMINARY TECHNICAL DATA

ADuC842
XRL A,#data XRL dir,A XRL A,dir XRL dir,#data CLR A CPL A SWAP A RL A RLC A RR A RRC A Data Transfer MOV A,Rn MOV A,@Ri MOV Rn,A MOV @Ri,A MOV A,dir MOV A,#data MOV Rn,#data MOV dir,A MOV @Ri,#data MOV dir,dir MOV dir,#data MOV DPTR,#data MOVC A,@A+DPTR MOVC A,@A+PC MOVX A,@Ri MOVX A,@DPTR MOVX @Ri,A MOVX @DPTR,A PUSH dir POP dir XCH A,Rn XCH A,@Ri XCHD A,@Ri XCH A,dir Boolean CLR C CLR bit SETB C SETB bit Clear carry Clear direct bit Set Carry Set direct bit 1 2 1 2 1 2 1 2 Move register to A Move indirect memory to A Move A to register Move A to indirect memory Move direct byte to A Move immediate to A Move register to immediate Move A to direct byte Move immediate to indirect memory Move direct byte to direct byte Move immediate to direct byte Move immediate to data pointer Move code byte relative DPTR to A Move code byte relative PC to A Move external (A8) data to A Move external (A16) data to A Move A to external data (A8) Move A to external data (A16) Push direct byte onto stack Pop direct byte from stack Exchange A and register Exchange A and indirect memory Exchange A and indirect memory nibble Exchange A and direct byte 1 1 1 1 2 2 2 2 2 3 3 3 1 1 1 1 1 1 2 2 1 1 1 2 1 2 1 2 2 2 2 2 2 3 3 3 4 4 4 4 4 4 2 2 1 2 2 2 Exclusive-OR immediate to A Exclusive-OR A to direct byte Exclusive-OR indirect memory to A Exclusive-OR immediate data to direct Clear A Complement A Swap Nibbles of A Rotate A left Rotate A left through carry Rotate A right Rotate A right through carry 2 2 2 3 1 1 1 1 1 1 1 2 2 2 3 1 1 1 1 1 1 1

12

Rev.PrA

PRELIMINARY TECHNICAL DATA

ADuC842
CPL C CPL bit ANL C,bit ANL C,/bit ORL C,bit ORL C,/bit MOV C,bit MOV bit,C Branching JMP @A+DPTR RET RETI ACALL addr11 AJMP addr11 SJMP rel JC rel JNC rel JZ rel JNZ rel DJNZ Rn,rel LJMP LCALL addr16 JB bit,rel JNB bit,rel JBC bit,rel CJNE A,dir,rel CJNE A,#data,rel CJNE Rn,#data,rel CJNE @Ri,#data,rel DJNZ dir,rel Miscellaneous NOP Notes: 1. One cycle is one clock. 2. Cycles of MOVX instructions are 4 cycles when they have 0 wait state. Cycles of MOVX instructions are 4+n cycles when they have n wait states. 3. Cycles of LCALL instruction are 3 cycles when the LCALL instruction comes from interrupt. No operation 1 1 Jump indirect relative to DPTR Return from subroutine Return from interrupt Absolute jump to subroutine Absolute jump unconditional Short jump (relative address) Jump on carry = 1 Jump on carry = 0 Jump on accumulator = 0 Jump on accumulator != 0 Decrement register, jnz relative Long jump unconditional Long jump to subroutine Jump on direct bit = 1 Jump on direct bit = 0 Jump on direct bit = 1 and clear Compare A, direct JNE relative Compare A, immediate JNE relative Compare register, immediate JNE relative Compare indirect, immediate JNE relative Decrement direct byte, JNZ relative 1 1 1 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 4 4 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 Complement carry Complement direct bit AND direct bit and carry AND direct bit inverse to carry OR direct bit and carry OR direct bit inverse to carry Move direct bit to carry Move carry to direct bit 1 2 2 2 2 2 2 2 1 2 2 2 2 2 2 2

REV. PrA

13

PRELIMINARY TECHNICAL DATA

ADuC842
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

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