lesson9-RF Oscillators

9 - RF Oscillator
The information in this work has been obtained from sources believed to be reliable. The author does not guarantee the accuracy or completeness of any information presented herein, and shall not be responsible for any errors, omissions or damages as a result of the use of this information.
April 08
2006 by Fabian Kung Wai Lee
References
[1]* D.M. Pozar, Microwave engineering, 2nd Edition, 1998 John-Wiley & Sons. [2] R. Ludwig, P. Bretchko, RF circuit design - theory and applications, 2000 Prentice-Hall. [3] B. Razavi, RF microelectronics, 1998 Prentice-Hall, TK6560. [4] J. R. Smith,Modern communication circuits,1998 McGraw-Hill. [5] P. H. Young, Electronics communication techniques, 5th edition, 2004 Prentice-Hall. [6] Gilmore R., Besser L.,Practical RF circuit design for modern wireless systems, Vol. 1 & 2, 2003, Artech House
April 08
Agenda
Positive feedback oscillator concepts. Negative resistance oscillator concepts (typically employed for RF oscillator). Equivalence between positive feedback and negative resistance oscillator theory. Oscillator start-up requirement and transient. Making an amplifier circuit unstable. Constant |1| circle. Fixed frequency oscillator design. Voltage-controlled oscillator design.
April 08
1.0 Oscillation Concepts
April 08
Classical Positive Feedback Perspective on Oscillator (1)

Consider the classical feedback system with non-inverting amplifier:
Non-inverting amplifier + +
Si(s)
E(s) A(s)
So(s)
So ) (s ) = 1 AAs(sF (s ) (1.1a) () Si
Positive Feedback
T (s ) = A(s )F (s ) (1.1b)
F(s) Loop gain
The system becomes unstable and oscillates when the following condition occurs:
For sustained oscillation For oscillation to startup
April 08
1 A(s )F (s ) = 0
Barkhausen Criterion
(1.2)
A(s )F (s ) > 1
arg( A(s )F (s )) = 0
5
Classical Positive Feedback Perspective on Oscillator (2)

Possible feedback system can also be achieved with inverting amplifier: Inverting amplifier Si(s) E(s) So So(s) ) + (s ) = 1 AAs(sF (s ) -A(s) () Si
-
Inversion F(s)
April 08
Example of Tuned Feedback Oscillator (1)

A 48 MHz Transistor Common -Emitter Colpitt Oscillator
R RC R=330 Ohm
2.0 1.5 1.0
VB, V VL, V
VL R RL R=220 Ohm
V_DC SRC1 Vdc=3.3 V R RB1 R=10 kOhm
C CD1 C=0.1 uF
0.5 0.0 -0.5
VC C Cc2 C=0.01 uF pb_mot_2N3904_19921211 Q1 R RB2 R=10 kOhm R RE R=220 Ohm C CE C=0.01 uF
-1.0 -1.5 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VB C Cc1 C=0.01 uF
time, usec
Si(s)
L C L1 C1 L=2.2 uH C=22.0 pF R=
+ -
E(s) -A(s)
So(s)
C C2 C=22.0 pF
F(s)
April 08

A 27 MHz Transistor Common-Base Colpitt Oscilator
600 400 200
V_DC SRC1 Vdc=3.3 V R RB1 R=10 kOhm C CD1 C=0.1 uF
VE, mV VL, mV
L L1 L=1.0 uH R= C C3 C=4.7 pF R R1 R=1000 Ohm
R RC R=470 Ohm
0 -200 -400 -600 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VC C Cc2 C=0.1 uF pb_m ot_2N3904_19921211 Q1 VE R RE R=100 Ohm
VL C C1 C=100.0 pF
VB C Cc1 C=0.1 uF
R RB2 R=4.7 kOhm
C C2 C=100.0 pF
time, usec
Si(s)
+ +
E(s) A(s)
So(s)
April 08
F(s)

V_DC SRC1 Vdc=3.3 V R RB1 R=10 kOhm C CD1 C=0.1 uF
A 16 MHz Transistor Common-Emitter Crystal Oscillator
R RC R=330 Ohm
VC C Cc2 C=0.1 uF pb_mot_2N3904_19921211 Q1 R RB2 R=10 kOhm R RE R=220 Ohm C CE C=0.1 uF
VL R RL R=220 Ohm
VB C Cc1 C=0.1 uF
C C1 C=22.0 pF
sx_stk_CX-1HG-SM_A_19930601 XTL1 Fres=16 MHz
C C2 C=22.0 pF
April 08
Introduction RF Oscillator (1)

In RF oscillator (foscillator > 300 MHz) , feedback method to induce oscillation can also employed. However it is difficult to distinguish between the amplifier and the feedback path, owing to the coupling between components and conductive structures on the printed circuit board (PCB). An alternative perspective is to use the 1-port approach. We can view an oscillator as an amplifier that produces an output when there is no input, Thus it is an unstable amplifier that becomes an oscillator! The concept of stability analysis of small signal amplifier using stability circles can be applied to RF oscillator design. Here instead of choosing load or source impedance in the stable region of the Smith Chart, we purposely choose load or source impedance in the unstable region. This will result in either |1 | > 1 or |2 | > 1 .
April 08 2006 by Fabian Kung Wai Lee 10

For instance by choosing the load impedance L at the unstable region, we could ensure that |1 | > 1. We then choose the source impedance properly so that |1 s | > 1 and oscillation will start up (refer back to Chapter 7 on stability theory). Once oscillation starts, an oscillating voltage will appear at both the input and output ports of a 2-port network. So it does not matter whether we enforce |1 s | > 1 or |2 L | > 1, enforcing either one will cause oscillation to occur (It will be shown later that when |1 s | > 1 at the input port, |2 L | > 1 at the output port and vice versa). The key to fixed frequency oscillator design is ensuring that the criteria |1 s | > 1 only happens at one frequency, so that no simultaneous oscillations occur at other frequencies.
April 08
11

A typical RF oscillator block diagram with the one-port criteria for oscillation. One-port means we induce oscillation by either concentrating on Port 1 or Port 2 of the oscillator system. This one-port criteria is also referred to as the negative-resistance criteria. Power Supply
This is usually called the Resonator Zs Port 1 Destabilized Amplifier Port 2
ZL
|1 s | > 1 @ foscillator
April 08
Or
|2 L | > 1 @ foscillator
12
Wave Propagation Stability Perspective (1)

From our discussion of stability from wave propagation in Chapter 7
Zs or s Source b1
Port 1 Port 2
2-port Network
a1 = bs + bs 1s + bs 12s 2 + ... bs a1 = 1 1s
b1 = bs 1 + bs 12s + bs 13s 2 + ... b1 = bs 1 1 1s 1 1 1s
Z1 or 1
bs
a1
bs1
bss 1
bss 12
b 1= bs
bss 212
bss 213
Compare with equation (1.1a)
bss 313
bss 314
April 08
So ) (s ) = 1 AAs(sF (s ) () Si
Feedback is provided by the reflection due to 13 source mismatch
Wave Propagation Stability Perspective (2)

Thus oscillation will occur when | s1 | > 1. Similar argument can be applied to port 2, and we see that the condition for oscillation is |L2 | > 1. It is easier to work with impedance (admittance) in circuit design, since this can be related to lumped passive components. The following slides, with are adapted from Chapter 7, shows how the above requirements can be cast into impedance form.
April 08
14
Oscillation Start-Up Requirements (1)

We will derive the oscillation start-up requirement in terms of impedance for Port. Assume Port 2 of the unstable amplifier is terminated with a suitable load impedance.
s =
(Rs Z o ) + jX s (Rs + Z o ) + jX s
Rs jXs
1 =
Zs
Z1
(R1 Z o ) + jX1 (R1 + Z o ) + jX1

R1
Z2 Vamp ZL
V jX1
Port 2 Source Network Port 1 R1 + jX 1 Z1 V= Vs = Vs R1 + Rs + j ( X 1 + X s ) Z s + Z1

April 08
(1.3)
15

From:
1s =
(R1 Zo ) + jX1 (Rs Zo ) + jX s o (R1 + Zo ) + jX1 (Rs + Zo ) + jX s 2 R R Z o (R1 + Rs ) + Z o X1 X s + j (R1 X s + Rs X1 Z o ( X1 + X s )) = 1 s 2 R1Rs + Z o (R1 + Rs ) + Z o X1 X s + j (R1 X s + Rs X1 + Z o ( X1 + X s ))
o
(R Z o ) + jX (R + Z o ) + jX
Let o be the desired oscillation frequency
1s =
(R R Z (R + R ) + Z (R R + Z (R + R ) + Z
1 s o 1 s 1 s o 1 s
2 o 2 o
X1 X s X1 X s
) + (R X ) + (R X
2 1 2 1
+ Rs X 1 Z o ( X 1 + X s ))2
(1.4)
2 s + Rs X 1 + Z o ( X 1 + X s ))
April 08
16

From (1.4), it is easily seen that if Rs + R1 |o = 0 (1.5a)
Note: These only represents the necessary conditions for oscillator to startup, not the sufficient condition. Sometimes it may not work. We also need to consider the variation of R1 and X1 as a function of signal amplitude. To simplify the steps, this is ignored. See Chapter 6 of [6].
X s + X 1 | o = 0
Then | s1 | = 1 at o. Moreover if
(1.5b) (1.6a) (1.6b)
Rs + R1 | o < 0
X s + X 1 | o = 0

Then | s1 | > 1 at o. Since Rs is > 0, (1.6a) implies that R1 must be negative. Thus in designing an oscillator, we try to make an amplifier unstable so that R1 or R2 will be negative. Then we try to have the condition R1+Rs|o<0, X1+Xs|o= 0 at port 1 or R2+RL|o<0, X2+XL|o= 0 at port 2.

Equations (1.6a) and (1.6b) are equivalent to requiring the denominator of (1.3) to have a complex conjugate pole pair at the frequency o where oscillation occurs, this means:
Z1 (s ) V (s ) = Vs (s ) Z s (s ) + Z1 (s )
When:
Im Pole pair
Rs + R1 | o < 0
X s + X 1 | o = 0
Re
April 08
18
What Happens During Oscillation Start-Up?

Usually the transient signal or noise signal from the environment will contain a small component at the oscillation frequency. This forms the seed in which the oscillation built up. As the voltage amplitude in the two-port network increases, the assumption of small signal operation become invalid. For instance in BJT, nonlinear effects such as transistor saturation and cut-off will happen, this limits the beta of the transistor and finally limits the amplitude of the oscillating signal. Therefore, the design of oscillator in a nutshell is: Use linear analysis to design an unstable system which would let any small transient signal to built up gradually. As the transient signal increases, let the nonlinearity of the circuit limits the final oscillation amplitude.
April 08
19
2.0 Fixed Frequency Oscillator Design
April 08
20
10
Procedures of Designing Fixed Frequency Oscillator (1)

Step 1 - Design a transistor/FET amplifier circuit. Step 2 - Make the circuit unstable by adding positive feedback at radio frequency, for instance, adding series inductor at the base for commonbase configuration. Step 3 - Determine the frequency of oscillation o and extract Sparameters at that frequency. Step 4 - With the aid of Smith Chart and Load Stability Circle, make R1 < 0 by selecting L in the unstable region. Step 5 - Find Z1 = R1 + jX1.
April 08
21
Procedures of Designing Fixed Frequency Oscillator (2)

Step 6 - Find Rs and Xs so that R1 + Rs<0, X1 + Xs=0 (in order for | 1 s |>1) at o. The rule of thumb is to make Rs=(1/3)|R1| . Step 7 - Design the impedance transformation network for Zs and ZL. Step 8 - Built the circuit or run a computer simulation to verify that the circuit can indeed starts oscillating when power is connected. Note: Alternatively we may begin Step 4 using Source Stability Circle and work on | 2 L |> 1 at o .
April 08
22
11
Making an Amplifier Unstable (1)

An amplifier can be made unstable by providing some kind of feedback. Two favorite transistor amplifier configurations used for oscillator design are the Common-Base configuration with Base feedback and Common-Emitter configuration with Emitter degeneration.
April 08
23

This is a practical model of an inductor Base bypass capacitor
V_DC SRC1 Vdc=4.5 V
At 410MHz
DC
DC DC1
S-PARAMETERS
S_Param SP1 Start=410.0 MHz Stop=410.0 MHz Step=2.0 MHz
SStabCircle
S_StabCircle S_StabCircle1 SSC=s_stab_circle(S,51)
StabFact
Common Base Configuration
R Rb1 R=10 kOhm
L LC L=330.0 nH R=
StabFact StabFact1 K=stab_fact(S)
LStabCircle
L_StabCircle L_StabCircle1 LSC=l_stab_circle(S,51) Vout
C Cc2 C=10.0 nF L LB L=22 nH R= R RLB R=0.77 Ohm C Cb C=10.0 nF
Term Term2 Num=2 Z=50 Ohm
C CLB C=0.17 pF
pb_phl_BFR92A_19921214 Q1 R Rb2 L R=4.7 kOhm LE L=330.0 nH R=
Vin C Cc1 C=10.0 nF
An inductor is added in series with the bypass capacitor on the base terminal of the BJT. This is a form of positive series feedback.
Positive feedback here

April 08
R Re R=100 Ohm
24
12

s22 and s11 have magnitude > 1
S(1,2) 0.162 / 166.9... S(2,1) 2.068 / -12.723 S(2,2) 1.154 / -3.535
freq 410.0MHz freq 410.0MHz
K -0.987 S(1,1) 1.118 / 165.6...
L Plane
Unstable Regions
s Plane
April 08
25

DC
DC DC1
S-PARAMETERS
S_Param SP1 Start=410.0 MHz Stop=410.0 MHz Step=2.0 MHz
SStabCircle
S_StabCircle S_StabCircle1 SSC=s_stab_circle(S,51)
V_DC SRC1 Vdc=4.5 V
StabFact
R Rb1 R=10 kOhm
L LC L=330.0 nH R=
StabFact StabFact1 K=stab_fact(S)
LStabCircle
L_StabCircle L_StabCircle1 LSC=l_stab_circle(S,51) Vout
C Cc1 C=1.0 nF Term Term1 Num=1 Z=50 Ohm
C Cc2 C=1.0 nF pb_phl_BFR92A_19921214 Q1 C Ce1 C=15.0 pF
R Rb2 R=4.7 kOhm
Feedback
R Re R=100 Ohm
C Ce2 C=10.0 pF
Common Emitter Configuration Positive feedback here

26
April 08
13

S22 and S11 have magnitude > 1
freq 410.0MHz freq 410.0MHz K -0.516 S(1,1) 3.067 / -47.641 S(1,2) 0.251 / 62.636 S(2,1) 6.149 / 176.803 S(2,2) 1.157 / -21.427
L Plane
s Plane
Unstable Regions
Precautions
The requirement Rs= (1/3)|R1| is a rule of thumb to provide the excess gain to start up oscillation. Rs that is too large (near |R1| ) runs the risk of oscillator fails to start up due to component characteristic deviation. While Rs that is too small (smaller than (1/3)|R1|) causes too much nonlinearity in the circuit, this will result in large harmonic distortion of the output waveform.
V2
Clipping, a sign of too much nonlinearity t
V2 Rs too small For more discussion about the Rs = (1/3)|R1| rule, and on the sufficient condition for oscillation, see [6], which list further requirement.
April 08 2006 by Fabian Kung Wai Lee
Rs too large
28
14
Aid for Oscillator Design - Constant |1| Circle (1)

In choosing a suitable L to make |L | > 1, we would like to know the range of L that would result in a specific |1 |. It turns out that if we fix |1 |, the range of load reflection coefficient that result in this value falls on a circle in the Smith chart for L . The radius and center of this circle can be derived from:
S D 1 = 11 L 1 S 22L
Assuming = |1 |:
By fixing |1 | and changing L .
Tcenter =
2 S 22* + D*S11 D S 22
2 2 2
(2.1a)
Radius =
S12 S 21 D 2 S 22
2 2
(2.1b)
April 08
29
Aid for Oscillator Design - Constant |1| Circle (2)

The Constant |1 | Circle is extremely useful in helping us to choose a suitable load reflection coefficient. Usually we would choose L that would result in |1 | = 1.5 or larger. Similarly Constant |2 | Circle can also be plotted for the source reflection coefficient. The expressions for center and radius is similar to the case for Constant |1 | Circle except we interchange s11 and s22, L and s . See Ref [1] and [2] for details of derivation.
April 08
30
15
Example 2.1
In this example, the design of a fixed frequency oscillator operating at 410MHz will be demonstrated using BFR92A transistor in SOT23 package. The transistor will be biased in Common-Base configuration. It is assumed that a 50 load will be connected to the output of the oscillator. The schematic of the basic amplifier circuit is as shown in the following slide. The design is performed using Agilents ADS software, but the author would like to stress that virtually any RF CAD package is suitable for this exercise.
April 08
31
Example 2.1 Cont...

Step 1 - DC biasing circuit design and S-parameter extraction.
DC
DC D C1
S-PAR AME T ER S
S t ab F ac t
S_Param SP1 Start=410. 0 MH z Stop=410.0 MHz Step=2. 0 MH z
StabFact StabFact 1 K=st ab_f act (S )
V_DC SR C1 Vdc =4.5 V
R Rb1 R=10 kO hm
L LC L=330.0 nH R=
Port 2 - Output
Term Term 2 Num=2 Z=50 Ohm
LSt abC irc le
L_St abCircle L_St abCircle1 load_s tabcir=l_s tab_c irc le(S, 51)
C Cc2 C =1. 0 nF L LB L=12. 0 nH R= C Cb C =1.0 nF R Rb2 R=4.7 kOhm
S S tabC irc le
pb_phl_BF R 92A_19921214 Q1 L LE L=220.0 nH R=
S_StabCircle S_StabCircle1 source_s tabc ir=s_st ab_c irc le(S ,51)
L3 is chosen carefully so that the unstable regions in both L and s planes are large April enough. 08
C Cc1 C =1. 0 nF
Term Term 1 Num=1 Z=50 O hm
Port 1
Amplifier
Port 2
R Re R =100 Ohm
Port 1 - Input
2006 by Fabian Kung Wai Lee 32
16
Example 2.1 Cont...

freq 410.0MHz freq 410.0MHz K -0.987 S(1,1) 1.118 / 165.6... S(1,2) 0.162 / 166.9... S(2,1) 2.068 / -12.723 S(2,2) 1.154 / -3.535
Unstable Regions
Load impedance here will result in |1| > 1

April 08
Source impedance here will result in |2| > 1

33
Example 2.1 Cont...

Step 2 - Choosing suitable L that cause |1 | > 1. We plot a few constant |1 | circles on the L plane to assist us in choosing a suitable load reflection coefficient.
This point is chosen because it is on real line and easily matched.
LSC |1 |=1.5 |1 |=2.0
L = 0.5<0
ZL = 150+j0
L Plane
|1 |=2.5 Note: More difficult to implement load impedance near edges of Smith Chart
34
17
Example 2.1 Cont...

Step 3 - Now we find the input impedance Z1 at 410MHz:
S DL 1 = 11 = 1.422 + j 0.479 1 S 22 L Z1 = Z o
1 + 1 = 10.257 + j 7.851 1 1
R1
X1
Step 4 - Finding the suitable source impedance to fulfill R1 + Rs<0, X1 + Xs=0:
Rs =
1 R1 3.42 3 X s = X1 7.851
April 08
35
Example 2.1 Cont...

The system block diagram:
Port 1 Zs = 3.42-j7.851 Port 2
Common-Base (CB) Amplifier with feedback
ZL = 150
April 08
36
18
Example 2.1 Cont...

Step 5 - Realization of the source and load impedance at 410MHz.
Zs= 3.42-j7.851 49.44pF ZL=150 27.27nH
3.42
CB Amplifier @ 410MHz
3.49pF
50
1 C 1 C= = 49.44 pF 7.851 7.851 =

Example 2.1 Cont... - Verification Thru Simulation
Vpp
BFR92A
Vpp = 0.9V V = 0.45V Power dissipated in the load:
PL = = 0.5
1V 2 RL
0.452 = 2.025mW 50 38
19
Example 2.1 Cont... - Verification Thru Simulation

Performing Fourier Analysis on the steady state wave form:
The waveform is very clean with little harmonic distortion. Although we may have to tune the capacitor Cs to obtain oscillation at 410 MHz.
484 MHz
Example 2.1 Cont... The Prototype

Voltage at the base terminal and 50 Ohms load resistor of the fixed frequency oscillator:
1.4
1.2
1.0
Vbb
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
Vout
0 10 20 30 40 50 60 70 80 90 100 110 120
Output port
-0.6
-0.8
Startup transient ns
20
Example 2.2 - Sample Oscillator Design 2 Using Agilents ADS Software

DC T R ANS IE NT
Tran Tran1 StopTim e=100. 0 nsec MaxTimeS tep=1.2 nsec
P ARAM ET ER SWE EP
ParamSweep Sweep1 SweepVar="R load" SimI nstanceNam e[1] ="Tran1" SimI nstanceNam e[2] = SimI nstanceNam e[3] = SimI nstanceNam e[4] = SimI nstanceNam e[5] = SimI nstanceNam e[6] = St art=100 St op=700 Var VAR Eqn St ep=100 VAR 1 X=1. 0 R load=100
A UHF Voltage Controlled Oscillator:
DC D C1
VtP WL Vtrig V_Tran=pwl(t ime, 0ns, 0V, 1ns,0. 01V, 2ns ,0V) R Rb R=47 kOhm V_DC Vc c Vdc=3.0 V
L Lc L=220.0 nH R=
L L2 L=47. 0 nH R=
R C Rout C c2 C =330. 0 pF R=50 O hm R RL R=Rload
C C b1 C =2. 2 pF
pb_phl_BFR92A_19921214 Q1
C Cb3 C=4. 7 pF C C b2 C =10. 0 pF R V _D C R1 R=4700 Ohm S R C1 V dc=-1.5 V di_sms_bas40_19930908 D1 C C b4 C =4.7 pF
R Re R=220 O hm
April 08
41
Example 2.2 - Oscillator Start-up Waveform and Hardware 2

Voltage across the load resistor RL:
1.0 0.5
Vout
Auxiliary trigger signal
0 10 20 30 40 50 60 70 80 90 10 0
0.0
-0.5
-1.0
-1.5
ns Power splitter
Output port
21
End Notes
To improve the frequency stability of the oscillator, the following steps [5] can be taken. Use components with known temperature coefficients, especially capacitors. Neutralize, or swamp-out with resistors, the effects of active device variations due to temperature, power supply and circuit load changes. Operate the oscillator an low power. Reduce noise, use shielding, AGC and bias-line filtering. Use an oven or temperature compensating circuitry (such as thermistor).
April 08
43
3.0 Voltage Controlled Oscillator
April 08
44
22
About the Voltage Controlled Oscillator (VCO) (1)

A simple VCO using Clapp-Gouriet configuration. The transistor chosen for the job is BFR92A, a wide-band NPN transistor which comes in SOT-23 package. Similar concepts as in the design of fixed frequency oscillator are employed. Where we design the biasing of the transistor and carefully choose a load so that from the input port (Port 1), the oscillator circuit has an impedance:
Z1 ( ) = R1 ( ) + jX 1 ( )
Of which R1 is negative, for a range of frequencies from 1 to 2.
April 08
45
Zs
Clapp-Gouriet Oscillator Circuit with Load
ZL
Z1 = R1 + jX1
April 08
46
23

If we can connect a source impedance Zs to the input port, such that within a range of frequencies from 1 to 2:
Z s ( ) = Rs ( ) + jX s ( ) Rs ( ) < R1 ( ) R1 ( ) < 0
X s ( ) = X 1 ( )
The circuit will oscillate within this range of frequencies. By changing the value of Xs, one can change the oscillation frequency.
The rationale is that only the initial spectral of the noise signal fulfilling Xs = X1 will start the oscillation.
For example, if X1 is +ve, then Xs must be -ve, and it can be generated by a capacitor. By changing the capacitance, one can change the oscillation frequency of the circuit. If X1 is ve, Xs must be +ve. A variable capacitor in series with a suitable inductor will allow us to adjust the value of Xs.

Usually we will design the transistor biasing so that X1 is +ve within the intended range of frequencies. This will be carried out in the example shown here. The design of the transistor biasing is achieved by using computer simulation, where first we design the d.c. biasing, then run small-signal simulation to obtain the S-parameters or Z parameters of the input port. Of course Load Stability Circle is also used to ensure that real part of Z1 is -ve.
April 08
48
24
Schematic of the VCO

Initial noise source to start the oscillation
DC
DC D C1
T R ANS IE NT
Tran Tran1 StopTim e=100. 0 ns ec MaxTimeS tep=1.2 nsec
P ARAM ET ER SWEEP
ParamSweep Sweep1 SweepVar="R load" SimI ns tanc eNam e[1] ="Tran1" SimI ns tanc eNam e[2] = SimI ns tanc eNam e[3] = SimI ns tanc eNam e[4] = SimI ns tanc eNam e[5] = SimI ns tanc eNam e[6] = St art=100 St op=700 V ar VAR E qn St ep=100 VAR 1 X=1. 0 R load=100
VtP WL Vtrig V_Tran=pwl(t ime, 0ns , 0V, 1ns,0. 01V, 2ns ,0V) R Rb R=47 k Ohm V_DC Vcc Vdc =3.0 V
L Lc L=220.0 nH R=
Variable capacitance tuning network
L L2 L=47. 0 nH R=
R C Rout C c2 C =330. 0 pF R=50 O hm R RL R=Rload
C Cb1 C=2. 2 pF
pb_phl_BF R92A_19921214 Q1
C Cb3 C=4. 7 pF C Cb2 C=10. 0 pF
R Re R=220 O hm
R V _D C R1 R=4700 Ohm S RC1 V dc=-1.5 V
di_s ms _bas 40_19930908 D1 C C b4 C =4.7 pF
2-port network
April 08
49
More on the Schematic

L2 together with Cb3, Cb4 and the junction capacitance of D1 can produce a range of reactance value, from -ve to +ve. Together these components form the frequency determining network. Cb4 is optional, it is used to limit the effect of the junction capacitance of D1. R1 is used to isolate the control voltage Vdc from the frequency determining network. It must be a high quality SMD resistor. The effectiveness of isolation can be improved by adding a RF choke in series with R1. Notice that the frequency determining network has no actual resistance to counter the effect of |R1()|. This is provided by the loss resistance of L2 and the junction resistance of D1.
April 08
50
25
Time Domain Result
1.0
0.5
0.0
-0.5
-1.0
-1.5 0 10 20 30 40 50 60 70 80 90 100
Vout when Vdc = -1.5V
April 08
51
Load-Pull Experiment
Peak-to-peak output voltage versus Rload for Vdc = -1.5V.
Vout(pp)
1 100 200 300 400 500 600 700 800
RLoad
April 08
52
26
Controlling Harmonic Distortion (1)

Since the resistance in the frequency determining network is too small, large amount of non-linearity is needed to limit the output voltage waveform, as shown below there is a lot of distortion.
Vout
April 08
53

The distortion generates substantial amount of higher harmonics. This can be reduced by decreasing the positive feedback, by adding a small capacitance across the collector and base of transistor Q1. This is shown in the next slide.
April 08
54
27

The observant person would probably notice that we can also reduce the harmonic distortion by introducing a series resistance in the tuning network. However this is not advisable as the phase noise at the oscillators output will increase ( more about this later).
Capacitor to control positive feedback

DC DC1
DC
TRANSIENT
Tran Tran1 StopTime=280.0 nsec MaxTimeStep=1.2 nsec
VtPWL L Vtrig Lc L=220.0 nH V_Tran=pwl(time, 0ns, 0V, 1ns,0.01V, 2ns,0V) R R= Rb R=47 kOhm I_Probe V_DC I_Probe Iload Vcc IC Vdc=3.0 V C Ccb C=1.0 pF L L2 L=47.0 nH C R= Cb1 pb_phl_BFR92A_19921214 C=6.8 pF Q1 C Cb3 C=4.7 pF C Cb2 C=10.0 pF R Re R=220 Ohm
C Cc2 C=330.0 pF
R Rout R=50 Ohm
R RL R=50 Ohm
R R1 V_DC R=4700 Ohm SRC1 Vdc=0.5 V
di_sms_bas40_19930908 D1 C Cb4 C=0.7 pF
April 08
55

The output waveform Vout after this modification is shown below:
Vout
April 08
56
28

Finally, it should be noted that we should also add a low-pass filter (LPF) at the output of the oscillator to suppress the higher harmonic components. Such LPF is usually called Harmonic Filter. Since the oscillator is operating in nonlinear mode, care must be taken in designing the LPF. A practical design example will illustrate this approach.
April 08
57
The Tuning Range

Actual measurement is carried out, with the frequency measured using a high bandwidth digital storage oscilloscope.
410
D1 is BB149A, a varactor manufactured by Phillips Semiconductor.
405 f
MHz
400
395
0.5
1 Vdc
1.5
2.5
April 08
Volts
58
29
Phase Noise

v(t) t fo Large phase noise v(t) t Small phase noise
April 08
In a practical oscillator, the instantaneous frequency and magnitude of oscillation are not constant. These will fluctuate as a function of time. As a result, the output in the frequency domain is smeared out. This is known as Phase Noise.
Phase noise is mathematically modeled as random phase and amplitude modulation. It is measured in dBc/Hz @ foffset. dBc/Hz stands for dB down from the carrier (the c) in 1 Hz bandwidth. For example -90dBc/Hz @ 100kHz offset from a CW sine wave at 2.4GHz.
59
- 90dBc/Hz 100kHz
fo
Reducing Phase Noise (1)

Requirement 1: The tuning network (or the resonator) of an oscillator must have a high Q factor. This is an indication of low dissipation loss in the tuning network (See Chapter 3a impedance transformation network on Q factor).
Xtune Xtune
X1
Tuning Network with High Q
X1
f
f
Tuning Network with Low Q

f
-X1
2|X1|
-X1 Ztune = Rtune +jXtune

2|X1|
April 08
60
30
Reducing Phase Noise (2)

A Q factor in the tuning network of at least 20 is needed for medium performance oscillator circuits at UHF. For highly stable oscillator, Q factor of the tuning network must be in excess or 1000. We have looked at LC tuning networks, which can give Q factor of up to 40. Ceramic resonator can provide Q factor greater than 500, while piezoelectric crystal can provide Q factor > 10000. At microwave frequency, the LC tuning networks can be substituted with transmission line sections. See R. W. Rhea, Oscillator design & computer simulation, 2nd edition 1995, McGraw-Hill, or the book by R.E. Collin for more discussions on Q factor. Requirement 2: The power supply to the oscillator circuit should also be very stable to prevent unwanted amplitude modulation at the oscillators output.
More on Varactor
The varactor diode is basically a PN junction optimized for its linear junction capacitance. It is always operated in the reverse-biased mode to prevent nonlinearity, which generate harmonics.
Vj Reverse biased Linear region
Cjo
Cj
Forward biased Vj
As we increase the biasing voltage VDC , Cj decreases, hence the oscillation frequency increases. The abrupt junction varactor has high Q, but low sensitivity (e.g. Cj varies little over large voltage change). The hyperabrupt junction varactor has low Q, but higher sensitivity.
0
April 08
62
31
A Better Variable Capacitor Network

The back-to-back varactors are commonly employed in a VCO circuit, so that at low Vcontrol, when one of the diode is being affected by the AC voltage, the other is still being reverse biased. When a diode is forward biased, the PN junction capacitance becomes nonlinear. The reverse biased diode has smaller junction capacitance, and this dominates the overall capacitance of the back-to-back varactor network. This configuration helps to decrease the harmonic distortion. To suppress RF signals Vcontrol
Symbol for Varactor
63
To ve resistance amplifier
At any one time, at least one of the diode will be reverse biased. The junction capacitance of the reverse biased diode will dominate the overall capacitance of the network.
April 08
Example 3.1 VCO Design for Frequency Synthesizer

To design a low power VCO that works from 810 MHz to 910 MHz. Power supply = 3.0V. Output power (into 50 load) minimum -3.0 dBm.
April 08
64
32
Example 3.1 Cont

Checking the d.c. biasing and AC simulation.
DC
DC DC1
S-PARAMETERS
S_Param SP1 Start=0.7 GHz Stop=1.0 GHz Step=1.0 MHz
V_DC SRC1 Vdc=3.3 V R RB R=33 kOhm
b82496c3120j000 LC param=SIMID 0603-C (12 nH +-5%)
100pF_NPO_0603 Cc2 pb_phl_BFR92A_19921214 Q1 4_7pF_NPO_0603 Term Cc1 Term1 Num=1 Z=50 Ohm 2_2pF_NPO_0603 C1 R RL R=100 Ohm
Z11
April 08
3_3pF_NPO_0603 C2 R RE R=100 Ohm
65
Example 3.1 Cont

Checking the results real and imaginary portion of Z1 when output is terminated with ZL = 100 .
m1 freq=775.0MHz m1=-89.579
-40 -50 -60
m2 freq=809.0MHz m2=-84.412
imag(Z(1,1)) real(Z(1,1))
-70 -80
m2 m1
-90 -100 -110 -120 0.70 0.72 0.74 0.76 0.78 0.80 0.82 0.84 0.86 0.88 0.90 0.92 0.94 0.96 0.98 1.00
freq, GHz
April 08
66
33
Example 3.1 Cont

The resonator design.
PARAMETER SWEEP
ParamSweep Sweep1 SweepVar="Vcontrol" SimInstanceName[1]="SP1" SimInstanceName[2]= SimInstanceName[3]= SimInstanceName[4]= SimInstanceName[5]= SimInstanceName[6]= Start=0.0 Stop=3 Step=0.5
S-PARAMETERS
S_Param SP1 Start=0.7 GHz Stop=1.0 GHz Step=1.0 MHz
Var Eqn
VAR VAR1 Vcontrol=0.2
L L1 L=10.0 nH R= C C3 C=0.68 pF Term Term1 Num=1 Z=50 Ohm
Vvar V_DC SRC1 Vdc=Vcontrol V L L2 L=33.0 nH R= 100pF_NPO_0603 C2 BB833_SOD323 D1
April 08
67
Example 3.1 Cont

The resonator reactance.
120
-X1 of the destabilized amplifier

m1 freq=882.0MHz m1=64.725 Vcontrol=0.000000 m1
100
-imag(VCO_ac..Z(1,1)) imag(Z(1,1))
80
60
40
Resonator reactance as a function of control voltage

April 08
20
The theoretical tuning range
0 0.70 0.75 0.80 0.85 0.90 0.95 1.00
freq, GHz
2006 by Fabian Kung Wai Lee 68
34
Example 3.1 Cont

The complete schematic with the harmonic suppression filter.
TRANSIENT
Tran Tran1 StopT ime=1000.0 nsec MaxTimeStep=1.0 nsec DC DC1
DC
Low-pass filter
VtPWL Src_trigger V_T ran=pwl(time, 0ns,0V, 1ns,0.1V, 2ns,0V) V_DC SRC1 Vdc=3.3 V R RB R=33 kOhm
b82496c3120j000 L3 param=SIMID 0603-C (12 nH +-5%) 100pF_NPO_0603 Cc2 b82496c3150j000 L4 param=SIMID 0603-C (15 nH +-5%)
b82496c3100j000 L1 param=SIMID 0603-C (10 nH +-5%) 4_7pF_NPO_0603 C Cc1 C6 C=2.2 pF pb_phl_BFR92A_19921214 Q1 2_7pF_NPO_0603 C8 0_47pF_NPO_0603 C9 R RL R=100 Ohm
b82496c3330j000 L2 param=SIMID 0603-C (33 nH +-5%) Vvar V_DC SRC2 Vdc=1.2 V 100pF_NPO_0603 C4 R R1 R=100 Ohm BB833_SOD323 D1
C C5 C=0.68 pF
C C7 C=3.3 pF
R RE R=100 Ohm
April 08
69
Example 3.1 Cont

The prototype and the result captured from a spectrum analyzer (9 kHz to 3 GHz).
Fundamental -1.5 dBm
Harmonic VCO suppression filter

- 30 dBm
April 08
70
35
Example 3.1 Cont

Examining the phase noise of the oscillator (of course the accuracy is limited by the stability of the spectrum analyzer used).
-0.42 dBm
Span = 500 kHz RBW = 300 Hz VBW = 300 Hz
300Hz April 08 2006 by Fabian Kung Wai Lee 71
Example 3.1 Cont

VCO gain (ko) measurement setup:
Variable power supply
V_DC SRC1 Vdc=3.3 V R RB R=33 kOhm
b82496c3120j000 L3 param=SIMID 0603-C (12 nH +-5%) 100pF_NPO_0603 Cc2 b82496c3150j000 L4 param=SIMID 0603-C (15 nH +-5%) R Rattn R=50 Ohm Port Vout Num=2
b82496c3100j000 L1 param=SIMID 0603-C (10 nH +-5%) 4_7pF_NPO_0603 Cc1 C C5 C=0.68 pF C C6 C=2.2 pF pb_phl_BFR92A_19921214 Q1 2_7pF_NPO_0603 C8
Spectrum Analyzer
0_47pF_NPO_0603 C9
Vvar Port Vcontrol Num=1 R Rcontrol R=1000 Ohm BB833_SOD323 D1
C C7 C=3.3 pF
R RE R=100 Ohm
April 08
72
36
Example 3.1 Cont

Measured results:
fVCO / MHz
950
900
850
800
750 0.0
April 08
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Vcontrol/Volts
73
Example 3.1 Cont

The PLL analysis:
PFD PLL with 3rd order loop filter with zero
Parameters of the PLL: VCO gain:
6 ko := 40.7 10 (MHz per volt)
PFD with charge pump: Loop filter:
Io := 1.0 10
3 9
(Ampere)
R2 := 10000 C2 := 1 10 R3 := 33000 C1 := 100 10

12
C3 := 0.1 10
Note that the divider ratio is given by N and is settable
Transfer function vco(s)/in(s) computation as in Appendix A of the notes: T1 := R2 C1 C2 C1 + C2 T2 := R2 C2 T1 ( 1 + s T2) s T2 C1 ( 1 + s T1) ( 1 + s T3) T3 := R3 C3
ZLPF( s ) := k := Io 2
The normalized transfer function:
The loop gain: T( s , N) := k ko s N ZLPF( s )
k ko ZLPF( s ) s H( s , N) := N 1 + k ko ZLPF( s ) s N
1
April 08
74
37
Example 3.1 Cont

Plotting the Transfer Function in frequency domain: k := 1.. 10000 f := 200
20
20 log( H( i 2 k f , 1)
)
20
40
1 .10
1 .10
1 .10
1 .10 2 k f
1 .10
1 .10
200
100
arg( H( i 2 k f , 4400) ) 180
100
200
April 08
1 .10 1 Wai 2006 by Fabian Kung.10 Lee 1 .10
1 .10 2 k f
1 .10
1 .10
75
38

lesson9-RF Oscillators

Hochgeladen von

Dokumentinformationen

Originalbeschreibung:

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

lesson9-RF Oscillators

Hochgeladen von

Copyright:

Verfügbare Formate

9 - RF Oscillator

2006 by Fabian Kung Wai Lee

2006 by Fabian Kung Wai Lee

2006 by Fabian Kung Wai Lee

1.0 Oscillation Concepts

2006 by Fabian Kung Wai Lee

Classical Positive Feedback Perspective on Oscillator (1)

2006 by Fabian Kung Wai Lee

Classical Positive Feedback Perspective on Oscillator (2)

2006 by Fabian Kung Wai Lee

Example of Tuned Feedback Oscillator (1)

2.0 1.5 1.0

V_DC SRC1 Vdc=3.3 V R RB1 R=10 kOhm

0.5 0.0 -0.5

VC C Cc2 C=0.01 uF pb_mot_2N3904_19921211 Q1 R RB2 R=10 kOhm R RE R=220 Ohm C CE C=0.01 uF

2006 by Fabian Kung Wai Lee

Example of Tuned Feedback Oscillator (2)

VC C Cc2 C=0.1 uF pb_m ot_2N3904_19921211 Q1 VE R RE R=100 Ohm

R RB2 R=4.7 kOhm

2006 by Fabian Kung Wai Lee

Example of Tuned Feedback Oscillator (3)

A 16 MHz Transistor Common-Emitter Crystal Oscillator

VC C Cc2 C=0.1 uF pb_mot_2N3904_19921211 Q1 R RB2 R=10 kOhm R RE R=220 Ohm C CE C=0.1 uF

sx_stk_CX-1HG-SM_A_19930601 XTL1 Fres=16 MHz

2006 by Fabian Kung Wai Lee

Introduction RF Oscillator (1)

Introduction RF Oscillator (2)

2006 by Fabian Kung Wai Lee

Introduction RF Oscillator (3)

2006 by Fabian Kung Wai Lee

Wave Propagation Stability Perspective (1)

Compare with equation (1.1a)

2006 by Fabian Kung Wai Lee

Feedback is provided by the reflection due to 13 source mismatch

Wave Propagation Stability Perspective (2)

2006 by Fabian Kung Wai Lee

Oscillation Start-Up Requirements (1)

(R1 Z o ) + jX1 (R1 + Z o ) + jX1

Port 2 Source Network Port 1 R1 + jX 1 Z1 V= Vs = Vs R1 + Rs + j ( X 1 + X s ) Z s + Z1

2006 by Fabian Kung Wai Lee

Oscillation Start-Up Requirements (2)

Let o be the desired oscillation frequency

2006 by Fabian Kung Wai Lee

Oscillation Start-Up Requirements (3)

(1.5b) (1.6a) (1.6b)

Oscillation Start-Up Requirements (4)

2006 by Fabian Kung Wai Lee

What Happens During Oscillation Start-Up?

2006 by Fabian Kung Wai Lee

2.0 Fixed Frequency Oscillator Design

2006 by Fabian Kung Wai Lee

Procedures of Designing Fixed Frequency Oscillator (1)

2006 by Fabian Kung Wai Lee

Procedures of Designing Fixed Frequency Oscillator (2)

2006 by Fabian Kung Wai Lee

Making an Amplifier Unstable (1)

2006 by Fabian Kung Wai Lee

Making an Amplifier Unstable (2)

S_StabCircle S_StabCircle1 SSC=s_stab_circle(S,51)

Common Base Configuration

R Rb1 R=10 kOhm

StabFact StabFact1 K=stab_fact(S)

L_StabCircle L_StabCircle1 LSC=l_stab_circle(S,51) Vout