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# ISCAS 2000 - IEEE International Symposium on Circuits and Systems, May 28-31, 2000, Geneva, Switzerland

A UNIVERSAL ANALYTIC CHARGE INJECTION MODEL Yongwang Ding and Ramesh Harjani Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455, USA
ABSTRACT In this paper we present an analytical model for charge injection in MOS switches that is valid for all regions of operation. The model is general and can be applied for different load conditions. We analyze and develop two separate charge injection models for the different operating conditions. A simple continuos model that is valid for all conditions is then stitched together using appropriate functions. Simulation results from this model agrees well with previously published measurement results. The model is used to predict charge injection error and nonlinearity.
Rs

## Figure 1: A simple sample-and-hold circuit

Ron Vclk Cs Cox Ch Vgs=Vtn High

1. INTRODUCTION
Tclk Low Time

where,

## is the average value of

The turn-off transient can be broken up into fast-moderate and slow turn-off conditions. Individual closed form analytic models
0-7803-5482-6/99/\$10.00 2000 IEEE

First, the turn-off transient can be broken up into two separate states, conducting and cut-off. The switch is considered to be conducting when the gate voltage is greater than and the switch is considered to be cut-off when the gate voltage is . During the turnoff transient, the switch is less than usually in non-equilibrium. However, for extremely slow turnoff conditions the switch will approach equilibrium state for each time point in the transient. If during the turn-off transient the channel
d U  R d  U  d R d 

I-144

# @ X  6 \$!  #

#X iY" p W aR #Y" X

# p YX 

# p h  x5Gw% @ \$!  y 2

#! \$"

#! xgR a\$"

p  h  xGw%v u 6 2

#X #! % @ " 6 \$"

Sample-and-holds (SH) are important circuit components in most modern analog sample-data systems. In general, in many such systems the overall system accuracy is limited by the nonlinearity introduced by the input sample-and-hold circuit. One of the limiting mechanisms for fully differential circuits is the nonlinearity introduced by the SH charge injection error . Therefore, adequate modeling of charge injection is extremely important to predict the performance of sample-data circuits. A number of different models have been created to provide some insight into the charge injection problem [2, 3, 4]. Unfortunately, they provide results from numerical simulations that at best only provide general trends. Additionally, they are limited to the moderate turn-off region. Charge injection is usually modeled for the circuit shown in Figure 1. A simplied model for this circuit and a diagram for the clock is shown in Figure 2. The moderate turn-off region is specied by the following inequality, i.e. . Here, is the fall time for the switch gate , where is dened as the time it takes for the gate voltage voltage to reach the threshold voltage . The input source time constant is given by , where is the input source resistance, and is the input source capacitance. Likewise, the , channel charge transient time is given by where is the switch on resistance, and is the gate capacitance. We also dene an additional time constant that represents the settling time for the hold capacitor as shown in equation 1.
D B @ 2 ECA5 90 # 87% '6 H  G2 5  )' P 2 R  QTS42 0 # F' P 2 QI0  2 #! \$"  2 0  ' %  431)(&   %   H        2 # F'

Ts=RsCs

Tox=RonCox

## Figure 2: Simplied model and time constants for the SH

can then be developed for these two operating conditions. A general model valid for all switching speeds can then be reconstructed from these individual models. In the next section we rst introduce the charge injection mechanism. This is followed by our universal model. Then nally we present simulations results and compare our results with measurements. 2. CHARGE INJECTION MECHANISM In this section, we discuss the mechanisms that cause charge injection. For simplicity we only discuss a NMOS switch. However, a PMOS device would behave similarly. When an NMOS transistor is on the amount of charge in the , is a function of the input signal, as shown in equachannel, tion 3. The threshold voltage, , is also a function of the input signal due to back-gate effect and is one of the primary causes of switch nonlinearity. This dependence is shown in equation 4. (3) (4)

## s tEB q r f dc 0 ` #X W geb aYIA# V% # ' ' p h P !  Q i

@ \$6 # ' U

# '

Ron/2
Ec

Ron/2

Efi

e
Ef Ev Gate Channel Substrate

Rs

Cs

Cox

Ch

## Figure 4: Fast turn-off model for conducting state

, and is the forward bias voltage. Since the where bias voltages for the source-channel junction and drain-channel junction are the same, their resistances should also be the same. Therefore the channel charge is equally split between the drain and the source for this period after cut-off. The ratio of the charge loss into the substrate and the charge transferred to the source and the drain is proportional to their conductance, as is given by equation 8.
E  # | 1' P FE ' l E d d u % d vu d Pd R d vu ` i u }

Depending on the switch turn-off speed, we separate our analysis into two conditions: moderate-to-fast turn-off and slow turn-off. 3.1. Moderate-to-fast turnoff We dene moderate-to-fast turnoff when . As mentioned in the previous section the switch is in non-equilibrium for most of the turn-off transient. For moderate-to-fast turn-off even just reaches , a large fraction of the channel charge when is still left in the channel as . Before cut-off a small fraction of the channel charge, represented as , has already been distributed into the source and drain. Their relationship is given by equation 5.
d u d u d d vu 5ev2 d R d u # \$!  % u  h  u    

The charge injected to the hold capacitor after the switch is in the cut-off state is given by equation 10.
d d u 0 @ p i 90 6 i % d Pd u

(5)
o n r m j @ pqQl3kp i 6 s

Therefore, from equations 5, 6 and 10 the total charge injected onto the hold capacitor for the moderate-to-fast turn-off case is given by equation 11.
0 H g # fa  D  o m j n @ qp r Ql p i 6 5v2 e k p u i % P u

(6)

By using appropriate stiching functions we obtain the complete moderate-to-fast charge injection model shown in equa-

I-145

p os nr m j @ qw1l kp i 6

H g # f  D  o  j n @ qp r m l kp i 6 @ 5e 2

P Q2

P 2 QTR @

p z@

p oy qn x

p oy qn x

u Rhi 6  2

u Rhi 6  2

p i 6

p i t

We model the switch in the conducting state as shown in Figure 4. During the conducting state a fraction of the channel charge, , is split up into the drain and source. The charge split ratio is derived in the appendix. Using the derivations in the appendix the charge that is injected into the hold capacitor in Figure 1 is given by equation 6.
p osnr l qwm 9jp zf i P Q2 pz@ p oC qwn x y u R v4i 6E42  p i t5d u i % Pd u d u

E 

dd u E d d u

a

PC '

## 3. CHARGE INJECTION MODEL

, and are the channel charge transferred to the where source, to the hold capacitor and to the substrate after the switch is in the cut-off state. The resistance between the channel and the substrate, , depends on the substrate doping density. We dene the charge leakage factor in equation 9.
a d d u d P d u d d u

aIEj G ~  0 u }

% # 1' | r IB q %

charge is able to distribute much faster than the switch turns off, then we can assume that the switch reaches its equilibrium state at all times. However, if the switch turns off faster than the channel charge is able to redistribute then the switch operates in a nonequilibrium state. In most cases, the MOS switch operates somewhere in between equilibrium and non-equilibrium. Even when the switch has reached the off state there may still be some charge in the channel. We show the energy band diagram for an NMOS switch in non-equilibrium in Figure 3. In this condition, the forces caused by the electrical eld and diffusion are not balanced and the source-channel and the drain-channel junctions can be considered to be forward biased. The remaining charge in the channel is then injected into the source, drain and the substrate. Because of the effectively forward biased channel-source and channel-drain junctions the preferred directions are the source and the drain. However, for extremely long channels and short fall times, some of the channel electrons will also be injected into the substrate resulting in substrate injection. For modern processes and typical gate sizes the amount of substrate injection is negligible. In the next section we derive our universal charge injection model.

After the switch turns off, the switch is operating in an nonequilibrium state as shown in Figure 3. The effective resistances of source-to-channel and drain-to-channel can be modeled as forward biased p-n junctions whose resistance is given by equation 7. (7)

(8)

(9)

(10)

{s

P Q2TR @

g H h# A  D f  p oy qwn x u R 4i 6  2

d d u

(11)

Rsw

Rsw
0.9

ox
Ch/Cs=393n/39.3n

0.8

Cox

Ch
0.7

0.6

Ch/Cs=39.3n/39.3n

Qh/Qox

0.5

## Figure 5: Slow turn-off model for conducting state

0.4

0.3

Ch/Cs=39.3n/393n

tion 12.
0  @ pqm l jp i 6 o r n e p p ) u Sm l j qo y n r %P u

0.2

0.1

0 14 10

10

12

10

10

10

10

10

10

10

## (12) the universal charge injection model as shown in equation 16.

0 s  u q r m l kp i p wn o j p) u p oy n r qwm l j e % P u

4. SIMULATION RESULTS In this section we use the universal model (equation 16) to compare our predictions with measurements and provide additional results. For our rst experiment we use the same dimentional NMOS switches and capacitors as done in . Three seperate sets of source and hold capacitor ratios are used. For this simulation we set the substrate injection factor to zero. The results are shown in Figure 6. As can be seen in this gure the predictions from our model t extremely well with measurement results from [2, 3]. Measurement results are only provided for the moderate-to-fast turn-off condition. It is also worth noting that the charge injected into the hold capacitor decreases signicantly for the slow turn-off condition. Our universal model can be used to analyze most circuits at any operating speed. In our next experiment we use an NMOS in the HP 0.5 CMOS process, switch with the charge injection error is shown in Figure 7, which includes gain and nonlinearity error. The nonlinearity is seperated and is shown in Figure 8. Both the total charge injection error and the nonlinearity decrease when the switch turn off time is increased. Therefore, one way to reduce nonliearity due to charge injection is to reduce the rise and fall times of the clock signals. 5. CONCLUSIONS In this paper we have developed a completely analytical and universal charge injection model valid for all speeds of operation. Predictions from the model were compared to measurement results
B Aa% EB

(13)

where S is of the same order as , and much smaller than . Therefore, equation 13 can be approximated by equation 14
i dd k u d Pvu d @ 3 2 # |186 B i '

(14)

Using similar analysis methods as in the previous cases, the charge injection model for the slow turn-off case is given by equation 15.
H g # f  D  v2 e @ p i 6 qp or Ql p n i m j q4l p iP u p oy n r m j %

## (15) Combining both cases with a conditional envelop we can write

I-146

po s Eqn u

qm 9p zf p os nr l j i

qp 4l p @ o n rm j i

p i 6

p i

We now model the slow turn-off case. For this case, both and are . Because the charge on distributes into the ground node much faster than the switch is able to turn-off, therefore, almost all the charge transfers from the channel to ground immediately. Figure 5 shows the effective model, where represents the resistance between the channel and the source/drain. equals when the switch is on, and equals when the switch is off. For the slow turn-off case the switch is able to reach equilibrium for all times, therefore, no excess charge is left ). Thereon the hold capacitor when the switch is off ( fore, the charge that is left in the channel transfers to the source and to the drain in proportion to the conductance seen at these nodes as shown in equation 13.
 )' # Q' | # e!" h %  i i iA a n 5 xE y E n  2 % y B # '     ' H I

po hS qwn



 42 h 2

P 2

P Q2

42 

 2

h 

PQ2 # \$! 

## Swtich Turn off Time: Tclk (s)

o hapqwn

o s S pqwn u @ qw1l p i 6 @ p o n r m j

## p " m y qo y n r p os nr j @ qwm l p i 6 " l m p qo y n r y   B i  %

Figure 6: Simulation results of a NMOS switch charge injections vs. switch turning off time. W/L=10000/22, =79pF, =0.5 and =2V. (a) =39.3nF, =393nF; (b) =39.3nF, =39.3nF and (c) =393nF, =39.3nF.

p i 6

p i

(16)

0.02

10

0.018

Ch/Cs=1p/1p
0.016

10

Ch/Cs=1p/1p

10

Ch/Cs=10p/1p

0.014

Siwtch Nonlinearity

0.012

10

Ch/Cs=1p/10p
0.01

10

Ch/Cs=1p/10p
10
6

0.008

0.006
10
7

0.004

Ch/Cs=10p/1p
0.002

10

0 16 10

10

14

10

12

10

10

10

10

10 16 10

10

14

10

12

10

10

10

10

## Swtich Turning off Time Tclk (s)

Figure 7: Simulation results of the charge injection error vs. switch turning off time in a NMOS switch. . (a) ; (b) ; (c) .
%  2 B Q2 P  2 5i B 142 B P 2 i %  B Aaw% aB P Q2  2 i B 142 B P 2 i %  i B 5i

Figure 8: Simulation results of the switch nonlinearity vs. switch turning off time.
@ \$6 d u U { vs   I  H p os nr m j qw4l p zf i p oy qwn x p P Q2 R @ \$6 d u U p @ p oy qwn x p oy qwn x % u u U

where, is the charge stored on the source capacitor, and the is the charge lost into the ground node. These two charge quantities are given by equations 19 and 21.
 2 R P 4TQ2 l j i s r 3p  2 p Q2 P p i @ \$6 d u U i % @ \$6 d u U u d p oy qn u u

6. REFERENCES
%

In the case of moderate turn-off, i.e, , equations 17 and 18 can be approximated by equations 22 and 22.
  2 R P h 4FQ2 @ \$6 d u @  \$6 d u R i U  U P Q2  Q2 2 R P @ \$6 d u @  \$6 Pd u U  P 2

 Eric A. Vittoz George Wegmann and Fouad Rahali, Charge injection of analog mos switches, IEEE Journal of SolidState Circuits, vol. SC-22, no. 6, pp. 10911097, December 1987.  C. Eichenberger and W. Guggenb hl, Charge injection of analogue cmos switches, IEE Proceedings-G, vol. 138, no. 2, pp. 155159, April 1991.

Then the charge split ratio between drain and the source is given by equation 23.
u R vGi 42  P Q2 i d @ \$6  u  @  \$6 Pd u 

## Appendix: Charge Split Ratio

@

(17)

I-147

P 2 QR @

R hi 6  2

R 6  hi a42

t p i d u i

% Pd u

In this appendix we derive the ratio for the charge split between the drain and the source for the turn-off transient when the switch is still conducting. During this transient there are two mechanisms in operation. One, the channel charge splits to the drain and the source and two, there is a redistribution of charge from , the channel the drain/source to the source/drain. For charge is initially split equally between the source and the drain. The redistribution of charge from drain ( ) to the source ( ) is determined by their voltage difference and time constant. Therefore, the total charge transfered to the hold capacitor ( ) is given can be approximated by by equation 17, and the total charge to equation 18.
P Q2 r j i s l p H 5 2 R  P S42 P Q2 p 42  p i @ \$6 d u U i % @ \$6 Pd u U

with the effective source capacitance By replacing in equation 17, the total charge injected into the drain is given by equation 24. (24)

R zi 6  2

 2

 Mahesh Patil He-Hurn Shieh and Bing J. Sheu, Measurement and analysis of charge injection in mos analog switches, IEEE Journal of Solid-State Circuits, vol. SC-22, no. 2, pp. 277281, April 1987.

 TQ2 2 R P l j i H I s r 3p  42 p P 2

 E R P  2FQ2 4U 2 P A @ \$6 vu U d

 David Johns and Ken Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc, New York, 1997.

Q '  2 u d !

u d

and showed excelled agreement. However, additional measurement results are needed to verify the model for the slow turn-off condition. Although only a simple sample and hold has been analyzed in this paper the model is applicable for any MOS sampleddata application.

% @ \$6 d u U

(18)

(19)

@ \$6 d u U

(20)

(21) (22)

(23)