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EE141- Spring 2003

Lecture 4 Design Rules CMOS Inverter MOS Transistor Model

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Todays lecture
Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis

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Important!
Labs start next week You must show up in one of the lab sessions next week If you dont show up you will be dropped from the class
Unless you let me know that you still want to be in the class

Homework 2 will be posted later today. Due next Thursday, February 6.


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Design Rules

Jan M. Rabaey

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3D Perspective
Polysilicon Aluminum

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Design Rules
Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules)

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CMOS Process Layers


Layer Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Color Yellow Green Green Red Blue Magenta Black Black Black Representation

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Layers in 0.25 m CMOS process

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Intra-Layer Design Rules


Same Potential 0 or 6 10 3 Active 3 2 Select Contact or Via Hole 2 2
Metal2 3
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Different Potential 9 Polysilicon 2 Metal1 3


4

Well

Transistor Layout
Transistor

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Vias and Contacts


2 Via 1 1 5 Metal to 1 Active Contact Metal to Poly Contact 3 2 4

2 2

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Select Layer
2 3 2 1 3 3 Select

Substrate
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Well

CMOS Inverter Layout


GND In VD D A A

Out (a) Layout

A p-substrate n+ (b) Cross-Section along A-A


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A n p+ Field Oxide

Layout Editor

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Design Rule Checker

poly_not_fet to all_diff minimum spacing = 0.14 um.

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Sticks Diagram
V DD In 3 Out
Dimensionless layout entities Only topology is important Final layout generated by compaction program

1
GND
Stick diagram of inverter
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CMOS Inverter MOS Transistor


Jan M. Rabaey

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What is a Transistor?
A MOS Transistor
|VGS|

A Switch!
VGS VT Ron S D

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NMOS and PMOS


NMOS Transistor
V GS>0 G V GS<0

PMOS Transistor
G

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The CMOS Inverter: A First Glance


V DD

V in

V out CL

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CMOS Inverter
N Well VDD 2

VDD

PMOS

PMOS In Out
In Polysilicon

Contacts

Out Metal 1

NMOS
NMOS GND
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Two Inverters
Share power and ground

Abut cells

VDD

Connect in Metal

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Switch Model of CMOS Transistor


|VGS|

Ron

|VGS | < |VT|


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|VGS| > |V T|

CMOS Inverter First-Order DC Analysis


V DD V DD Rp

V out Rn

V out

VOL = 0 VOH = VDD VM = f(Rn, Rp)

V in 5 V DD
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V in 5 0

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CMOS Inverter: Transient Response


V DD Rp V DD

tpHL = f(Ron.CL) = 0.69 RonCL


V out CL Rn V out CL

V in 5 0 (a) Low-to-high
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V in 5 V DD (b) High-to-low

CMOS Properties
Full rail-to-rail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power dissipation Direct path current during switching

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The MOS Transistor


Polysilicon Aluminum

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MOS Transistors Types and Symbols


D D G

G S

NMOS Enhancement NMOS Depletion


D D

G S

PMOS Enhancement

NMOS with Bulk Contact

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Threshold Voltage: Concept

S n+

+ VG S G

n+

n-channel p-substrate B
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Depletion region

The Threshold Voltage


Threshold

Fermi potential

2F is approximately - 0.6V for p-type substrates the body factor VT0 is approximately 0.45V for our process

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The Body Effect


0.9 0.85 0.8 0.75 0.7

V (V)

0.65 0.6 0.55 0.5 0.45 0.4 -2.5

-2

-1.5

-1

-0.5

BS

(V)

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The Drain Current


Charge in the channel is controlled by the gate voltage:

Drain current is proportional to charge and velocity:

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The Drain Current


Combining velocity and charge:

Integrating over the channel:

Transconductance:

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Transistor in Linear
Linear (Resistive) mode
S VGS G n+ VDS D n+ L x ID

V(x)

p-substrate B

MOS transistor and its bias conditions


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Transistor in Saturation
VGS VDS > VGS - VT D

G S n+
-

VGS - VT

n+

Pinch-off

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Saturation
For VGD < VT, the drain current saturates
k W I D = n (VGS VT )2 2 L

Including channel-length modulation


k W I D = n (VGS VT )2 (1 + VDS ) 2 L

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Modes of Operation
Cutoff:

VGS < VT
Resistive:

ID = 0
2 kn W VDS ID = (VGS VT )VDS 2 L 2

VT < VGS ; VGS VT > VDS

Saturation:

VT < VGS ; VGS VT < VDS


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k W I D = n (VGS VT )2 2 L

Current-Voltage Relations A Good Ol Transistor


6 x 10
-4

VGS= 2.5 V

Resistive
4 ID (A)

Saturation
VGS= 2.0 V

VDS = VGS - VT
VGS= 1.5 V

Quadratic Relationship

VGS= 1.0 V

0.5

1 VDS (V)

1.5

2.5

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A model for manual analysis

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Current-Voltage Relations The Deep-Submicron Era


2.5 x 10
-4

Early Saturation
2

VGS= 2.5 V

VGS= 2.0 V
1.5 ID (A)

VGS= 1.5 V

Linear Relationship

0.5

VGS= 1.0 V

0.5

1 VDS (V)

1.5

2.5

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Velocity Saturation
n (m/s) sat = 105
Constant velocity

Constant mobility (slope = )

c = 1.5
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(V/m)

Velocity Saturation
ID
Long-channel device VGS = VDD Short-channel device

V DSAT
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VGS - V T

VDS

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ID versus VGS
6 5 2 4
ID (A)

x 10

-4

x 10 2.5

-4

quadratic

linear
1.5
ID (A)

3 2 1 0 0

0.5

quadratic
0.5 1
VGS(V)

1.5

2.5

0 0

0.5

1
VGS(V)

1.5

2.5

Long Channel
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Short Channel

ID versus VDS
6 5 4 ID (A) 3 2 1 0 0 x 10
-4

VGS= 2.5 V

x 10 2.5

-4

VGS= 2.5 V
2

Resistive Saturation VDS = VGS - VT


VGS= 1.5 V
0.5 ID (A)

VGS= 2.0 V

VGS= 2.0 V
1.5

VGS= 1.5 V

VGS= 1.0 V
0.5 1 VDS(V) 1.5 2 2.5 0 0 0.5 1 VDS(V) 1.5

VGS= 1.0 V
2 2.5

Long Channel
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Short Channel

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Including Velocity Saturation


Approximate velocity:

And integrate current again:

In deep submicron, there are four regions of operation: (1) cutoff, (2) resistive, (3) saturation and (4) velocity saturation
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Regions of Operation

Long Channel
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Short Channel

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An Unified Model for Manual Analysis


G

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Regions of Operation
2.5 x 10
-4

VDS=VDSAT
2

Linear
1.5

Velocity Saturated

ID (A)
1

0.5

VDSAT=VGT VDS=VGT

Saturated
1 1.5 2 2.5

0.5

V DS (V)
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A PMOS Transistor
0 x 10
-4

VGS = -1.0V -0.2 VGS = -1.5V -0.4


ID (A)

-0.6

VGS = -2.0V

Assume all variables negative!

-0.8

VGS = -2.5V

-1 -2.5

-2

-1.5
VDS (V)

-1

-0.5

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Transistor Model for Manual Analysis

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The Transistor as a Switch


VGS VT Ron S
ID

D
Rmid R0

V GS = VD D

V DS VDD/2 VDD

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The Transistor as a Switch


7 x 10
5

(Ohm) R

eq

0 0.5

1.5

2.5

DD

(V)

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The Transistor as a Switch

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Future Perspectives

25 nm MOS transistor (Folded Channel)


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