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What is the impact of Xilinxs 3D silicon interposer announcement?

Xilinx made a big announcement last month when announcing their intention to commercialize 3D silicon interposers based on TSV interconnects for their nextgeneration 28nm FPGAs in their Virtex 7 future product line. Lets look at why this announcement is so important: To begin with, Xilinx is the first large semiconductor company to jump into the free space of 3D integration in the logic area. Its quite impressive that a fabless company is taking the first big step in this new direction for manufacturing. Indeed, Xilinx is kind of cleaning the pipeline so that other players can quickly follow in the FPGA and high-performance ASIC spaces.
Interview with Dr. William Chen of ASE

Yole Dveloppement recently had an opportunity to interview William (Bill) Chen about his long career in microelectronics packaging and his current activities as a part of ASE.
Yole Dveloppement: Dr Chen before we start our questions on ASE, can you share a little on your past history. Its our understanding that you had a full career at IBM before coming to ASE and that you just finished two terms as President of the IEEE Component, Packaging and Manufacturing Technology Society (CPMT). Can you fill us in on this part of your past? Bill Chen: After I completed my PhD studies at Cornell University, I started working at the IBM Development Laboratory in Endicott New York. It was still at an early point in the history of electronics and certainly an exciting time at IBM. I soon gravitated to work in electronic packaging. The science was intriguing and technology was new. I learned how to do engineering from concept nucleation, feasibility demonstration, and product development to manufacturing. I spent over 33 years at IBM in various technical and R&D management positions. After retirement, I joined the Institute of Materials Research and Engineering (IMRE) in Singapore. My initial role at IMRE was to establish a research program in Electronic Packaging within this young Research Institute. As it turned out I became the Director of IMRE, nurturing the young Institute to become the premier materials research institute in the region. I retired from IMRE to join ASE in 2000. I was President of IEEE CPMT Society from 2006 to 2009. I am currently co-chair of the ITRS Assembly and Packaging ITWG. I have been elected a Fellow of ASME and IEEE.
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Next up for 3D ICs: Wide I/O

any companies are publicly discussing their 3D IC integration roadmaps and the role wide input/output (I/O) interfaces will play. For starters, South Korean-based electronics giant Samsung hails the wide I/O and through-silicon via (TSV) combination as the best of both worlds in terms of achieving performance and thin multipledie stacks. Memory maker Elpida, based in Tokyo, Japan, is actively developing next-gen mobile wide I/O DRAM, which expands the I/O interface bus width, and mounting technologies that use TSVs. In fact, Elpida has installed a production line at its Hiroshima Plant to develop TSV and mass production technologies for multiple connections using TSVs. And Nokia, an Espoo, Finland-based leader in the transformation and growth of the converging Internet and communications industries, describes the evolution of 3D IC integration as moving from 2.5 to true 3D, relying on various applications of TSVs in silicon interposers, memories, and ICs. The company plans to integrate wide I/O interface structures using TSVs for mobile phones in volume by 2013.
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The wide I/O interface is already being embraced as the next step in the evolution of 3D IC integration.
Why I/O interfaces?
When asked whats fueling the drive to use wide I/O interfaces for 3D ICs, answers vary slightly from company to company but a theme is clearly emerging. As handheld devices become increasingly more sophisticated, applications are emerging that require much higher memory bandwidth, says Jeff Brighton, director of CMOS 3DIC technology development at Texas Instruments (TI; Dallas, Texas). However, fundamental power and thermal limitations remain the same as in todays handsets. The initial version of a wide I/O memory interface will deliver 12.8GB/s of memory bandwidthwhile keeping the processor plus memory system-onchip (SoC) power consumption under control, he adds. ...
Wide I/O interface with TSV for Mobile processors (Courtesy of Texas Instruments)
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But this achievement also clearly raises the importance of supply chain collaboration. This would never have been possible without a close collaboration that began 4 years ago between key partners such as imec for initial R&D, TSMC as a CMOS and interposer turnkey foundry, Amkor and Ibiden for the final substrate, assembly, packaging & test. This announcement also confirms the nearterm availability of a high-reliability via middle copper-filled-type of TSV manufactured in the CMOS wafer foundry environment. It is an important sign that the infrastructure for such vias will be ready soonafter many years of R&D and overcoming numerous technical issues (such as long via filling and plating time, copper vias CTE mismatch with silicon, growing of high aspect ratios isolation / seed / barrier layers in TSV, contamination issues, etc.). Unsurprisingly, foundry giant TSMC seems to be one of the key players the closest to the production of these emerging types of substrates! Last, but certainly not least, Xilinxs annoucement confirms that the 2.5D age is here. Indeed, 3D interposers, based either on glass or silicon substrates, are definitely bridging the gap to the later step toward fully redesigned and partitioned 3DICs. It will be interesting to look at the details of Xilinxs silicon interposer when coming to market in a real product, as it will certainly serve as a first reference design of its kind that could serve another part of the IC industry for different applications, leveraging a real platform available from niche to high-volume markets. Yole Dveloppement has always predicted well in advance the next big trends that will emerge in the 3D packaging space and, hopefully, will continue to do so. In 2006, we announced that TSV would become a reality in MEMS that would move way beyond this space. In 2007, we announced the imminent production of TSV in CMOS image sensors. In 2008, we announced that 2.5D interposers would become a bridge platform before fully redesigned 3DICs. In 2009, we announced the imminent arrival of TSV interconnects in the stacked DRAM memory area, and later on in high-speed, low-power-consumption wide I/O interface applications. But what exactly is wide I/O? I invite you to discover the next big thing ahead for 3DICs inside our 3D Packaging magazine #17! Jrme Baron, baron@yole.fr
Next up for 3D ICs: Wide I/O

From page 1 In a nutshell, the wide I/O interface allows us to reach a high bandwidth at an acceptable power consumption level for a cell phone; it is exhibiting an extremely interesting power per bit ratio. And on top of that, its a standard that should be able to evolve toward even higher performances, with an evolution path from SDR to DDR and frequency increase, points out Yann Guillou, who leads 3D and advanced packaging in the CTO and Strategic Planning Office at ST-Ericsson (Geneva, Switzerland), a leader in innovative mobile platforms and wireless semiconductors. The performance targets are for significantly lower power at a high bandwidth with small form factor. These specifications are being set by JEDECs 42.6 Committee, in collaboration with memory suppliers, with 12.8GB/s bandwidth for initial instantiations, says Matt Nowak, senior director of engineering in the VLSI Technology Group, CDMA Technology Division, at Qualcomm (San Diego, Calif.), a leader in next-generation mobile technologies. The key reason driving wide I/O interfaces is lowering the device power while maintaining the same performance and bandwidth requirements. In some cases you can reduce the power from 10W to 4W, says Calvin Cheung, vice president of engineering for application and design at Taiwanbased packaging and testing house Advanced Semiconductor Engineering (ASE). At San Jose, Calif.-based Avago Technologies, a provider of solutions for wireless communications, the driver for wide memory I/O is a high data rate with low latency. Were seeing 10s of GB/s on products were working on right now, and our customers are moving us to 100s of GB/s and
Elpida DRAM memory roadmap for Wide I/O interface with TSV in next generation smart-phone mobile and tablet devices (Courtesy of Elpida)
would like even more if it was available, says Pete ONeill, Test, Reliability, & Technology Engineer. Regarding latency, the lower the better. Avoiding the latency of a serial interface really helps. As far as power consumption, our customers are limited by power in many cases, so theyre trying to get as much performance as possible within a power envelope. Serial I/O power is a big contributor to overall power, and wed like to eliminate that. Breaking it down a bit more, programmable chip provider Xilinx Inc.s (San Jose, Calif.) Patrick Dorsey, senior director of product management, and Arif Rahman, principal engineer and technology architect, explain that when using field-
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Nokias Wide I/O interface between logic and DRAM memories with need TSV interconnects to meet the next generation performance requirements (Courtesy of Nokia)
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directly connected to the laminate substrate. Flip chip is currently preferred over wire bonding for APE, due to high I/O density and specific performance needs, adds Guillou. So, if the logic die needs to be flip chip and the wide I/O memory needs to be directly connected to the logic die, TSV must be implemented in the logic die so we can obtain a face-to-back configuration where the active part of the memory die is facing the backside of the logic die. Concurring with ST-Ericssons perspective, Nokia believes that for mobile phones there are many-use cases such as 3D graphics, 1080 encode/decode, external HD displays, and especially the related multitasking, which are behind the adoption of the wide I/O interface. We see it as the best approach to integrate logic with DRAM by having the logic flip chip connected to a substrate with TSV connections to the backside for the wide I/O interface, with memory facing the backside of the logic, Kujala says. If theres more than one DRAM bump connected to the logic, then the DRAM also needs TSVs. As ONeill puts it: Networking is the application thats driving Avagos interest in wide I/O. 3D integration makes a wide memory interface spatially possible, while drastically reducing I/O power. Networking chips need multiple, independent memory arrays, each with a wide interface that pushes memory-tologic interface density beyond the capability of sideby-side multichip interconnect technology.
Xilinx recently introduced 3D Silicon intersposers with TSV for wide I/O interface in FPGA products (Courtesy of Xilinx)
programmable gate arrays (FPGAs), their customers use a variety of bus lengths and proprietary wide interfaces to maximize performance. SoC designs comprise millions of gates connected by complex networks of wires in the form of multiple buses, complicated clock distribution networks, and multitudes of control signals. To successfully partition a SoC design across multiple FPGAs requires an abundance of I/Os to implement the nets spanning the gap between FPGAs. And Kauppi Kujala, senior technology manager at Nokia R&D, sums it all up: Wide I/O performance target assumptions include 12.8GB/s, peak bandwidth, 4-channel SDRAM x128 200MHztype interface, 1.2V LVCMOS look-alike, power approximately 500mW (which offers a large power savings compared to LPDDR2), with a maximum DRAM memory die count of 4.
Guillou expects this new interface to make an appearance on high-end platforms first, followed by potential penetration into lower-end market segments later. Wide I/O is based on highly parallelized interface with a relatively low memory frequency of 200MHz. This means that more than 1100 connections are needed to connect the logic die with the memory die, he explains.
Networking is the application thats driving Avagos interest in wide I/O. 3D integration makes a wide memory interface spatially possible, while drastically reducing I/O power, explains Pete ONeill, Avago Technologies
Such a high number of interconnections cant be done through a traditional package, such as package-on-package (PoP), where the ball pitch is in the range of 0.5 or 0.4mm. Dies need to be Dorsey and Rahman say that Xilinxs customers, encompassing aerospace and defense, communications, medical, test and measurement, high-performance computing, and ASIC prototyping
Whats driving wide I/O?

The key driver behind wide I/O right now is that the mobile phone industry is embracing it as a solution to combine processors with memories, especially for high-end smartphones and connected devices. Smartphone marketshare has soared from less than 5% a few years ago to nearly 30% today. And devices such as tablets, e-readers, or netbooks are also appearing and bringing along demanding needs for high bandwidth data without major power penalties. The web experience is being redefined with the mobile phone, and HD is moving from our home environment and becoming mobile. As a consequence, the computing power of new application processor engines (APE) and multicore CPUs is growing and the latest solutions are being defined to run well above 1GHz, Guillou says. Similarly, the multimedia performance of these APE will need to deliver features such as HD 1080p encode/decode with 60fps or even higher, dual density, 3D graphics, etc. To deliver this performance, the wide I/O interface is one technology of interest.
Nokias next generation mobile phones and tablet systems will need wide I/O interface based 3DICs with TSV interconnects for high bandwidth, low power consumption (Courtesy of Nokia)
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(emulation), who want to implement their nextgeneration applications with FPGAs, are likely to benefit from the earlier availability of the most resource-rich FPGA devicesincluding applications with wide I/O interfacing requirements.
Challenges for commercialization?

There are a variety of interesting viewpoints about what the biggest commercialization challenges for wide I/O will be. Brighton sees three big challenges for the commercialization of the wide I/O interface. First: the availability and maturity of process technology; this is just starting to come together. Two: Cost. A wide I/O interface requires added performance, but the consumers willingness to pay for it is limited. Whatever we do must be cost effective. Three: Standardization. Today there is no wide I/O standard, but momentum is really growing, he says. And while interposers make sense in some applications, the cost of the additional piece of silicon needs to be taken into consideration. ONeill says the biggest commercialization challenge is interesting DRAM makers in offering a wide interface, high data rate, low latency chip suitable for networking, especially one divided into multiple arrays, given the size of the networking market compared to mobile devices and PCs. What we really want to see is a wide I/O memory wafer that can be configured in both interconnect and physical size to match a variety of ASICs, he adds. ONeill expects the second-largest challenge will be the supply chain. Nowak sees cost as the biggest hurdle, especially for cost-sensitive, high-volume mobile applications. He says he wont be surprised if interposers are used for applications such as servers, FPGAs, and tablets where size isnt an issue, but believes theyre unlikely to be used in smaller form factor mobile devices such as smartphones due to size and cost constraints.
Logic + Memory Integration Scenarios (Courtesy of QualComm, IMEC & Javelin)
Guillou believes the main challenge of wide I/O is its intrinsic novelty that can be considered disruptive and the fact that it impacts many different areas. Obviously, a mature, reliable, fully characterized TSV and assembly technology at an affordable cost process is required, he says. However, its not all about process technology. Complexity comes from the consequences wide I/O interface has, for instance, on logic die floorplans, 3D design flow, testability, memory hierarchy, business model, and supply chain. In the end, to be successful, wide I/O needs to be technically and commercially viable for all players involved along the supply chain.
already isnt free. Adding an additional interposer, which should contain TSV and microbumps as well, wont help make this technology more affordable or the final stack thinner. The silicon interposer isnt the option ST-Ericsson is considering. There are also many technical challenges related to the wide I/O bump interface, Kujala points out, such as how to connect more than 1200 bumps between the dies. The die must have very good coplanarity to be able to connect the other die with bump and interface into that, he says. If we will have more DRAM dies, are the memory dies coming separate or as a pre-assembled memory cube?
In the end, to be successful, wide I/O needs to be
technically and commercially viable for all players involved along the supply chain, explains Yann Guillou, ST-Ericsson
Kujala doesnt see a major benefit from a silicon interposer between logic and DRAM. The other solution would be side-by-side logic and DRAM on top of a silicon interposer, but thats not for mobile phone applications due to the large size. Nokias target is to go for wide I/O without an additional silicon interposer, he explains. And from an OSAT perspective, the biggest challenges are thin wafer handling and tight pitch assembly for the middle-end and back-end assembly process, says Cheung. Another challenge, he adds, is the known good die test methodology.
A wide I/O JEDEC standard defines bump positioning and assignment of signals to have all memory providers delivering the same ball out. As a result, the silicon interposer that matches the memory with the logic die becomes optional, Guillou says. The mobile industry has to deal with tough cost, footprint, and thickness constraints. The wide I/O interface
Standardization?
Standardization will play a critical role in 3DIC integration and is currently being discussed by many industry organizations. Industry collaboration has already begun. There are a variety of standardization and consortia groups working on TSV, so theres a lot of momentum in this area, Brighton says. In addition to overt standardization efforts, TI expects to see significant convergence of ideas as the technology matures, but this effect of natural selection will take some time to develop.
Mobile & Portable Devices are Placing Stringent Demands for DRAM bandwidth (Courtesy of Rambus, Yole Developpement)
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Standards body JEDEC is among those leading important standardization activities for wide I/O, and companies such as OEMS, memory providers, chipset suppliers, and test, packaging, and IP houses are also deeply involved in the process, notes Guillou. Nokia is among those participating in JEDECs wide I/O standardization work, and Kujala says that their preference is to follow JEDECs lead. Based on the standard, there will be an offering by IC suppliers, he explains. For the whole 3DIC technology development, having a standard is a positive step, and Nokia sees this activity as one of the first common targets for the entire industry. Xilinx is also working with industry groups including Imec, Sematech, and SEMI to help promote and support standardization in this area, according to Dorsey and Rahman. Avago firmly believes standardization is essential, ONeill says, although its not yet clear whos leading since several standards organizations (JEDEC, GSA, SEMI, IEEE) have recently become involved in 3D integration work and each is addressing different aspects. At a recent JEDEC meeting, Avago proposed creating a task group to develop a standard for a configurable, stackable, high data rate, low latency DRAM. The JEDEC 42.2 committee assigned this item 1787.01 and is organizing the task group. Cheung and Nowak indicate that theyre seeing many companies from the semiconductor industry participate in the wide I/O standardization committee efforts. Bottom line: The industry is clearly collaborating and targeting wide I/O standards. Its only a question of timing now.
companies, especially since using a temporary carrier to ensure rigidity of the thin wafer stacks would be necessary. If carriers are used, some agreements should be redefined between foundries and packaging housesespecially regarding the bonding/debonding process. This is a key step in the process that also needs standardization. From Brightons perspective, chip suppliers and OSATs must collaborate more closely to meet customers requirements. As an industry, we have challenges about the compatibility of processes and materials used by different foundries and OSATs, he says. Another challenge Cheung sees is timing. How quickly and effectively the industry can come up with cost-effective assembly equipment and an
assembly process. If this isnt achieved, cost may be a potential showstopper, he cautions.
While there will be supply chain challenges, well be working on them, says Kujala. Mobile products are extremely performance hungry and performance is the driver behind wide I/O. There is already consensus in the industry that wide I/O is needed. To fulfill that needed performance, the industry will make it happen.
Sally Cole Johnson for Yole Dveloppement
Calvin Cheung is vice president of engineering for Application and Design at Advanced Semiconductor Engineering (ASE) Inc. Before joining ASE, Cheung spent many years at AMD, in a variety of engineering and management roles. Later, he was the manager of product development engineering where he was responsible for building and managing the chipset development engineering group. Prior to working with the chipset group, he held a number of positions within other product groups at AMD, gaining vast experience in various silicon development functions from design to manufacturing. Patrick Dorsey, senior director of product management at Xilinx, responsible for the overall product line management, development, and marketing for FPGAs, CPLDs, and EasyPath solutions. Dorsey has been involved in technology marketing and solutions development for more than 18 years. He holds a B.S. in computer engineering and a Masters in business administration from the University of Michigan (Go Blue!). Yann Guillou leads 3D and advanced packaging in the CTO and Strategic Planning Office at STEricsson. Guillou began his career at CEA-LETI and then worked at STMicroelectronics and ST-NXP. He holds a MSc. in materials and nanotechnology from the National Institute of Applied Sciences, and a Masters in Management of Technology and Innovation from Grenoble Business School, France. Kauppi Kujala is the senior technology manager at Nokia R&D. Kujala has worked at Nokia since 1999. Prior to that, he was a project engineer at VTI Technology. He holds a M.Sc. in materials science from Helsinki University of Technology.
Matt Nowak is Qualcomms senior director of engineering in the VLSI Technology Group of their CDMA Division. His responsibilities include leadership of the Advanced Semiconductor and Packaging Technology Initiatives such as throughsilicon stacking, advanced memory technology, design for 3D, spintronics, and More than Moore initiatives. He manages a combination of internal advanced development teams, supplier JDPs, and consortia and university projects. He holds BS and Masters degrees in electrical engineering from Cornell University, has more than 30 years of semiconductor experience, and is a Senior Member of IEEE. Pete ONeill is investigating the application of 3D integration to Avago Technologies ASIC Products Divisions networking and computing products. His primary responsibilities concern test strategy and reliability screening. In 32 years in the IC units of Avago, Agilent Technologies, and HewlettPackard, ONeill has also worked in the areas of CMOS processing, SPICE modeling, reliability, and test equipment. Arif Rahman is a principal engineer and technology architect at Xilinx Inc., where he has incubated R&D programs, leading to successful technology transfer for commercialization. With more than 10 years experience in digital, mixed-signal, and sensor design, development, and supply chain evaluation, he has worked in all aspects of 3D ICs. He holds a Ph.D. in electrical engineering from Massachusetts Institute of Technology and an MBA from Santa Clara University. Jeff Brighton is a TI Fellow and manages the CMOS 3DIC technology development program for Texas Instruments. During more than 25 years at TI, Brighton has been a key technical leader in process development and volume ramp for more than 10 generations of CMOS technology. He helped pioneer TIs flexible, internal and external manufacturing model for advanced CMOS technology and also directed TIs 45nm and 28nm low power CMOS development programs prior to his role with TIs 3DIC program. He graduated from the University of Illinois at Urbana Champaign with a MS degree in electrical engineering.
Ahead: Supply chain issues?

The supply chain is a key part of the wide I/O approach, and there are issues worth noting. Nearly everyone involved in 3D integration cites the supply chain as their major practical concern, points out ONeill. Its not at all clear how the established players will divide the new functions and whether new players will fill in the gaps, he says. The supply chain is particularly difficult for fabless companies that need suppliers for new operations such as TSV formation and die-to-wafer bonding that neither the foundries nor OSATS currently provide. A good example in terms of whos responsible for what: Guillou expects via middle TSV is the technology option the industry is most likely to select, with the TSV process run in foundries between FEOL and BEOL. TSV will be embedded within a regular thickness CMOS wafer, he explains. To make the TSV emerge and connect the logic die with the memory, the logic wafer will need to be thinned to a few 10s of microns. Depending on what point in the chain the foundry stops and the assembly begins, very thin wafers or stacks will be manipulated and exchanged between foundries and assembly houses. These aspects are an area of concern for
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C o M P a N Y v i s i o N
2- and 3-dimensional design alternatives for System- and IC Designers
eda2 asic
For the last 40 years we were able to double transistor counts of ICs every ~ 2 years and managed to follow Moores Law by shrinking feature sizes successfully. With every new process generation we achieved higher speed, lower power and even lower cost per function --- until recently.
hile process experts are confident to continue on the shrink-path for a few more generations, the challenging design requirements and costly manufacturing equipment triggered the search for alternatives to shrinking of 2-dimensional SoCs. The first viable 3-dimensional alternatives started to gain market share about five years ago. PoP (Package-on-Package) and SiP (System-inPackage) demonstrated space and/or power savings, compared to implementing the same functions in multiple 2-dimensional SoCs. To gain more from utilizing the 3rd dimension, leading edge companies focused on thinning wafers to less than 50 microns and started to interconnect bare dice with TSVs (Through Silicon Vias). This 3D/TSV stacks were even faster, smaller and consumed less power than SiP solutions. As leading edge wafer foundries and OSATs (OutSourced Assembly and Test houses) engaged in the development of the necessary manufacturing flows and encouraged their equipment vendors to meet the demanding new requirements, it became clear that 3D/TSV technology offered many compelling benefits but still required development efforts to become cost-effective in volume production. Also, to fully utilize the 3D/TSV benefits, the individual dice need to be designed
3D-ready with the TSVs and their drivers and receivers included in the layout, instead of the much larger I/O buffers and bonding pads. Facing these 3D challenges, creative engineers developed a less demanding interposer-based alternative and called it 2D, indicating its place between 2D SoCs and 3D stacked dice. A key advantage of the 2D technology is that it can utilize flip-chip dice, mounted side by side on an interposer or face-to-face with an interposer in between. To give an overview of all these technologies, their benefits and trade-off, Table 1 below shows in six columns major implementation alternatives ICor system designers can choose from and applies five technical criteria and two business criteria to compare these technologies.
If implemented in separate ICs, every one of these functions can benefit from cost-effective, dedicated process technologies. This benefit also applies to all four More than Moore alternatives and is essential to produce highly integrated solutions cost-effectively. Applying this fifth technical criteria to one large SoC, the most common alternative today, shows that significant technical challenges arise. Despite very flexible and capable process technologies and design tools, the implementation of logic and memory and/or analog, is not as easy as dedicated processes can enable and often forces relaxing of specifications. First business criteria (Time to Profit): It gets increasingly difficult and time consuming to integrate all functions needed into one large SoC and manufacture the design cost-effectively in a universal process technology. Design iterations and yield enhancement efforts can further delay the product introduction, increase time to profit and reduce profit margins. Distributing the functions into multiple ICs allows more reuse, reduces the application-specific development efforts and helps to get to market and profit faster. However, many applications need higher performance or dont allow the power budget or space required for multiple SoCs. The second business criteria (NRE and Risk) is closely related with the first. As a consequence of increasing design complexity, the hardware development cost for one large SoC is increasing. So is the risk of functional failures at the first tape-out and additional mask cost as well as yield variations in production. The multiple SoCs alternative reduces the risk of failures and yield variations, but multiple SoCs may not meet the technical application criteria and the tooling cost for them can add up to a significant amount.
The two More Moore alternatives on the left

The first four technical criteria (speed, power, form factors) are self-explanatory. The fifth criteria Heterogeneous Technology Mix refers to designs comprised of significant amounts of logic, large memories and/or analog / RF components, MEMS, sensors, etc.
The two proven More than Moore alternatives in the center

The five technical criteria show that PoP and SiP alternatives cant compete with the one large SoC alternative in regards to speed and power dissipation, but have a clear advantage if the
IC- and System-Implementation Alternatives (Courtesy of eda2asic)
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The business criteria show that both emerging technologies are rapidly maturing and will complement their technical benefits with compelling value propositions. As mentioned at the beginning of this article, to fully benefits from the 3D/TSV advantages, the dice need to be thinned and have a 3D-ready layout with TSVs, but have the large I/O buffers and bonding pads removed to reduce area, silicon cost and power dissipation.
www.eda2asic.info
Herb Reiter, president of eda2asic Consulting, Inc., is an industry veteran with 20 years of semiconductor experience and 14 years of providing high-productivity EDA tools, IP blocks, design services and the support of industry organizations to semiconductor vendors. Herb founded eda2asic in 2002 and focuses since 2008 on chairing the GSAs EDA Interest Group and the 3D Working Group to accelerate and broaden market acceptance of 3D/TSV technology. Herb can be reached at herb@eda2asic.com.
2 D Alternatives - Interposer/Substrate in RED (Courtesy of Paul D. Franzon, NCSU)
design requires a mix of logic, memory and/or analog functions. While PoP and most likely also SiP quickly exceed the allowed package height, they are equal or better than multiple SoCs in regards to the other technical criteria. Both PoP and SiP have proven their benefits in regards to the two business criteria.
The two emerging More than Moore alternatives on the right

The technical criteria show the significant benefits of 3D/TSV technology and where the interposerbased 2D alternative is equal to a large SoC and better than multiple SoCs.
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Stud bumping serves as TSV alternative for BSI image sensor in latest iPhone 4
Chipworks Inc. recently opened the 5MPixel camera module from latest iPhone 4 of Apple. Yole and Chipworks had the chance to redact a join article analysing the possible reasons for the choice of stud bumping technology on ceramic carrier for the final packaging of Omnivision BSI image sensor.
n the February 2010 Yole 3D Packaging newsletter we discussed the advantages of Xintec WL-CSP used by OmniVision/TSMCs first back illuminated (BSI) image sensor. We were excited by the iPhone 4 announcement in June which included mention of a 5 Mp, 1.75 m pixel pitch BSI camera module. Early speculation of an OmniVision design win proved to be true and one surprising find from the reverse engineering analysis is yet another approach to BSI CIS package integration. The 5 Mp iPhone 4 camera module, which integrates an LED flash assembly, was assembled by LG Innotek. The module dimensions are 9.2 mm x 9.2 mm x 6.2 mm thick (excluding the LED flash). The large form factor is a clue that CSP is not used for this device.
Apple iPhone 4 Rear Camera BSI Image Sensor (Courtesy of Chipworks)
to the chip carrier lands, while a die under fill material encapsulates the die periphery. This type of packaging for a CIS application has typically only been seen in some front-illuminated DSLR camera sensors. Tilt and cross-section SEM views show details of the bonding region on the die. The final steps of the wafer process flow included opening windows in the dielectric stack over the bond pads. In this case, the
bond pad metal is the back of the aluminum metal 2 die interconnect. TSMC would have then shipped the wafers to the packaging house for dicing and formation of the gold ball bonds and gold studs. While OmniVision/TSMC do have a TSV process for BSI parts, the back bonding scheme has provided what is likely a higher yielding alternative that satisfied Apples specification. Additionallly, this approach enables the flexibility to also simply wire
Apple iPhone 4 Rear Camera Module (Courtesy of Chipworks)
The lens barrel is affixed to a ceramic chip carrier likely fabricated by Kyocera. Surface mount capacitors, a flip-chip mounted autofocus ASIC die, and a glass window are mounted to the front of the chip carrier, while a BSI image sensor die is seated in a cavity in the back. A die photograph of the back, or light-receiving, surface appears similar to a typical front-illuminated sensor. Instead, in this implementation the ultra-thin BSI silicon substrate has been etched at the die edge allowing access to the back of the bond pads. A side view X-ray and schematic diagram show the ceramic chip carrier and BSI die configuration. Gold studs are used to connect the die bond pads
Apple iPhone 4 Rear Camera Die and Package X-Ray, Schematic (Courtesy of Chipworks)
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bond directly to the pads as we saw in the new 4th generation iPod Touch 0.7 Mp BSI camera module. In summary, with a little ingenuity CIS foundries and IDMs need not take on the cost and complexities of a TSV process for all applications. Contrasting the investment required for TSV integration in a 300 mm wafer process, these devices show what is possible using 200 mm wafer fabs and a depreciated wire bonding toolset. Given the low number of I/Os and large pad pitch, BSI CIS represents a sweet spot for gold stud bumping. www.chipworks.com www.yole.fr
Apple iPhone 4 Rear Camera Die Bond Pad Region (Courtesy of Chipworks)
Jrme Baron leads Yoles MEMS and Advanced Packaging market research. He has been involved in the technology analysis of the 3D packaging market evolution at device, equipment, and material supplier levels. Baron earned a MSc. Degree in Micro and Nanotechnologies from the National Institute of Applied Sciences in Lyon, France.
Ray Fontaine has been a process analyst at Chipworks since 2001, specializing in image sensors. He has authored and technically reviewed numerous image sensor process review (IPR) reports.
CMOS Image Sensors

technologies & Markets - 2010 Report
Disruptive technologies pave the way to the future of digital imaging industry!
MaRKEt tREnDs the reason why we are now releasing the first report on cMos image sensor industry is that we feel that we are at an historic turning point of this young, but still maturing industry. says Jrme Baron, technology & Market analyst, MEMs & advanced Packaging. KEY FEatuREs the objectives of this first report are to provide: Market data on CMOS image sensor key market metrics & dynamics: cMos image sensor unit shipments, revenues and wafer production by application, market shares with detailed breakdown for each player Key technical insight about future technology trends & challenges: from BsI and other front-end technologies evolution to WLc realization with wafer level optics, packaging / assembly & test A deep understanding of CIS value chain, infrastructure & players contact us For more information, feel free to contact David Jourdan: tel: +33 472 83 01 90, Email: jourdan@yole.fr
Y O L E D V E L O P P E M E N T
CMOS Image Sensors Technology Drivers: New Challenges to face !
BSI (Backside illumination) New color filters, AR coatings Pixel isolation, substrate techno
HDR (Hide Dynamic Range) eDoF (Extended Depth of Focus) NIR (Near IR Capability)
Front-end Packaging / Assembly

WLP (Wafer Level packaging) 3D TSV interconnects Wafer Level Camera & Molding
Software / Design Optical module

WLO (Wafer Level Optics) Image stabilization (MEMS Inertial) Auto-focus (Piezo, liquid lense, MEMS)
YOLE DVELOPPEMENT
Y O L E
D V E L O P P E M E N T
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Interview with Dr. William Chen of ASE

From page 1 Yole Dveloppement: So you joined ASE in 2000. What are your job responsibilities in the ASE organization? Bill Chen: As ASE Fellow and Senior Technical Advisor, I have a broad portfolio of technology strategy, customer involvement, product promotion, and industry networking. I work with a small group of senior experienced industry veterans. As a part of the ASE global sales and marketing organization, we have the opportunity to engage with the senior technical leaders in the global customer community while at the same time, have strong linkages deep into the manufacturing engineering and R&D organizations in the ASE family. YD: There are so many exciting things going on in Advanced Packaging today its hard to know where to begin. Certainly ASE has been deeply involved with scaling up the Infineon eWLB fan out technology can you share with us whats been involved and where that stands? BC: ASE has been serving customers in WLCSP for over ten years. eWLB (fanout WLP) is the natural extension of our WLP service offerings to customers. ASE was the first OSAT to collaborate with Infineon on eWLB , taking the technology successfully into high volume manufacturing production in April 2009. We put together a dedicated team to work with the Infineon team for volume manufacturing implementation. There has been much learning on both sides. The yields have been steadily climbing above 97% and the goal of 99% is now well within reach. The initial production has been focusing on single die fanout packages. Engineering development is ongoing with multiple customers focusing on the future generations of Fan out products, including 2D Multi-die and 3D Double sided fan out packaging, incorporating additional features such as Integrated Passive components. YD: Amkor and TI have recently announced their advances in Cu Pillar technology. Can you share with us where this technology stands at ASE and what we can expect in the future ? What applications are requesting ? or are suited for this technology ? BC: As you well know, Intel has been in production with Cu Pillar for their microprocessor flip chip package for some years. Cu Pillar technology brings significant advancement over traditional solder bump technologies in flip chip packaging. It provides a lead free solution, improved electromigration performance, cost reduction of the laminate substrates, and as a controlled stress environment for ULK dies. As a leader in advanced packaging innovation, ASE has been developing
(Courtesy of ASE Group)
an excellent set of packaging solutions in this area for our customers that include PC and mobile processor device makers. ASE has been working on Cu pillar technology for several years and is working closely with a number of customers. The highest level of interest is in the area of mobile application processors , which drive integration and small package size. These applications need fine pitch i.e. slim pillars to shrink the pitch while allowing escape traces between the pillars. The later facilitates lower cost substrate technologies in FC CSP and thereby an overall cost effective package. YD: Looking at ASE integrated passives technology, how has customer acceptance been on this technology? Can you tell us where the focus has been application wise? BC: ASE is working with customers producing IPDs for integration into module package assemblies. IPDs are very well suited for the high levels of integration and miniaturization required for the next generation of advanced modules. The most common application is the integration of various filters into RF applications. The incorporation of IPDs into Interposers, 3D packages, and Fanout packages is an important aspect of the ASEs technology portfolio. YD: ASE has been a leader in bringing copper WB into the mainstream. Any issues with bringing up this technology? Any issues with customer acceptance? Can you tell us what % of your business you expect to switch over to copper WB? BC: You have hit the nail right on the head: technical challenges and customer acceptance. Changing from Au wire to Cu wire involves a whole set of changes in materials, equipment, and manufacturing processes. It took a lot of hard work and commitment from the top management to process
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engineers, and manufacturing operators to make the Cu wirebond qualification and implementation seamless for customers. ASE actively worked on fine pitch Cu wire bond technology for a number of years before starting high volume production in September of 2008. With gold price escalating, there is real cost benefit for the customers across a broad spectrum of products. Many technical and manufacturing challenges were addressed one by one. This is indeed is a major step forward for the industry. We are proud that we have won over many customers by providing them with solid reliability data and manufacturing track record. ASE will exit 2010 having shipped approximately 2 billion units, with approximately 30% of our wirebond output allocated to copper. We expect the conversion rate to exceed 70% within the next 2-3 years, and expect Au to be only a niche (<10%) after 2015. YD: Certainly many of our readers are following the emergence of 3D / TSV technology very closely. How would you describe overall 3D status at ASE? What issues have been resolved and what issues are still to be solved? BC: 3DIC / TSV offers significant advantages for many customer applications in the market place, from wireless to PC and server applications. ASE is collaborating closely with key customers and foundry partners to enable the full middle and backend process elements of 3D / TSV technologies. While basic process technology feasibility has been demonstrated, there is still much work to do. Areas include material handling of thin wafers that require dual side patterning, warpage control, testing including ultrafine pitch probe, and overall cost of manufacturing. Standards are needed for physical connection of the various IC elements in 3D structures. Co-design tools must be ready. For TSV enabled integrated packages, test will be a major challenge for the industry. YD: ASE has been a strong proponent of interposers for the initial stages of full 3D IC stacking. Can you tell us something about your interposer program and when we can expect to see something in production? We are hearing that single chip interposers for the 32 and 22 node will be an important interposer application space is this correct? When can we expect interposers applied to 3D stacks? BC: Silicon interposer is a viable, if not critical, enabler for addressing the CPI issue with CTE mismatch between ELK silicon die and organic substrate. We agree with you that 32 and 22 nm node will be an important application space. It will also be an important package solution for 3D heterogeneous integration. We are working with our foundry partners and our key customers on a number of interposer package development programs. For example, the interposer could include a 3D memory stack in the architecture design. In our view, production ramp will be sometime in late 2012 or early 2013. YD: What can you say about your standard 3D process? Cu metal?, oxide liner?, Cu/Sn bonding? underfill?, expected initial pitch ? Anything
that makes the ASE approach different or more reliable than your competitors?
BC: We are working with multiple partners on various Middle process approaches for the assembly of die with TSVs into their final package assemblies. ASE has developed a TSV formation process, middle end, and final package Dr Bill Chen, assembly capability for 200mm wafers. Fellow and Senior Technical Advisor, ASE 300mm wafer capability is on schedule for next year. ASE has developed both copper solid fill and copper lining plating with polymer isolation for the TSV processing for both via middle YD: When it comes to D2W bonding what is and via last. The polymer isolation provides better the thinnest chip you can currently handle? electrical performance and lower stress distribution What can you tell us about handling these than some alternative barrier and isolation techniques. thin die? Underfill materials and underfill application process BC: We have good success with D2W bonding with are also crucial parts of assembly for microbump 50m thick die using thermocompression bonding interconnection of silicon dies with TSV. and NCF underfill. Engineering development has YD: Many are assuming that the OSATS will demonstrated success with alternative approaches be responsible for bond, test and package. of die to substrate and die to memory stack However, another option would be for the assembly for 3D stacked packages. For handling OSATS to receive the wafers with TSV directly chips at this thickness, sawing tape, ejection from the foundries and then be responsible for system & bonding tool design in TC bond, and die everything else including thinning, backside flatness are keys for successful yields processing, bond, test and package. Has this YD: Without telling us who, can you share division of labor been determined between ASE anything about customer pull for 3D with and the foundries. If you had to guess how you interposers and full 3D stacks? expect this to play out? BC: We have talked to many customers. The BC: We have many customers working with different strongest interests are in mobile processor and PC foundries. We expect both business models to applications. And the motivations are market driven be in play. The issues of test, product liability as you may expect. boundaries, as well as competitive supply chain concerns will have an effect on each companys YD: What unresolved issues does ASE see in decision regarding which model to employ. the infrastructure? YD: Are any of the required 3D unit operations qualified yet at ASE? Can you share with us which ones? When do you expect your full 300 mm line to be in place? BC: Works on various standards is slowly taking shape. Particularly important for us are those at the interface connections.
BC: We have test vehicles designed with our partners that have been generated for process evaluations in our R&D environment. Technology feasibility demonstrations and stress tests are on schedule for middle end and back end assembly processes. ASE will expand our capabilities for wafer level processing and assembly within 2011, aligning our schedule to meet our customer development timeline requirements. At this time we do not have products qualified.
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YD: Is ASE confident that testing protocols will be in time for initial product production? BC: Typically, the IC houses are responsible for test protocols. In this case, we will have SiP with processor and memory, with which we have good experience and knowledge. While test will be an important challenge, we are confident that working closely and early with our customers, and developing the test hardware and test protocols together in the whole development process we will be ready for production. YD: Qualcomm has publically stated that anything over a 15% premium for 3D IC could be a deal breaker. Does ASE see this as being possible? What will it take to achieve these cost goals? BC: The total cost of the solution must be evaluated for each application. We are sure that Qualcomm has done a good study of the market and the front end and back end processes to come up with this 15% premium for their own set of applications. The front end 3DIC die with TSV formation and backside processing steps will add to the throughput. The backend will have additional processing steps due to TSV expose and ultra fine pitch assembly. Both front and back end have thin wafer handling added to their processing. We believe the 3DIC - TSV technology will be commercialized. The ability of
ASE Silicon interposer prototype (Courtesy of ASE Group)
our technical community to collaborate on common manufacturable standards will certainly impact the final cost of the 3D structures to the market. YD: Many of the recent roadmaps from foundries such as TSMC and UMC and assembly houses like ASE, SPIL, Amkor, STATS ChipPAC appear to agree that we will see interposers in the 2010-2011 timeframe and full 3D IC stacking in the late 2011 2012 timeframe. As of today is ASE standing by these predictions? Do you see these roadmaps as aggressive or realistic? BC: In ASE we design our roadmaps to be aggressively realistic. We are already actively engaging with key customers in both 3D IC and silicon interposer. We position our roadmap forecast to be in line with our readiness for customer engagement. Production schedules are determined by customers and their end user customers and highly influenced by the market. YD: Any other topics that our readers might be interested in?
BC: You have touched on most of the high profile topics in our industry. While 3DIC/TSV is the highest profile technology in many peoples minds, let us not forget that electronics are ubiquitous, IC is not all CMOS, and innovation is needed everywhere. A prime example is ASEs initiative on Cu wirebonding. We are working with customers on MEMS, and on heterogeneous integration with different SiPs and modules. We are working on thin, low cost substrates. At the other end of the semiconductor spectrum are the low pin count ICs and discretes. A couple of years ago, ASE entered the business to serve the low pin count IC and discrete customers in Weihai, China, and now we are well established in this area. We believe in technology and business model innovations to serve customers large and small across the globe. YD: Thanks so much for fielding these questions. BC: Thank you for bringing this discussion to your many readers. Phil Garrou Sr Analyst
Make plans to attend today ...
3-D Architectures for Semiconductor Integration and Packaging

Keys to Design, Manufacturing, and Markets 810 December 2010
Hyatt Regency San Francisco Airport Hotel
This conference provides a unique perspective of the technobusiness aspects of the emerging commercial opportunity offered by 3-D integration and packagingcombining technology with business, research developments with practical insightsto offer industry leaders the information needed to plan and move forward with confidence.
Burlingame, California
For more information visit: http://techventure.rti.org
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REGISTER FOR LIVE WEBCAST TODAY Enabling next generation motion solutions for consumer electronics
Join our webcast to examine the challenges faced by system integrators to develop products with advanced motion features. We will discuss the MotionIC platform, now available to help developers meet market demands without having to deal with the complexities of sensor combination and motion processing.
To learn more and to register, please go to www.i-micronews.com/webcast or click here.
Register Today
to Explore the MotionIC platform

When: Wednesday, December 15 8:00 AM PST Speakers:
Bruno Flament, CTO, Movea Tim Kelliher, Customer Solutions Architect, Movea Jean-Christophe Eloy, CEO, Yole Dveloppement
Sponsored by
Hosted by
C o M P a N Y v(Courtesy of VTI) CMA3000 i s i o N
The MEMS pioneer VTI relies on its proprietary 3D MEMS technology

VTI Technologies can be considered as a pioneer in MEMS for the past 20 years.
he company is a leading supplier of acceleration, inclination and angular motion sensor solutions for transportation, medical, instrument and consumer electronics applications. VTI develops and produces silicon-based capacitive sensors using its proprietary 3D MEMS (Micro Electro-Mechanical System) technology. In 2009 VTI was the first MEMS company to adopt Wafer Level Packaging in the worlds smallest and least power consuming three-axis acceleration sensor, the CMA3000, and the company has already announced that it will launch new MEMS solutions at Electronica 2010. Mr Anssi Korhonen, VTI Chief Technology Officer, was interviewed for the MEMS Trend Magazine.
Yole Dveloppement: VTI is one of the very few MEMS companies using a Through-Glass Vias technology for its 3-axis accelerometer. Why using glass wafers instead of Si? Anssi Korhonen : We are actually using a silicon wafer and molten glass material for isolation of TSVs. Benefits of the VTI cap wafer technology include good insulation and very low parasitic (stray) capacitance. Glass, on the other hand, provides planar surface and reliable bonding interface to the structural wafer. Also, glass is very inexpensive starting material, Mr. Korhonen explains. YD: There are different ways to do TGV. What makes the VTI technology specific? AK: The process is VTI proprietary technology. We avoid using plating processes in forming the vias. It is compatible for wafer level processing although needs some specific equipment. Currently we are satisfied with the via resistance in the tens of ohms range. YD: Is VTI Technologies planning to use its TGV AK: The technology in its initial form (planar isolation and one via) has been in use since 1984. In the late 90s due to requirements by multi-axis accelerometers and gyros we added the capability for a multitude of vias. More recently this technology has been developing for finer pad pitch and size by
utilizing dry etching of silicon instead of mechanical machining. The process is scalable for larger wafer sizes. It is used for all VTI MEMS designs. YD: VTI has recently achieved the smallest accelerometer on the market (2x2 mm). Do you plan to go even smaller? AK: Smallest size components can be achieved with the Wafer Level Packaging (WLP) technology, which is close to WLCSP technology that has received wide acceptance in the market. VTI WLP goes one step further by flip chip attaching ASIC on the MEMS sensing element. Further size reduction is possible and restricted to specific MEMS or ASIC design requirements, not so much on packaging technology, Mr. Antti Korhonen concludes. www.vti.fi
Mr. Anssi Korhonen, M.Sc. in electrical engineering, has worked as Chief Technology Officer for VTI Technologies since 2008. He has worked for electronics manufacturing services industry since 15 years.
CMA3000 (Courtesy of VTI)
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SET makes strides to enable 3D Integration with high precision Chip-to-Chip and Chip-to-Wafer bonding
SET collaborates with CEA-LETI, STMicroelectronics, ALES and the CEMES-CNRS on advanced chipto-wafer technologies (direct metallic bonding) for 3D integration: history & content . Direct copper-to-copper bonding requires a good planarity and excellent surface quality especially in terms of both particulate and metallic contamination. The low roughness of the copper pillars and pad as well as the topology between the copper and oxide areas are critical to obtain good bond at low force and room temperature. The process is developed by CEA-LETI. ALES is supporting some specific developments for the surface preparation. The CEMES-CNRS characterises the bond quality especially concerning the copper structure evolution upon annealing. STMicroelectronics is driving the application of this technology for the high density 3D integration. SET has developed a clean FC300 enabling Dieto-Wafer direct bonding at high yield. The machine operates at room temperature. Special care has been taken for cabling in order to reduce drastically the particle generation. The clean environment inside the machine housing protects the wafer surface while it is fully populated with dice. What are the advantages of this technology compares to conventional thermo-compression bonding? SET is very much interested by this direct metal-tometal bonding which enables fast placement for 3DIC. It is performed at low force and room temperature which is advantageous for high density interconnect applications requiring high accuracy placement as we do avoid temperature expansion problem. To ensure void-free bonding, the die placement must be carried out in a particle-free environment. JEMSIP-3D: project based on the development of a High speed bonder required for the high volume production of 3D devices using the TSV technology. SET has entered the JEMSiP-3D project to develop a high accuracy, high speed die bonder for the production of devices using 3D technology with high density TSV. The goal is to introduce a die-to-wafer bonder with submicron placement accuracy with stacking capability compatible with face-to-face or face-to-back alignment. A 2-Step approach with individual placement followed by a global bonding sequence is favoured. prevents oxygen intrusion while preserving the alignment of the device with respect to its substrate. Consequently, it ensures an excellent wetting and a higher quality of solder joints at reduced bonding forces and temperatures as well as higher yield as no cleaning step is required. With the confinement chamber, the process gas is injected through horizontal nozzles aimed at the device being bonded. An exhaust ring removes the process gas from the micro-chamber and sends it into the gas exhaust line, keeping the gas out of the machine and the clean room. A nitrogen curtain is formed around the exhaust, ensuring that ambient air is not entrained into the micro-chamber by the Venturi effect, while a deflector attached to the bond head creates the confined micro-chamber. The wafer acts as the deflector for D2W configuration when the chamber is attached to the bond head. Yole Dveloppement understands that SET mainly works on accurate placement. What is SETs market positioning with respect to placement accuracy? What are the trades-offs being made to achieve such levels of accuracy? For over 30 years, SET has been involved in high accuracy applications such as the hybridization of infrared focal plane arrays and the assembly of optoelectronics components required for high bandwidth telecommunication. Both applications require placement within a micron or better. Optoelectronics typically involves components ranging from a few hundred microns in size to a few millimetres, whereas the infrared focal plane arrays can be as large as 100 millimetres. 3D integration with high-density TSVs requires submicron [or
Semi-open confinement substrate for the FC150
Semi-open confinement chamber for oxide removal: principle & advantages. Cu-based systems have become a major focus as an interconnect material for 3D integration. Cu surfaces are bonded together using either die-todie (D2D), die-to-wafer (D2W), or wafer-to-wafer (W2W) bonding. The oxides present at the Cu surfaces compromise results of thermocompression bonding. To achieve high-quality and reliable bonding, a controlled environment preventing oxide formation during the bonding sequence is required; it is also necessary to remove the oxide that might be present before bonding. Mechanical scrubbing cannot be used when submicron accuracy is needed; therefore SET has developed the semiopen confinement chamber to enable chemical oxide removal without jeopardizing the final placement accuracy. The chamber can be used with forming gas, but efficiency of the oxide reduction is significantly increased by using formic acid vapour. The semi-open confinement chamber includes a substrate chuck and a bond head with a non-contact localized confinement which operates safely with reducing gases such as forming gas or formic acid vapour. To preserve the standard capabilities of SETs bonding tools and especially the low contact force measurement applied to the components, the Semi-Open Confinement Chamber has no hardware sealing. A non-contact virtual seal of the micro-chamber enables gas confinement for chipto-chip or chip-to-wafer bonding under controlled atmosphere. This ensures gas collection and
Inside view of the FC300 with direct metallic bonding configuration
FC300 submicron high force die bonder
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many bonding schemes are being investigated around the world for 3D devices, a clear winner has not yet emerged and so process flexibility is still a critical feature. Commercialization of 3D integration is expected to begin perhaps as early as 2012, with higher volume applications ramping up after that. Several tool designs to meet these market needs are on the drawing boards at SET, always with an eye to meeting the process and throughput requirements of emerging market segments. As noted earlier in
Cross section of three chips stack
highly accurate] bonding, consistent with the accuracy historically required by the IR FPA devices. The primary difference between these two markets is the need for much higher throughput; production of IR FPAs may be limited to a few tens of devices/ day due to extremely long bonding times, while consumer applications of 3D IC may require several thousand bonds/hour. These high throughputs are available on some production bonders, but not at the accuracy or process conditions required by most 3D bonding schemes. SET offers a tool for submicron bonding on 300mm wafers, but with a throughput of only a few hundred units/hour. SET will continue to deliver a high accuracy tool for 3D development and lower volume applications, concurrent to developing a tool with throughputs to meet high volume consumer applications. While
this article, a 2-step approach with individual die placement followed by global bonding captures the best features of D2W and W2W bonding schemes; this method is being characterized to identify best practices for pre-attachment. While submicron alignment and positioning of stages and bonding arms will continue to occupy a significant portion of the machine overhead, bonding materials and processes which reduce the temperature and force requirements will likely play a key role in increasing the throughput for 3D applications. For this reason, molecular bonding, performed at modest temperatures and forces, is of great interest. Similarly, polymer bonding is under investigation at IMEC, where SET is partnering with the institute to develop 3D processes using accurate die placement followed by collective bonding in a wafer bonder.
Populated wafer Courtesy of IMEC
www.set-sas.fr
3D Glass & Silicon Interposers

Myth, niche or high volume necessity?
MARKET TRENDS
These players, in search of growth opportunities, have positioned as service providers for the back-end operations for the making of through silicon vias (TSVs) and other related wafer-level assembly operations, explains Jean-Marc Yannou, Project Manager at Yole Dveloppement.Thanks to 3D glass / silicon interposers, they can go one step further, and actually propose products combined with their service offer.
KEY FEatuREs
Detailed account of all the application fields of 3D interposers Drivers and expected benefits by application Comparison with technology alternatives and likeliness of 3D interposer penetration by application Market trends and figures Analysis of target cost structure for a few key applications Supply chain analysis for the commercialization of 3D interposers
YOLE DVELOPPEMENT
Y O L E
contact us For more information, feel free to contact David Jourdan: tel: +33 472 83 01 90, Email: jourdan@yole.fr
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Reverse Costing : Analysis of Infineons eWLB
System Plus Consulting presents in exclusivity some extracts from their recent analysis of the Fan-Out Wafer Level BGA package from Infineon.
Package is adapted to the desired pitch, independently of die size, lowering the constraints on the PCB. eWLB technology has been developed by Infineon, and licensed to ASE, STATS ChipPAC and Nanium. These last 2 companies are the first to propose this technology using 300mm wafers. This package is produced since 2009 and is used in baseband SoCs: the Infineon X-GOLD 113 or 116 (GSM baseband) and 213 (EDGE baseband) were among the first components to use this packaging technology.
he eWLB (enhanced Wafer Level BGA) is the first Fan-Out BGA package available on the market.
Chip placement (pick and place equipment) Wafer molding (epoxy) De-bonding of carrier wafer Redistribution layer: First dielectric coating and development Copper deposition and pattern Second dielectric coating and development Ball drop, reflow and singulation: Thin tin layer deposition Ball dropping and reflow Final test Dicing
Large octagonal aluminum pads are used to connect with the vias of the redistribution metal layer. This is to prevent from misalignment due to die shift issue during curing.
The CMOS process is standard up to passivation.
eWLB packaging technology has several advantages over alternative approaches like fan-in WLCSP or flipchip BGA: A smaller footprint and a lower thickness than BGA A better reliability than small pitch fan-in CSP Lower thermal resistance Possibility to have multiple dies in the same package (SiP) No substrate, so a simplified supply chain
Inside Technology
As can be seen from the X-ray picture, the die (darker area) is not centered in the package. The area ratio is around 2.5 for this 209 balls, 8x8 mm package with a 0.5mm pitch.
Packaging process
The technology is based on a carrier on which the dies are individually placed to form a reconstituted wafer. The wafer is then molded and the carrier removed. One or 2 distribution layers are deposited before bumping and singulation. Wafer reconstitution and wafer molding: Lamination of adhesive film onto steel carrier wafer
47%
Cost analysis
The cost analysis performed on this package showed that in 2010 the manufacturing cost is slightly higher than equivalent flip-chip BGA.
3% Depreciation Cost 28% Manufacturing Cost Labor Cost 22% Yield Losses
In this first generation of eWLP, only one redistribution layer is used to route the die pads to the package balls.
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But there are several cost gains factors: Improvement of packaging yield, a critical parameter for expensive SoC dies Removing of the temporary bonding step used to reduce the risk or warping Amortization of the specific equipments required by this process Manufacturing on 300mm wafers Simulations done with these scenarios provide very competitive results. With eWLB packaging technology in high volume production, the manufacturers are preparing the next generation: Integration of passive components Multi-metal layer redistribution Side by side dies Reduced thickness 3D packaging with two-side redistribution and TMV is also being developed but the future yield of this approach is still difficult to estimate. The amounts invested by Nanium and STATS ChipPAC in production lines and R&D for eWLB prove that this technology is already a serious alternative, with applications extending outside mobile phones to many consumer products.
SOLUTIONS FOR
MEMS
PROCESSES
Lithography, spray coating, top/bottom alignment Nano imprint lithography and hot embossing
Michel Allain, System Plus Consulting
Recent Reverse Costing Reports Semisouth SiC JFET - Physical Analysis of the Device - Step by Step Reconstruction of the Process Flow - Cost of Manufacturing & Estimation of Selling Price Discera 8002 MEMS Oscillator AKM AK8973S 3-Axis Compass LEDs from Cree, Nichia, Lumileds, Acriche
System Plus Consulting develops Costing Tools and performs on demand Reverse Costing studies of Semiconductors (from Integrated Circuits to Power Devices, from Single Chip Packages to MEMS and MultiChip Modules) & of Electronic Boards and Systems. Please contact System Plus Consulting: www.systemplus.fr
3D integration and wafer level packaging
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Freescale Semiconductor answers Yole Dveloppement questions about RCP technology status
Yole Dveloppement had the pleasure to interview Navjot Chhabra, Redistributed Chip Packaging R&D and Operations Manager, Packaging Solutions Development, Freescale Semiconductor.
Yole Dveloppement: Could you introduce our readers about your recent announcement with NEPES on 300mm RCP agreement? Could you comment on the choice of NEPES as a key strategic partner? Navjot Chhabra: Freescale Semiconductor began work on the RCP technology in 2003. In Q3 2006 Freescale made a decision to commercialize the technology based on the maturity of its research and development activity. Up to that point, most of the R&D work was being done on an eight inch format and was based on financial and capacity models as market analysis. It was determined that a larger format would be required to allow this technology to be competitive, especially for consumer packages and eventually multi-die systems. Ideally, a square/ rectangle format with panel sizes greater than 400- 500mm would be ideal, however Freescale decided to move initially to a 300mm round format to minimize tooling cost and customization. We felt it was important to develop a fully automated tool set with similar fab like technologies with an assembly cost structure and yield expectations. Freescale picked Nepes for a number of reasons. They continue to be very aggressive in serving a growing market. They bring to the table complementary technology and capability with a common goal of providing customers with new and enabling technology. Nepes has been providing 200mm Flip chip bumping services since 2000 in Korea and providing 300mm Flip chip bumping services in Singapore since 2005. Nepes was looking to extend their product offerings in the wafer level packaging area with its high volume bumping production for 65nm/45nm devices (both leadfree and eutectic), WLCSP and the recent 50um pitch micro bump. With well matched capabilities and a 300mm toolset, this turned out to be a winwin collaboration for both Freescale and Nepes to commercialize the RCP technology and enable us to penetrate both existing and new markets. YD: Do you plan to license RCP to additional companies in the month to come? NC: We are not planning any additional announcements related to licensing of RCP in the next few months. We are very focused on getting RCP fully transferred and qualified at Nepes. Over the longer term, we absolutely desire to see RCP proliferate in the industry. YD: What are the key motivations and applications driving the commercialization of Fan-out Wafer-level-packages? NC: We see a broad set of requirements for the RCP Fan-out wafer level packaging technology. Interest is coming from multiple customers and industries. Having a 300mm platform can drive very low costs in both small and large body sizes, with multiple layers of redistribution allowing for a broad range of integration schemes. For those customers migrating to consumer based, flip-chip packages, the RCP solution provides a compelling alternative. A significant number of companies are evaluating 2D systems integrating between two to four die along with a number of surface mounted devices (SMDs). Where space constraints are critical, a number of customers are designing and evaluating 3D RCP packages. What is exciting about this technology is the level of flexibility it provides the customer and ability to provide specific solutions. Significant performance, size and flexibility is gained with the ability to integrate sensors and other heterogeneous ICs. In most cases customers see this technology as a way to differentiate themselves from their competition. YD: Infineon seems to experience a lot of success in licensing its eWLB packaging technology: could you explain what is the main difference between eWLB and RCP from a manufacturing stand-point? Is it an issue to have multiple Fan-out Wafer-level-packaging technologies co-existing on the worldwide packaging IP landscape? NC: The technologies are very similar in that the customer will see a pin for pin compatible package. The differences come in the features the technology offers. In the table provided is list of attributes and requirements customers are looking for with respect to this technology. Clearly the entry point is to
Reliability, Configuration, Components
Cellular Products
Wireless pplications
Consumer electronics
Networking
In Chassie Automotive
In Dash Automotive
Aerospace & Defense
Robotics
Medical
Consumer level certification Industrial level certification Automotive level certification Medical level certification Single Die FO-WLP 2D Multi-die FO-WLP < 6x6mm Package size (as small as 2x2mm) 6x6mm 13x13mm Package size > 13x13mm Package size (up to 40x40mm) FO-WLP PoP Stacked 3D Multi-die FO-WLP 3D Integrated FO-WLP 3D IC with 3D FO-WLP integrated system MEMS / Sensor Integration SMDs (Capacitors, Inductors, Oscillators, etc) Memory (DDR, NVM, MRAM) 3D FO-WLP Photonic Module Radar High Power / Thermal Management Redistribution Layers Volumetric space sensitive
X X
X X X X
X X X
X X
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 to 4 X 1 to 4 X 2 to 4 X 2 to 6 X 2 to 4 2 to 4 X X X X X X X X X X X X X X X X X X X X 2 to 6 2 to 6 2 to 4 X X X X X X X X X X X X X X X X X X X X X X X X X X X
Requirements and features by industry and application for Redistributed Chip Packaging technology (RCP) (Courtesy of Freescale)
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support a single die Fan-out package however this is only the beginning. To enable a game changing solution for customers, we need to be able to provide very flexible building blocks off the same fanout platform. The question will be how robust the platform is to support these needs. YD: What are the challenges to face for next generation FO WLP based on multi-die, doubleside RDL, 3D vias and, eventually, based on Panels? NC: Freescale has made good progress in developing and qualifying various RCP building blocks and platforms to allow a diverse range of configurations and applications to be realized. Overcoming the challenges of processing on 300mm with multiple layers of routing has put us in a good position to develop a diverse range of integration schemes. We are continuing to work with multiple customers to find new ways to exploit this technology. Listed below are some of the challenges we have to solve. From a RCP technology perspective, we have qualified to commercial and industrial levels. Getting to multi-die systems (2D) require anywhere from two to six RDL layers, which can also be done in RCP without assembly, die drift, yield and warping issues. Multi-die packages have new requirements
but mostly in developing the infrastructure to support this capability. Effort and activities are underway in developing these solutions. Infrastructure development challenges: - Supply chain and die management - System architecture - 2D and 3D IC system design and electrical modeling - 2D and 3D package design and modeling - Inline and end of line component and system testing - Thermal management - Yield management - Failure analysis For 3D systems the biggest challenges will be reliability, system design and addressing yield and testability challenges. With respect to the process technology, it does require a different level of sophistication to build these reliable structures but not insurmountable. Lastly, Freescale made the decision early to migrate development and pilot production to a 300mm format to resolve any issues we may see moving from our 200mm platform. As expected, we did see significant challenges that we had not experienced at 200mm. A large number of those showed up
in reliability and appear on larger packages with increased layers of redistribution. Fortunately, we were able to resolve these by passing reliability with good margin and capability. www.freescale.com
Navjot Chhabra is currently heading Research and Development as well as the operations for Redistributed Chip Packaging technology within Packaging Solutions Development at Freescale Semiconductor. Navjot has held several positions within Freescale /Motorola including Strategy, Director of Interconnect at International SEMATECH and key positions in Manufacturing. Prior to Motorola, Navjot spent several years with Micron Technology working in process development, process and device integration as well as manufacturing. Navjot has been involved in the introduction of several generations of Memory devices as well as the initial migrating to Cu interconnects and adoption of ultra low k dielectrics. Navjot holds several patents in the area of process development and design.
Infineon IFX-213 eWLB Package

The first reverse engineering analysis report of a Fan-Out Wafer Level Package !
The Infineon eWLB is a Wafer Level Package with a Fan-Out in order to increase the bump number and pitch. The IFX-213 in eWLB package is directly assembled on a PCB, with a 0.5mm pitch. One redistribution layer is used for this package. KEY FEATURES
CONSULTING CONSULTING
Physical Analysis Methodology
This report provides a complete teardown including: Detailed photos Material analysis Schematic assembly description Manufacturing Process Flow In-depth economical analysis Manufacturing cost breakdown Selling price estimation
YOLE DVELOPPEMENT
Y O L E
conTAcT US For more information, feel free to contact David Jourdan, Tel: +33 472 83 01 90, Email: jourdan@yole.fr
Analysis performed by
Distributed by
CONSULTING
Y O L E
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The Market Leader in eWLB Technology

First in high volume
eWLB manufacturing with best-in-class yields eWLB reconstituted wafer manufacturing of next-generation eWLB
First to offer 300mm
eWLB is a fan-out wafer level packaging technology that offers a small, thin, high performance semiconductor solution for mobile phones and consumer devices. STATS ChipPAC is leading the industry in eWLB manufacturing and innovative next-generation technology such as:
multiple die side-by-side super thin eWLB two metal-layer
Pioneering the development
redistribution larger body size and higher I/O count 3D/PoP versions
To learn more about eWLB visit: www.statschippac.com/eWLB
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Amkor talks 3D trends, looks to the future

Amkor Technology, headquartered in Chandler, Arizona, is among the worlds largest providers of contract semiconductor assembly and test services.
Yole Dveloppement: Are any new trends emerging in 3D packaging? Terry Davis: Were seeing several trends emerging. For starters, interconnect density is increasing. This means a smaller bond pad pitch, stacked die that require more interconnects in the same package footprint, and the adoption of mixed interconnect types, wirebond and flip chip, in the same package. Reducing package thickness is another big trend right now. This is being done with thinner wafers and die, heightening the importance of thinning methods for creating space for wirebonds such as spacer films, as well as thin core substrates. Another trend is shrinking footprint size while maintaining or increasing I/O count. Were seeing finer external ball pitch, with 0.4mm gaining wider adoption and 0.3mm in development. Theres also a push to increase the number of I/O rows. Were also seeing custom external ball patterns being used to optimize escape routing on applications boards. YD: Is an example of these custom external ball patterns the A4 used in Apples iPad? TD: Yes, a good example is the A4 processor used in the iPad. YD: What are the biggest challenges that remain for 3D packaging? Any not-so-obvious ones? TD: Package warpage is still a key concern, with the drive to a thinner package height. This requires thinned wafer/die, a thin mold cap, and a thin substrate core. The electrical and thermal performance of the system are more heavily influenced by package performance as more functionality is transferred to fewer packages by making use of 3D-type package structures. Before you can solve a problem, you need to first understand it, and Amkor has extensive electrical, thermal, and mechanical modeling and testing capabilities. Historically, multi-die packages have used die from the same sources such as memory stacks. As 3D packaging expands, we can expect die from multiple sources to be packaged together. Well see various die designed for optimum connection within a single package. This will be even more critical for TSV and designs where two die are connected by flip chip. YD: How is demand for 3D packages compared to more traditional packages? TD: Handheld applications like smartphones and tablets are driving higher levels of integration. YD: Any comments on the A4 processor in some handheld tablets? TD: The A4 processor is the bottom package in a package-on-package (PoP) configuration, with the top package housing two memory die. The benefits include reduced footprint, improved communication between application processor and memory, and the ability to package and test the application processor separately from the memory to reduce yield stack-up. Again, using handheld tablets as an example, the flash memory is in 64GB LGA packages, where four die are stacked in each package. Memory-type devices have been the early adopters of 3D-type packaging. YD: How is Amkor differentiating itself with 3D? TD: Amkor recognized the drive toward 3D-type packaging early on, and our TMV (through-mold via) PoP, Stacked CSP, and FlipStack CSP (Figure 1) are clearly aimed at 3D packaging requirements. We also recently announced our fine pitch copper
Copper pillar bumps (Courtesy of Amkor)
pillar flip chip technology platform (Figure 2), which will enable fine-pitch 3D interconnects well into the future. Amkor has relationships with leading foundries, which enables us to collaborate on reliability studies with advanced silicon nodes to ensure silicon/packaging interactions are addressed for applications like 3D packaging, where fragile, low-k dielectrics create challenges due to the thin, highdensity structures and interconnect technologies. YD: What role will industry collaboration play in the future of 3D packaging? TD: Collaboration is a key element in both translating requirements and reducing time to market. For example, we worked with Nokia and ST to qualify our TMV PoP package. All parties benefited from this collaboration, which resulted in reduced time to market and increased sales, thanks to a short qualification time. We also recently collaborated with TI on our finepitch copper pillar flip chipshrinking bump pitch up to 300% compared to current solder bump flip chip technology. YD: Whats next for 3D packaging? Any trends we should watch for during the next 5 years? TD: Amkor expects to see increased stacked die counts for memory applications. In waferlevel packages, we also expect to see various configurations of stacked die and stacked package with TMV as an enabling technology. Were also expecting more hybrid packages, in the form of wafer-level packages stacked with laminate packages. And as far as TSVs, its still a question of whether itll be via first, middle, or last. www.amkor.com
Terry W. Davis, Amkor Technologys senior director of technical marketing Davis currently serves as Amkors senior director of technical marketing, and previously developed and managed their MicroLeadFrame package family.
(Courtesy of Amkor)
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a N a l Y s t C o r N e r
Packaging power semiconductors the next big thing?

As demand for power semiconductors heats up, Yole analyst Jean-Marc Yannou provides a backgrounder on their evolution and packaging requirements.
At the recent IMAPS France chapters power packaging conference, held in Tours on November 18, presenters from application fields ranging from aerospace to military to transportation gathered to discuss the latest trends and solutions. And its worth noting just how surprisingly standardized their solutions seem to be. As of now, there are very few substrate suppliers and no standard supply chain. Original equipment manufacturers (OEMs) package their power semiconductor devices themselves or count on integrated device manufacturers (IDMs) to do it for them. But the outsourced semiconductor assembly and test (OSAT) companies are now taking to the power semiconductor business, seeing a great deal of potential down the road. And even though the supply chain varies greatly from one player to another, especially from one application to another, they are all following the same innovation pace and track and solutions as they emergewhich is quite remarkable. Demand for power semiconductor packaging is increasing and likely to become a very significant business in the future, so its a good time to talk about the evolution of power semiconductors and their packaging requirements. are used for electrical engines and energy conversion, and especially for photovoltaic inverters. The applications for power semiconductors include electric trains and tramways, as well as aerospace and automotive applications, audio amplifiers for consumer applications, photovoltaic inverters, and electrical vehicles or hybrids, etc. Power semiconductors typically fall within the wide range of 5W to hundreds of kW, and silicon is the most common material used in the transistors because its still cheaper than many of the other emerging solutions.
Jean-Marc Yannou, Project Manager, Advanced Packaging, WLP & 3D system Integration, Yole Dveloppement
There are two big issues with power semiconductors. They must carry high current, and the result of high currents and voltages transiting through electronic appliances is the generation of a lot of heat that then must be extracted. High current and temperature are driving all of the innovation in this field.
Most of the emerging technologies work much better at higher temperatures than silicon, up to 250C. Since internal heat generation is a problem, it can be tempting to replace silicon by the compound semiconductors to avoid the need for cooling systems, which are also very expensive.
Packaging power semiconductors

The main issues for packaging power semiconductors are high currents and high temperatures. Measures must be taken to counter these issues, such as specific die attach materials, heat spreaders, insulators, specific interconnects, and cooling gels. The internal transistor temperatures, known as junction temperatures, can rise up to 250C and even reach as high as 300C. The best
The transistors themselves can be made of silicon; a MOSFET. You can make different types of transistors, such as isolated gate bipolar transistors (IGBTs). And for even higher power applications, we find compound semiconductors, with silicon carbide or gallium nitride. These are the semiconductors with larger bandgaps that are being used in emerging technologies for the higher-power range of power applications.
Power semiconductors
First, lets look at power semiconductors. What are they? Essentially power semiconductors involve energy management controlled by on/off transistors. Electronics for this energy management
According to Yole Dveloppement, outsourced semiconductor assembly and test (OSAT) companies are now taking to the power semiconductor business, seeing a great deal of potential down the road
DBC package structure for power semiconductors (Yole Dveloppement - Nov. 2010)
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way to manage the temperature issue of power semiconductors can often be found in packaging materials. When you look at most ICs for consumer applications, theyre being overloaded with epoxy resins. These epoxy resins are limited to operating temperatures of 200C. For higher-power applications, overmoldings are no longer used. Then you need a specific substrate as well, because the standard organic substrates have the same issue: theyre epoxy-based. The most common one is the direct-bond copper (DBC) substrate. It uses a ceramic-based substrate either made of aluminum nitride or silicon nitride, with copper foils on both sides. This ceramic substrate is a good thermal conductor, which helps with heat extraction. Copper is also a good heat extractor. The transistors, silicon MOSFETs, IGBTs, GaN, or SiC, are attached on the overlying copper foil. The whole device is encapsulated and then signals exit the upper face of the device. Substrates Its not at all easy to find companies who provide substrates for power semiconductors. The substrates are quite difficult to produce and there is a lot of secrecy surrounding which companies produce them and for whom. Its rumored that there will only be three providers of the nitride-based substrates worldwide, because it requires knowing how to place copper on the nitride substrates. Thermal dissipation The goal is to dissipate/extract heat off the semiconductor junction, through the semiconductor material to extract it from the package. Silicon isnt as good a thermal dissipater as ceramic, and not even close to copper. So when using silicon wafers, they need to be thinned down to below 100m. Actually, all of the high-powered transistors need to be thinner than 100mand only to combat thermal dissipation issues. Die attach materials ICs need to be attached to the substrates using die attach materials. The material of choice in most semiconductor packaging is usually glue, so for power semiconductor devices in the past thermal conductive glues with a high metal content were used.
The limited number of substrate suppliers for power semiconductors and lack of a supply chain, however, are challenges that need to be overcome, explains Jean-Marc Yannou, Yole Developpement
Since they needed even higher thermal conductivity, the industry continued to load more metal particles into the latest glues to the point where the latest ones are 80% silver; they barely contain glue anymore. The latest step in the evolution of die attach materials is using pure silver. One issue is that it has a high melting point. Thats why recent R&D involves silver powder with some chemical agents to help it be sintered at low temperatures using low temperature sintering technology. The next step will likely be nanoparticles, which are still in the R&D stage. Interconnects For consumer electronics the most common interconnections are wire bonds, although bumping interconnects are becoming common for flip chip devices. Both are used in power applications. The two issues of high current and high temperature are a problem because interconnects must be able to drive enough current density, and the high temperatures are an issue of interconnect reliability. To drive more current density than in the past, instead of using one wire bond per pad, multiple wires are being used, as well as a larger-diameter wire bond. For consumer electronics, the most common wire bonds are made of gold. But there are serious cost issues involved and its difficult to make large-diameter gold wire bonds. Now, aluminum, which can be grown in large diameters, is usually substituted for gold. After the arrays for wire bonding, the industry began using ribbon bonding. It uses the exact same principle as wire bonding and the same equipment. But instead of putting a round-shaped wire they use a rectangular-shaped wire, referred to as a ribbon, which is much larger and capable of driving much higher current density. There are other interconnects being used, such as clip bonding, which is when a MOSFET transistor is sandwiched between its copper foil and another copper foil, with attachment material on both sides of the device. And the reason for so many different technologies for interconnects is that we need to drive high current, but also reduce the excess resistance to the transistors. Copper pillars Copper pillars are an attractive option for power semiconductors, but contrary to how theyre used in flip chips, they would be placed on the topside of the semiconductor device to bring the signal to the top. The downside is used for grounding and heat extraction.
Power module with parallel wide bond interconnections
A driver for using copper pillars is that wire bonds or ribbon bonds create some intermetallic compounds (IMCs), but these are interface alloys between the interconnection itself and the pads on the semiconductor device. There are conductivity and reliability issues with wire bonds, including cracking.
Future of packaging power semiconductors

The future of packaging power semiconductors looks very bright. A lot of industry momentum is starting to ratchet up the pace of evolution of power semiconductor technologies and, as a consequence, packaging for these devices. The limited number of substrate suppliers for power semiconductors and lack of a supply chain, however, are challenges that need to be overcome. However, standardized technical solutions are emerging which will allow at their turn an outsourcing of assembly and packaging services of power semiconductors as they keep on growing.
Sintering for die attach, in production at Semikron (Yole Dveloppement - Nov. 2010)
Ribbon bonding interconnections (Courtesy of ST Microelectronics)
Jean-Marc Yannou joined Yole Developpement as technology and market expert in the fields of advanced packaging and system integration. He has 15-years of experience in the semiconductor industry. He worked for Texas Instruments and Philips (then NXP semiconductors) where he served as Innovation Manager for System-inPackage technologies. He is also the President of IMAPS (International Microelectronics And Packaging Society) in France.
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Embedded Wafer-Level-Packages
Fan-out WLP / Chip Embedding in Substrate
Be ready for the next generation of IC packaging & substrate assembly waves!
MARKET TRENDS
Embedded wafer-level-packaging technology is not new at all. Key benefits of the technology include miniaturization, improvement of electrical and thermal performance, cost reduction and simplification of logistic for OEMs Things are moving really fast at the moment as this year, we see both Fan-Out wafer level packaging and chip embeddeding into PCB laminate package infrastructures emerging at the same time, ramping to high volume production
3DIC with tSV 3-D WLP Flip-Chip
MEMS
Fan-out WLP Package PCB
IPDs
KEY FEatuRES
Both Fan-Out WLP and Chip embedded package technologies analyzed Key market drivers, benefits and challenges application by application Market trends & figures with detailed breakdown by application Description of the complete manufacturing tool-box for embedded wafer level packaging Analysis of several embedded package target prices for a few key applications Supply chain perspectives, key players and emerging infrastructure for embedded packaging
YOLE DVELOPPEMENT
300mm eWLB reconfigured wafer (Courtesy of NANIUM / Infineon).

ContaCt uS
For more information, feel free to contact David Jourdan: tel: +33 472 83 01 90, Email: jourdan@yole.fr
About Yole Dveloppement

Beginning in 1998 with Yole Dveloppement, we have grown to become a group of companies providing market research, technology analysis, strategy consulting, media in addition to finance services. With a solid focus on emerging applications using silicon and/or micro manufacturing Yole Dveloppement group has expanded to include more than 40 associates worldwide covering MEMS and Microfluidics, Advanced Packaging, Compound Semiconductors, Power Electronics, LED, and Photovoltaic. The group supports companies, investors and R&D organizations worldwide to help them understand markets and follow technology trends to develop their business.
SERVICES
Market data, market research and marketing analysis Technology analysis Reverse engineering and reverse costing Strategy consulting Corporate Finance Advisory (M&A and fund raising)
PUBLICATIONS
Collection of market & technology reports Players & market databases Manufacturing cost simulation tools Component reverse engineering & costing analysis More information on www.yole.fr
MEDIA
Critical news, Bi-weekly: Micronews, the magazine In-depth analysis & Quarterly Technology Magazines: MEMS Trends 3D Packaging PV Manufacturing EfficienSi Online disruptive technologies website: www.i-micronews.com Exclusive Webcasts Live event with Market Briefings
CONTACTS
For more information about : Services : Jean-Christophe Eloy (eloy@yole.fr) Publications: David Jourdan (jourdan@yole.fr) Media : Sandrine Leroy (leroy@yole.fr)
Editorial Staff
Managing Editor: Jean-Christophe Eloy - Editor in chief: Dr Eric Mounier Editors: Jrme Baron, Jean-Marc Yannou, Sally Cole Johnson, Dr. Phil Garrou PR & Media Manager: Sandrine Leroy - Assistant: Camille Favre - Production: atelier JBBOX
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M a g a z i n e

What is the impact of Xilinxs 3D silicon interposer announcement?

Interview with Dr. William Chen of ASE

Next up for 3D ICs: Wide I/O

eve Nts a N alYsis C o M Pa N Y v i s i o N s aNalYst CorN e r

Printed on recycled paper

Next up for 3D ICs: Wide I/O

3-D Architectures for Semiconductor Integration and Packaging

December 8 to 10, 2010 - Shangri-La Hotel, Singapore

IC Packaging Technology Expo

N ove MBer 2010

Whats driving wide I/O?

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Challenges for commercialization?

Logic + Memory Integration Scenarios (Courtesy of QualComm, IMEC & Javelin)

In the end, to be successful, wide I/O needs to be

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Sally Cole Johnson for Yole Dveloppement

Ahead: Supply chain issues?

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2- and 3-dimensional design alternatives for System- and IC Designers

The two More Moore alternatives on the left

The two proven More than Moore alternatives in the center

IC- and System-Implementation Alternatives (Courtesy of eda2asic)

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2 D Alternatives - Interposer/Substrate in RED (Courtesy of Paul D. Franzon, NCSU)

The two emerging More than Moore alternatives on the right

Wet Deposition With Superior Quality and Lower Cost

ALCHIMER at SEMICON Japan

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Apple iPhone 4 Rear Camera BSI Image Sensor (Courtesy of Chipworks)

Apple iPhone 4 Rear Camera Module (Courtesy of Chipworks)

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CMOS Image Sensors

CMOS Image Sensors Technology Drivers: New Challenges to face !

Front-end Packaging / Assembly

Software / Design Optical module

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Interview with Dr. William Chen of ASE

(Courtesy of ASE Group)

(Courtesy of ASE Group)

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(Courtesy of ASE Group)

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ASE Silicon interposer prototype (Courtesy of ASE Group)

Make plans to attend today ...

3-D Architectures for Semiconductor Integration and Packaging

For more information visit: http://techventure.rti.org

pub_movea_186X132:Mise s s u e n 1 7 N o v e M B e r 2 0 1 0 i en page 1 25/11/10

To learn more and to register, please go to www.i-micronews.com/webcast or click here.

to Explore the MotionIC platform

C o M P a N Y v(Courtesy of VTI) CMA3000 i s i o N

The MEMS pioneer VTI relies on its proprietary 3D MEMS technology

CMA3000 (Courtesy of VTI)

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Semi-open confinement substrate for the FC150

Inside view of the FC300 with direct metallic bonding configuration

FC300 submicron high force die bonder

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Cross section of three chips stack

Populated wafer Courtesy of IMEC

3D Glass & Silicon Interposers