Code No: RR410505 Set No.

1
IV B.Tech I Semester Regular Examinations, November 2006
VLSI SYSTEMS DESIGN
( Common to Computer Science & Engineering, Computer Science &
Systems Engineering and Electronics & Computer Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. Implement the following gates with CMOS Logic and explain its working

(a) 2 - InputNAND gate.

(b) 3 - Input NOR gate. [8+8]

2. Explain about different computer aided design tools used in designing Integrated
Circuits. [16]

3. Explain details about level-1 modeling of MOS transistor. [16]

4. Design a layout for CMOS 2-input NAND gate. [16]

5. Explain with suitable example how to design the layout of a gate to maximize
performance and minimize area. [16]

6. Discuss clearly about the following system Design principles.

(a) Pipelining
(b) Data-paths [8+8]

7. Explain clearly the global routing phase of the floor planning of the chip with few
examples by considering all constraints. [16]

8. Explain about switch - level simulation and give rules for evaluating switch - level
simulation. [16]

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Code No: RR410505 Set No. 2
IV B.Tech I Semester Regular Examinations, November 2006
VLSI SYSTEMS DESIGN
( Common to Computer Science & Engineering, Computer Science &
Systems Engineering and Electronics & Computer Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. Implement the following gates with CMOS Logic and explain its working

(a) 2 - Input OR gate.

(b) 4 - Input NAND gate. [8+8]

2. An n-MOS transistor is operated in active region with the following parameters.

µn Cox = 95 µ A/V 2 W/L (ratio) = 100 V gs = 4V, Vtn = 1V . Find its drain
current & drain ?Source resistance. [16]

3. Explain with neat sketches CMOS fabrication using P - well process. [16]

4. Design a layout for CMOS 2-input AND gate. [16]

5. Explain the rise time and fall time calculation procedure of the CMOS inverter.
[16]

6. Draw the basic structure of serial-Parallel multiplier and explain its working prin-
ciple. [16]

7. Clearly discuss about power distribution and clock distribution routing procedure.
[16]

8. Clearly explain about event driven simulation with suitable example. [16]

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Code No: RR410505 Set No. 3
IV B.Tech I Semester Regular Examinations, November 2006
VLSI SYSTEMS DESIGN
( Common to Computer Science & Engineering, Computer Science &
Systems Engineering and Electronics & Computer Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. Implement the following gates with CMOS Logic and explain its working

(a) 2 - Input NAND gate.

(b) 3 - Input NOR gate. [8+8]

2. Explain clearly about each step of typical design abstraction ladder for digital
integrated circuits. [16]

3. Design a stick diagram for CMOS logic shown below.

Y = (AB + CD)1 [16]

4. Explain about Pseudo-logic and draw the circuit topology of a three-input NOR
gate designed in Pseudo - NMOS. [16]

5. Explain the details of standard cell layout design method. [16]

6. Discuss clearly about the following system Design principles.

(a) Pipelining
(b) Data-paths [8+8]

7. Explain how power - down modes reduces the power consumption of the design.
[16]

8. Clearly explain about the generic integrated circuit design flow. [16]

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Code No: RR410505 Set No. 4
IV B.Tech I Semester Regular Examinations, November 2006
VLSI SYSTEMS DESIGN
( Common to Computer Science & Engineering, Computer Science &
Systems Engineering and Electronics & Computer Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. Implement the following gates with n-MOS transistors only and explain its working

(a) 2 - Input OR gate.

(b) 4 - Input NAND gate. [8+8]

2. Explain about different computer aided design tools used in designing Integrated
Circuits. [16]

3. Design a stick diagram for CMOS logic shown below.

Y = (AB + CD)1 [16]

4. (a) What do you mean by layout of a component?

(b) Draw neat layout diagram for NMOS transistor [8+8]

5. Give tests for struck-open fault for each transistor in a two-input static NOR gate.
[16]

6. Draw the structure of carry select adder and explain its working principle. [16]

7. Explain about the data - path controller architecture of register transfer machine.
[16]

8. Explain about design methodology for 1BM ASICS. [16]

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