different delays, the design of the system, allowing each E1 signal for the maximum delay of 64ms.

E1 frame structure system design The system stream of the E1 frame structure can refer to the CCITT G.732, G.704 or G.706 recommendations given by PCM-based system of group 30/32 road frame structure, but different. Information on the composition of spaces Transfer the system to the net load (information bit) is N 64Kbps data of the HDLC standard E1 signaling in time slot TS16 and TS1 ~ TS15 and TS17 ~ TS31 total of 31 slots can send a net load. Therefore, N and M satisfy the relation N 31 M. For the most cases, that is, N = 124, M = 4, the net load of 31 time slots occupied. When N <124, and can not fill all 31 slots, then fill in void spaces fixed'1 '. The design of slot TS0 Taking into account the system will be able to achieve all the way to N 64Kbps bit of the HDLC data tap in independent M Road E1 channel transmission, the receiving end in the correct way through the restoration of the combined data, a process requires M Road Road E1 signal complete synchronization , but the actual line between the various different levels of delay, which requires buffering capacity of the system delay. During this period the use of a buffer memory to preserve data. In order to identify a path stored in the SRAM of the CRC Multi-frame and other routes should be kept in the SRAM corresponding Combiner CRC Multi-frame, that is, in order to achieve frame synchronization complex needs of each CRC Multi-frame with a label, that is, Multi-frame to add location codes. In addition, the HDLC data is received by the M-bit sub-way transmission of E1 channel, when M = 2,3,4, then the receiver must be sent in accordance with the order of hours access to M Road E1 channel information bit by bit into HDLC data multiplexer. Therefore, various representatives of E1 need a sub / re-grade the way the order then. In order to take full advantage of E1 channel resources, the use of E1 odd frame header bits after the three back-up to provide users with a synchronous 12Kbps data channels, but also can serve as a low-speed asynchronous data channels, such as 2400,4800,9600 bps used the RS-232 signal. System Design Hardware design System hardware, including an FPGA and an SRAM, FPGA selected Altera Corporation Cyclone series EP1C6. Cyclone series devices are low-cost, medium-density FPGA, there are 5980 logic cells, 20 4Kbit the RAM block and two internal phase-locked loop. Since the system allows each E1 channel can have the greatest delay of 64ms, a Multi-frame period is 2ms, the maximum delay that is complex for the 32 time frame. Multi-frame from a basic frame 16 of the 32-bit Multi-frame number of 32 256 16 = 128Kbit, then the various needs of the largest RAM capacity of 128Kbit. Approach as a result of the largest M = 4, so the system RAM required for the maximum capacity of 4 128Kbit = 512Kbit. 80Kbit and only EP1C6 of internal RAM, so I chose to use the method of external RAM, the system's Inbond selected W24L01, its capacity for 1024Kbit. The realization of system functions through the VHDL Top-down system of the eda design flow using VHDL language programming system. Send some of the major by the PLL module, splitter modules, module framing, CRC checksum module and serial scrambler module. In master clock mode, from the local oscillator frequency generated by the rational points N 64KHz clock and 2.048MHz clock, N 64KHz clock HDLC data as the source of the clock generator, N 64Kbps after the first series of HDLC / and conversion, and write to M in a buffer, and then read out the clock 2.048MHz, E1 and inserted into the corresponding slot in the frame to form the M Road E1 signal, and by CRC-4 checksum, and finally after a serial scrambler , sent. From the clock mode, N 64KHz clock HDLC provided by, 2.048MHz clock by the PLL module from the N 64Kbps to extract the HDLC. Clock Mode Selection and M, N values can be adopted in the FPGA internal configuration VHDL programming language. Include phase-locked receiver module, detection module header, Descrambling code modules, as well as read and write RAM module combiner module. In the receiving part of phase-locked loop through the first input E1 signal lock out of the synchronous clock 2.048MHz and N 64KHz clock 2.048MHz clock signal on the E1 header detection to find the header, the system entered a state of frame synchronization , and then descrambling code, CRC countercheck, as well as the extraction of other control information and data. Descrambling code data after the string / and

converted output FPGA, kept in the RAM chip. Control information received, FPGA read from the RAM data, and N 64KHz clock under control and / string conversion, to header, the final synthesis of the N 64Kbps all the way HDLC output signal.

Figure 1 Simulation waveforms Simulation and test The entire system and each sub-module is a functional simulation and post-simulation. Functional simulation platform for the ModelSim + 5.5f, integrated platform for FPGA Express 3.5, after the simulation platform for the Altera Quartus3.0. HP54645D logic analyzer with the measured waveform as shown in Figure 1 (from M = 4, N = 104). Conclusion VHDL by FPGA programming to achieve the rate of N 64Kbps (N = 1 ~ 124) of the HDLC data to the M-bit demultiplexer Road (M = 1 ~ 4) E1 channel transmission, and make full use of E1-qi TS0 frame slot to provide users with simultaneous 12Kbps data transmission channel, and allows each E1 are Delay 64ms. In this paper, the design of E1 to the HDLC controller can also transmit other agreements as a converter bridge the transition. For example, can be 10Base-T Ethernet signals to pass through the Ethernet HDLC protocol controller (such as the ADMtek chip ADM6993 produced), and then transferred through the HDLC controller E1 transmission, thereby achieving the functions of Ethernet over TDM.

Abstract: To transmit and receive data over any network successfully, a protocol is required to manage the flow. High-level Data Link Control (HDLC) protocol is defined in Layer 2 of OSI model and is one of the most commonly used layer 2 protocols. HDLC supports both full-duplex and halfduplex data transfer. In addition, it offers error control and flow control. Using a modified MT8952B controller design, the current research presents a new method for implementing an ultra high bit rate HDLC Controller that is compatible with ST-BUS format using Xilinx Virtex FPGA as the target technology using VHDL for implementation. The HDLC Transceiver is used to transmit and receive the HDLC frames. Implementing the HDLC protocol transceiver in FPGA offers the flexibility, upgradeability and customization benefits of programmable logic and also reduces the total cost of every project which involves HDLC protocol controllers. Key words: HDLC, FPGA, VHDL, CRC-CCITT INTRODUCTION HDLC is one of the most important data link control protocols which is widely used. It is the basis for many other important data link control protocols, such as LAPB, LAPD and PPP, which use the same or similar formats and the same mechanisms employed in HDLC (William Stallings, 2007). Some key applications of this protocol include frame relay switches, error correction in modems, packet data switches and data link controllers (Amit Dhir, 2000). Fast hardware implementation of new concepts and innovative thoughts in order to check their validity and possible advantage is possible by using modern field programmable gates such as the digital FPGAs and the analog FPAAs. Examples include reliability improvement, application of Genetic Algorithms in design of unmanned aerial vehicles, linear feedback shift register based stream ciphers, and multiple reference frames compensation in the H264 coder. Peiravi (2009) presented integration of discrete parts using modern VLSI gates such as FPAAs and FPGAs to improve the reliability of the analog computer of a gyroscopic naval navigation system. Allaire et al. (2009) presented a parallel FPGA implementation of a Genetic Algorithm solution of the re-planning requirements of path-planning in unmanned aerial vehicles to achieve real-time applicability and claimed to have attained an excellent autonomous path planner. Deepthi et al. (2009) presented the FPGA implementation of nonlinear combination generators and clock-controlled generators which are two very commonly used schemes in linear feedback shift register (LFSR) based stream ciphers. Hachicha et al. (2009) presented both DSP and FPGA implementations for multiple reference frames compensation in the H264 coder to improve the coding efficiency for sequences which contain uncovered backgrounds, repetitive motions and highly textured areas using a technique based on Markov Random Fields Algorithm relying on robust moving pixel segmentation. They claimed to process 50 frames (128 128)/s on the EP1S10 FPGA paltform and 35 frames (128 128)/s on the ADSP BF533. Many researchers have attempted to improve existing designs of various types of data processors using

FPGA implementation. For example, Gheorghiu et al. (2008) presented an FPGA implementation of a frequency domain equalizer design. Meng et al. (2009) proposed the use of FPGAs and an adaptive data prefetching scheme to avoid reconfigurable processing coprocessor stalls due to data unavailability through profiling methodologies and quantitative analysis for processing biological data and show a 42% improvement.