P-channel MOSFET:

Threshold voltage Vt is negative

Circuit Symbol for P-channel MOSFET:

a) Circuit symbol for the p-channel enhancement-type MOSFET

(b) Modified symbol with an arrowhead on the source lead.

(c) Simplified circuit symbol for the case where the source is connected to the body.

(d) (d) PMOS symbol used in digital circuits.

vGS<Vt vDS>vGS-Vt vDSvGS-Vt

(induced channel) (linear or triode region) (saturation)

If vDS>vGS-Vt (triode region ):

W i D = p C ox ( L

1 2 ) ( vGS Vt ) v DS v DS (1) 2
rDS = v DS 1 = iD ' W k p ( ) ( vGS Vt ) L

If |vDS| is sufficiently small, we obtain iD-VDS characteristic near origin:

W i D = k ( )( vGS Vt ) v DS L
' p

Where, rDS is linear resistance. If vDSvGS-Vt (Saturation region )from equation (1)
W ( vGS Vt ) 2 i D = p C ox ( ) ( 2) L 2

On verge of saturation: replace VGS-Vt=VDS in either region equation (as shown by dashed line)
2 W v DS i D = p C ox ( ) L 2

Complimentary MOS or CMOS:

Large-signal equivalent-circuit model of an n-channel and pchannel MOSFET operating in the saturation region:

Table 4.1

Aim
Design an amplifier of gain 30 v/v Choose the device Set DC bias Choose a circuit topology Design Analyse Re-design

Where to bias?
Max gain-------MAX IDRD------------MAX ID Min distortion ID= f (VGS)------SATURATION REGION Max current, ID captures variations of VGS faithfully ID= F (VGS, VDS)-----------LINEAR REGION Min current, ID varies with VGS , VDS ---(extra variation)

Transfer characteristics

V DD = 10V , Vt = 1V V DS = 4V , let R D = 18 K ID = V DD V DS 10 4 = = 0 .333 mA RD 18 K

VGSQ = Vt + VoV = 1 + 0 .816 = 1 .816 V

Output characteristicload line

v O = v DS = V DD R D i D where , i D = f ( v I )

VDD 1 iD = vDS RD RD 1 (equationof load line with slope = ) RD

Example 4.8.

vGS1=1.891-1.816=0.075V=75mV vGS2=1.816-1.741=0.075V=75mV

Example 4.8.

At vGS=1.891V , iD=0.397mA At vGS=1.816V , iD=0.333mA At vGS=1.741V , iD=0.275mA

iD1=0.397-0.333 =0.064mA iD2=0.333-0.275 =0.058mA This Shows nonlinearity.

At vGS=1.891V , Vo=2.85V At vGS=1.816V , Vo=4V At vGS=1.741V , Vo=5.05V Vo1=4-2.85=1.15V Vo2=5.05-4=1.05V This shows non- linearity.

Operation as a Switch: When vI<Vt (vO=VDD, transistor operates in cut-off region) When vI=VDD ( vO0, transistor operates in linear region) Operation as a Linear Amplifier: Q is appropriate bias point located close to middle of curve It is also called quiescent point Q (VIQ,VOQ) By keeping vi sufficiently small to restrict operation to an almost linear segment of transfer curve. Voltage gain of amplifier at Q is: (CS amplifier is inverting due to negative slope)

dv O AV = dv I

v I = V IQ

Selecting an appropriate location for bias point Q:

Bias point Q1, too close to VDD: (RD too small) does not leave sufficient room for positive signal swing at the drain occurs when vgs decreases further can amplify only positive input cycles. output signal will be distorted Bias point Q2 is too close to the boundary of the triode region: (RD too Large) might not allow for sufficient negative signal swing occurs when vgs increased further can amplify only negative input cycles