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1.50 "GAC" shall mean gases, acids and chemicals. 1.

51 "G&A Expenses" shall mean standard general and administrative expenses, as calculated by FoundryCo in accordance with accounting standards as generally applied by FoundryCo. 1.52 "GPU Minimum Percentage" shall have the meaning set forth in Section 2.1(c)(ii). 1.53 "GPU Product" shall mean an integrated or discrete graphics processing unit. As an example, as of the Effective Date, GPU Products consist of integrated or discrete graphics processing unit for use in any of the following or similar products: desktop computers, notebook computers, servers, workstations or game consoles. 1.54 "Interim Relief Proceeding" shall have the meaning set forth in Section 15.11(c). 1.55 "Lead Time" shall mean the time between the date an order is accepted by a FoundryCo Sales Entity and the date the Wafers are made available for shipment by the FoundryCo Sales Entity. 1.56 "Major Change" shall mean a change to a manufacturing process that would affect the form, fit, or function of a Product of AMD or that otherwise materially affects a manufacturing process for AMD. 1.57 "Minimum Batch Size" shall mean the minimum total number of Wafers in a Process Batch for a particular Product. 1.58 "MPU Products" shall mean any of the following: (i) the x86, x86- 64, and IA (Intel Architecture)- 64 families of microprocessors, (ii) any existing or new microprocessors based on the x86, x86- 64, and IA- 64 family architecture, or any new instruction set for a processor described in clause (i) first introduced by AMD, (iii) any microprocessors based on new architecture or an architecture adopted in the future, or (iv) Fusion Products. As used in this definition, a microprocessor shall include a component that can execute computer programs and is the central processing unit controlling an electronic device. 1.59 "Other Future Products" shall mean any future integrated circuit devices designed by AMD other than GPU Products and MPU Products. 1.60 "Partnership Committee" shall have the meaning set forth in Section 3.2(a). 1.61 "Period" shall mean a fiscal month or fiscal quarter, as applicable to the specific measurement period in question. 1.62 "Process Batch" shall mean a group of wafers that are processed together as a group. 1.63 "Process Development Wafers" or "Process Engineering Wafers" shall mean Engineering Wafers produced by a FoundryCo Manufacturing Entity to enable it to design, develop, establish, test, improve and validate FoundryCo Manufacturing Entity manufacturing processes. For avoidance of doubt, Process Development Wafers or Process Engineering Wafers shall not include Engineering Wafers expressly requested by AMD, which shall be counted as Product Development Wafers. 1.64 "Process Node" shall mean a specific geometry loosely based on minimum line width at which semiconductor integrated circuit devices, and the photomasks or reticles used in the manufacture of those devices, are manufactured (e.g., a 45 nm process node). For avoidance of doubt, Process Nodes shall include half nodes (e.g., 40nm and 28nm process nodes).
[****] = Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b- 2 of the Securities Exchange Act of 1934, as amended. Confidential treatment has been granted with respect to the omitted portions.