Duo-Binary Circular Turbo Decoder

Based on Border Metric Encoding

for WiMAX
Ji-Hoon Kim and In-Cheol Park

Division of Electrical Engineering

KAIST
 Introduction to Turbo Codes

• Introduced in 1993
– Error Correcting Performance within 0.5dB of Shannon limit
– Wid l Used
Widely U d in
i W-CDMA,
W CDMA CDMA2000,
CDMA2000 and d WiMAX
– Non-Uniform Interleaver
– Iterative Decoding

RSC
SISO
Encoder 1
Decoder 1

Interleaver Interleaver
RSC
SISO
Encoder 2
Decoder 2
2
 Turbo Codes for WiMAX

• Double-Binary Turbo Codes • Circular Coding

– Better Convergence – a.k.a Tail-Biting
– Larger Minimum Distances – No Tail Bits
– Reduced Latency – Avoid Spectrum Waste

< CTC Encoder for WiMAX > < 4-State Trellis for Circular Coding >

3
 Max log MAP for Double-Binary
Max-log-MAP Double Binary
Z (Source Bits)
11/00/01/10 7 7

01/10/11/00 6 6

11/00/01/10 5 5

01/10/11/00 4 4

10/01/00/11 3 3

00/11/10/01 2 2

10/01/00/11 1 1 with Minimum Overhead

00/11/10/01 0 0
 Sliding Window
For Non-Binary Turbo Decoder
• Border Metric with the values Small Window Size,
of previous Iteration Large Frame Size
Æ Huge
g Border Memory! y
– Avoid complex dummy calculation

Complex
Dummy Metric Calculation Efficient for
@ Border Circular Coding
 Proposed Border Metric Encoding

• Allow only a few values for the Border Metric

Flooring the Original Value

to the Closest Power-of-Two Number

Encoding Scheme Encoded Values

±256, ±128, ±64, ±32, ±16, ±8, ±4, 0

4-bit Encoding
(15 values) 6
 BER Performance Comparison

• Almost No Performance Degradation!

7
 Proposed Dedicated Interleaver

• Accumulator-Based Interleaver
– Small Area due to Simple Hardware

8
 Key to Low-Power
Low Power Consumption

• Small-Sized Border Memory

– By Border Metric Encoding
• Infrequent
I f t Access
A t B
to Border
d M Memory
– Only one load/store for processing one Window

9
 Implementation Results
• Time-Multiplex
Time Multiplex Architecture

Max-log-MAP Operating
SISO Algorithm 200 MHz
(Duo-Binary) Frequency
Window Size 32 Iteration 8 (Fixed)
Gate Count 65k Data Rate 24.26 Mbps
 Memory Size Comparison

• Single-Port SRAM Size

– Required for a SISO Decoder
100 % 100.4 %
20.7 %
79.3 %

11
 Energy Consumption Comparison
• For a SISO Decoder @ 1
1.2dB
2dB
100 %
26.2 %
73.8 %

12
 Conclusion

• Border Metric Encoding is Proposed

– Avoid Complex Dummy Calculation
– Effective
Eff ti forf non-binary
bi Turbo
T b Codes
C d

• Dedicated Hardware Interleaver is Proposed

– Generate Interleaved Addresses on-the-fly

• CTC Decoder for WiMAX is Designed

g
– Based on ..
• Border Metric Encoding
g
• Dedicated Hardware Interleaver
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